sim/testsuite/aarch64/fcvtz.s

   1 # mach: aarch64
   2
   3 # Check the FP convert to int round toward zero instructions: fcvtszs32,
   4 # fcvtszs, fcvtszd32, fcvtszd, fcvtzu.
   5 # For 32-bit signed convert, test values -1.5, INT_MAX, and INT_MIN.
   6 # For 64-bit signed convert, test values -1.5, LONG_MAX, and LONG_MIN.
   7 # For 32-bit unsigned convert, test values 1.5, INT_MAX, and UINT_MAX.
   8 # For 64-bit unsigned convert, test values 1.5, LONG_MAX, and ULONG_MAX.
   9
  10         .data
  11         .align 4
  12 fm1p5:
  13         .word   3217031168
  14 fimax:
  15         .word   1325400064
  16 fimin:
  17         .word   3472883712
  18 flmax:
  19         .word   1593835520
  20 flmin:
  21         .word   3741319168
  22 f1p5:
  23         .word   1069547520
  24 fuimax:
  25         .word   1333788672
  26 fulmax:
  27         .word   1602224128
  28
  29 dm1p5:
  30         .word   0
  31         .word   -1074266112
  32 dimax:
  33         .word   4290772992
  34         .word   1105199103
  35 dimin:
  36         .word   0
  37         .word   -1042284544
  38 dlmax:
  39         .word   0
  40         .word   1138753536
  41 dlmin:
  42         .word   0
  43         .word   -1008730112
  44 d1p5:
  45         .word   0
  46         .word   1073217536
  47 duimax:
  48         .word   4292870144
  49         .word   1106247679
  50 dulmax:
  51         .word   0
  52         .word   1139802112
  53
  54 .include "testutils.inc"
  55
  56         start
  57         adrp x0, fm1p5
  58         ldr s0, [x0, #:lo12:fm1p5]
  59         fcvtzs w1, s0
  60         cmp w1, #-1
  61         bne .Lfailure
  62         adrp x0, fimax
  63         ldr s0, [x0, #:lo12:fimax]
  64         fcvtzs w1, s0
  65         mov w2, #0x7fffffff
  66         cmp w1, w2
  67         bne .Lfailure
  68         adrp x0, fimin
  69         ldr s0, [x0, #:lo12:fimin]
  70         fcvtzs w1, s0
  71         mov w2, #0x80000000
  72         cmp w1, w2
  73         bne .Lfailure
  74
  75         adrp x0, fm1p5
  76         ldr s0, [x0, #:lo12:fm1p5]
  77         fcvtzs x1, s0
  78         cmp x1, #-1
  79         bne .Lfailure
  80         adrp x0, flmax
  81         ldr s0, [x0, #:lo12:flmax]
  82         fcvtzs x1, s0
  83         mov x2, #0x7fffffffffffffff
  84         cmp x1, x2
  85         bne .Lfailure
  86         adrp x0, flmin
  87         ldr s0, [x0, #:lo12:flmin]
  88         fcvtzs x1, s0
  89         mov x2, #0x8000000000000000
  90         cmp x1, x2
  91         bne .Lfailure
  92
  93         adrp x0, dm1p5
  94         ldr d0, [x0, #:lo12:dm1p5]
  95         fcvtzs w1, d0
  96         cmp w1, #-1
  97         bne .Lfailure
  98         adrp x0, dimax
  99         ldr d0, [x0, #:lo12:dimax]
 100         fcvtzs w1, d0
 101         mov w2, #0x7fffffff
 102         cmp w1, w2
 103         bne .Lfailure
 104         adrp x0, dimin
 105         ldr d0, [x0, #:lo12:dimin]
 106         fcvtzs w1, d0
 107         mov w2, #0x80000000
 108         cmp w1, w2
 109         bne .Lfailure
 110
 111         adrp x0, dm1p5
 112         ldr d0, [x0, #:lo12:dm1p5]
 113         fcvtzs x1, d0
 114         cmp x1, #-1
 115         bne .Lfailure
 116         adrp x0, dlmax
 117         ldr d0, [x0, #:lo12:dlmax]
 118         fcvtzs x1, d0
 119         mov x2, #0x7fffffffffffffff
 120         cmp x1, x2
 121         bne .Lfailure
 122         adrp x0, dlmin
 123         ldr d0, [x0, #:lo12:dlmin]
 124         fcvtzs x1, d0
 125         mov x2, #0x8000000000000000
 126         cmp x1, x2
 127         bne .Lfailure
 128
 129         adrp x0, f1p5
 130         ldr s0, [x0, #:lo12:f1p5]
 131         fcvtzu w1, s0
 132         cmp w1, #1
 133         bne .Lfailure
 134         adrp x0, fimax
 135         ldr s0, [x0, #:lo12:fimax]
 136         fcvtzu w1, s0
 137         mov w2, #0x80000000
 138         cmp w1, w2
 139         bne .Lfailure
 140         adrp x0, fuimax
 141         ldr s0, [x0, #:lo12:fuimax]
 142         fcvtzu w1, s0
 143         mov w2, #0xffffffff
 144         cmp w1, w2
 145         bne .Lfailure
 146
 147         adrp x0, f1p5
 148         ldr s0, [x0, #:lo12:f1p5]
 149         fcvtzu x1, s0
 150         cmp x1, #1
 151         bne .Lfailure
 152         adrp x0, flmax
 153         ldr s0, [x0, #:lo12:flmax]
 154         fcvtzu x1, s0
 155         mov x2, #0x8000000000000000
 156         cmp x1, x2
 157         bne .Lfailure
 158         adrp x0, fulmax
 159         ldr s0, [x0, #:lo12:fulmax]
 160         fcvtzu x1, s0
 161         mov x2, #0xffffffffffffffff
 162         cmp x1, x2
 163         bne .Lfailure
 164
 165         adrp x0, d1p5
 166         ldr d0, [x0, #:lo12:d1p5]
 167         fcvtzu w1, d0
 168         cmp w1, #1
 169         bne .Lfailure
 170         adrp x0, dimax
 171         ldr d0, [x0, #:lo12:dimax]
 172         fcvtzu w1, d0
 173         mov w2, #0x7fffffff
 174         cmp w1, w2
 175         bne .Lfailure
 176         adrp x0, duimax
 177         ldr d0, [x0, #:lo12:duimax]
 178         fcvtzu w1, d0
 179         mov w2, #0xffffffff
 180         cmp w1, w2
 181         bne .Lfailure
 182
 183         adrp x0, d1p5
 184         ldr d0, [x0, #:lo12:d1p5]
 185         fcvtzu x1, d0
 186         cmp x1, #1
 187         bne .Lfailure
 188         adrp x0, dlmax
 189         ldr d0, [x0, #:lo12:dlmax]
 190         fcvtzu x1, d0
 191         mov x2, #0x8000000000000000
 192         cmp x1, x2
 193         bne .Lfailure
 194         adrp x0, dulmax
 195         ldr d0, [x0, #:lo12:dulmax]
 196         fcvtzu x1, d0
 197         mov x2, #0xffffffffffffffff
 198         cmp x1, x2
 199         bne .Lfailure
 200
 201         pass
 202 .Lfailure:
 203         fail