sim/testsuite/aarch64/ldnr.s

   1 # mach: aarch64
   2
   3 # Check the load single 1-element structure and replicate to all lanes insns:
   4 # ld1r, ld2r, ld3r, ld4r.
   5 # Check the addressing modes: no offset, post-index immediate offset,
   6 # post-index register offset.
   7
   8 .include "testutils.inc"
   9
  10         .data
  11         .align 4
  12 input:
  13         .word 0x04030201
  14         .word 0x08070605
  15         .word 0x0c0b0a09
  16         .word 0x100f0e0d
  17 input2:
  18         .word 0x00000001
  19         .word 0x00000002
  20         .word 0x00000003
  21         .word 0x00000004
  22         .word 0x00000005
  23         .word 0x00000006
  24         .word 0x00000007
  25         .word 0x00000008
  26         .word 0x00000009
  27         .word 0x0000000a
  28         .word 0x0000000b
  29         .word 0x0000000c
  30
  31         start
  32         adrp x0, input
  33         add x0, x0, :lo12:input
  34         adrp x1, input2
  35         add x1, x1, :lo12:input2
  36
  37         mov x2, x0
  38         mov x3, #1
  39         ld1r {v0.8b}, [x2], 1
  40         ld1r {v1.16b}, [x2], x3
  41         ld1r {v2.4h}, [x2], 2
  42         ld1r {v3.8h}, [x2]
  43         addv b0, v0.8b
  44         addv b1, v1.16b
  45         addv b2, v2.8b
  46         addv b3, v3.16b
  47         mov x2, v0.d[0]
  48         mov x3, v1.d[0]
  49         mov x4, v2.d[0]
  50         mov x5, v3.d[0]
  51         cmp x2, #8
  52         bne .Lfailure
  53         cmp x3, #32
  54         bne .Lfailure
  55         cmp x4, #28
  56         bne .Lfailure
  57         cmp x5, #88
  58         bne .Lfailure
  59
  60         mov x2, x1
  61         mov x3, #8
  62         ld2r {v0.2s, v1.2s}, [x2], 8
  63         ld2r {v2.4s, v3.4s}, [x2], x3
  64         ld2r {v4.1d, v5.1d}, [x2], 16
  65         ld2r {v6.2d, v7.2d}, [x2]
  66         addp v0.2s, v0.2s, v1.2s
  67         addv s2, v2.4s
  68         addv s3, v3.4s
  69         addp v4.2s, v4.2s, v5.2s
  70         addv s6, v6.4s
  71         addv s7, v7.4s
  72         mov w2, v0.s[0]
  73         mov w3, v0.s[1]
  74         mov x4, v2.d[0]
  75         mov x5, v3.d[0]
  76         mov w6, v4.s[0]
  77         mov w7, v4.s[1]
  78         mov x8, v6.d[0]
  79         mov x9, v7.d[0]
  80         cmp w2, #2
  81         bne .Lfailure
  82         cmp w3, #4
  83         bne .Lfailure
  84         cmp x4, #12
  85         bne .Lfailure
  86         cmp x5, #16
  87         bne .Lfailure
  88         cmp w6, #11
  89         bne .Lfailure
  90         cmp w7, #15
  91         bne .Lfailure
  92         cmp x8, #38
  93         bne .Lfailure
  94         cmp x9, #46
  95         bne .Lfailure
  96
  97         mov x2, x0
  98         mov x3, #3
  99         ld3r {v0.8b, v1.8b, v2.8b}, [x2], 3
 100         ld3r {v3.8b, v4.8b, v5.8b}, [x2], x3
 101         ld3r {v6.8b, v7.8b, v8.8b}, [x2]
 102         addv b0, v0.8b
 103         addv b1, v1.8b
 104         addv b2, v2.8b
 105         addv b3, v3.8b
 106         addv b4, v4.8b
 107         addv b5, v5.8b
 108         addv b6, v6.8b
 109         addv b7, v7.8b
 110         addv b8, v8.8b
 111         addv b9, v9.8b
 112         mov x2, v0.d[0]
 113         mov x3, v1.d[0]
 114         mov x4, v2.d[0]
 115         mov x5, v3.d[0]
 116         mov x6, v4.d[0]
 117         mov x7, v5.d[0]
 118         mov x8, v6.d[0]
 119         mov x9, v7.d[0]
 120         mov x10, v8.d[0]
 121         cmp x2, #8
 122         bne .Lfailure
 123         cmp x3, #16
 124         bne .Lfailure
 125         cmp x4, #24
 126         bne .Lfailure
 127         cmp x5, #32
 128         bne .Lfailure
 129         cmp x6, #40
 130         bne .Lfailure
 131         cmp x7, #48
 132         bne .Lfailure
 133         cmp x8, #56
 134         bne .Lfailure
 135         cmp x9, #64
 136         bne .Lfailure
 137         cmp x10, #72
 138         bne .Lfailure
 139
 140         mov x2, x1
 141         ld4r {v0.4s, v1.4s, v2.4s, v3.4s}, [x2], 16
 142         ld4r {v4.4s, v5.4s, v6.4s, v7.4s}, [x2]
 143         addv s0, v0.4s
 144         addv s1, v1.4s
 145         addv s2, v2.4s
 146         addv s3, v3.4s
 147         addv s4, v4.4s
 148         addv s5, v5.4s
 149         addv s6, v6.4s
 150         addv s7, v7.4s
 151         mov x2, v0.d[0]
 152         mov x3, v1.d[0]
 153         mov x4, v2.d[0]
 154         mov x5, v3.d[0]
 155         mov x6, v4.d[0]
 156         mov x7, v5.d[0]
 157         mov x8, v6.d[0]
 158         mov x9, v7.d[0]
 159         cmp x2, #4
 160         bne .Lfailure
 161         cmp x3, #8
 162         bne .Lfailure
 163         cmp x4, #12
 164         bne .Lfailure
 165         cmp x5, #16
 166         bne .Lfailure
 167         cmp x6, #20
 168         bne .Lfailure
 169         cmp x7, #24
 170         bne .Lfailure
 171         cmp x8, #28
 172         bne .Lfailure
 173         cmp x9, #32
 174         bne .Lfailure
 175
 176         pass
 177 .Lfailure:
 178         fail