sim/testsuite/aarch64/stn_multiple.s

   1 # mach: aarch64
   2
   3 # Check the store multiple structure instructions: st1, st2, st3, st4.
   4 # Check the addressing modes: no offset, post-index immediate offset,
   5 # post-index register offset.
   6
   7 .include "testutils.inc"
   8
   9         .data
  10         .align 4
  11 input:
  12         .word 0x04030201
  13         .word 0x08070605
  14         .word 0x0c0b0a09
  15         .word 0x100f0e0d
  16         .word 0xfcfdfeff
  17         .word 0xf8f9fafb
  18         .word 0xf4f5f6f7
  19         .word 0xf0f1f2f3
  20 output:
  21         .zero 64
  22
  23         start
  24         adrp x0, input
  25         add x0, x0, :lo12:input
  26         adrp x1, output
  27         add x1, x1, :lo12:output
  28
  29         mov x2, x0
  30         ldr q0, [x2], 16
  31         ldr q1, [x2]
  32         mov x2, x0
  33         ldr q2, [x2], 16
  34         ldr q3, [x2]
  35
  36         mov x2, x1
  37         mov x3, #16
  38         st1 {v0.16b}, [x2], 16
  39         st1 {v1.8h}, [x2], x3
  40         mov x2, x1
  41         ldr q4, [x2], 16
  42         ldr q5, [x2]
  43         addv b4, v4.16b
  44         addv b5, v5.16b
  45         mov x4, v4.d[0]
  46         cmp x4, #136
  47         bne .Lfailure
  48         mov x5, v5.d[0]
  49         cmp x5, #120
  50         bne .Lfailure
  51
  52         mov x2, x1
  53         mov x3, #16
  54         st2 {v0.8b, v1.8b}, [x2], 16
  55         st2 {v2.4h, v3.4h}, [x2], x3
  56         mov x2, x1
  57         ldr q4, [x2], 16
  58         ldr q5, [x2]
  59         addv b4, v4.16b
  60         addv b5, v5.16b
  61         mov x4, v4.d[0]
  62         cmp x4, #0
  63         bne .Lfailure
  64         mov x5, v5.d[0]
  65         cmp x5, #0
  66         bne .Lfailure
  67
  68         mov x2, x1
  69         st3 {v0.4s, v1.4s, v2.4s}, [x2]
  70         ldr q4, [x2], 16
  71         ldr q5, [x2], 16
  72         ldr q6, [x2]
  73         addv b4, v4.16b
  74         addv b5, v5.16b
  75         addv b6, v6.16b
  76         mov x4, v4.d[0]
  77         cmp x4, #36
  78         bne .Lfailure
  79         mov x5, v5.d[0]
  80         cmp x5, #0
  81         bne .Lfailure
  82         mov x6, v6.d[0]
  83         cmp x6, #100
  84         bne .Lfailure
  85
  86         mov x2, x1
  87         st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2]
  88         ldr q4, [x2], 16
  89         ldr q5, [x2], 16
  90         ldr q6, [x2], 16
  91         ldr q7, [x2]
  92         addv b4, v4.16b
  93         addv b5, v5.16b
  94         addv b6, v6.16b
  95         addv b7, v7.16b
  96         mov x4, v4.d[0]
  97         cmp x4, #0
  98         bne .Lfailure
  99         mov x5, v5.d[0]
 100         cmp x5, #0
 101         bne .Lfailure
 102         mov x6, v6.d[0]
 103         cmp x6, #0
 104         bne .Lfailure
 105         mov x7, v7.d[0]
 106         cmp x7, #0
 107         bne .Lfailure
 108
 109         pass
 110
 111         mov x2, x1
 112         st1 {v0.2s, v1.2s}, [x2], 16
 113         st1 {v2.1d, v3.1d}, [x2]
 114         mov x2, x1
 115         ldr q4, [x2], 16
 116         ldr q5, [x2]
 117         addv b4, v4.16b
 118         addv b5, v5.16b
 119         mov x4, v4.d[0]
 120         cmp x4, #0
 121         bne .Lfailure
 122         mov x5, v5.d[0]
 123         cmp x5, #0
 124         bne .Lfailure
 125
 126         mov x2, x1
 127         st1 {v0.2d, v1.2d, v2.2d}, [x2]
 128         mov x2, x1
 129         ldr q4, [x2], 16
 130         ldr q5, [x2], 16
 131         ldr q6, [x2]
 132         addv b4, v4.16b
 133         addv b5, v5.16b
 134         addv b6, v6.16b
 135         mov x4, v4.d[0]
 136         cmp x4, #136
 137         bne .Lfailure
 138         mov x5, v5.d[0]
 139         cmp x5, #120
 140         bne .Lfailure
 141         mov x6, v6.d[0]
 142         cmp x6, #136
 143         bne .Lfailure
 144
 145         mov x2, x1
 146         st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2]
 147         mov x2, x1
 148         ldr q4, [x2], 16
 149         ldr q5, [x2], 16
 150         ldr q6, [x2], 16
 151         ldr q7, [x2]
 152         addv b4, v4.16b
 153         addv b5, v5.16b
 154         addv b6, v6.16b
 155         addv b7, v7.16b
 156         mov x4, v4.d[0]
 157         cmp x4, #136
 158         bne .Lfailure
 159         mov x5, v5.d[0]
 160         cmp x5, #120
 161         bne .Lfailure
 162         mov x6, v6.d[0]
 163         cmp x6, #136
 164         bne .Lfailure
 165         mov x7, v7.d[0]
 166         cmp x7, #120
 167         bne .Lfailure
 168
 169         pass
 170 .Lfailure:
 171         fail