sim/testsuite/bfin/se_illegalcombination.S

   1 //Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp
   2 // Description: Multi-issue Illegal Combinations
   3 # mach: bfin
   4 # sim: --environment operating
   5 # xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-*
   6
   7 #include "test.h"
   8 .include "testutils.inc"
   9 start
  10
  11 //
  12 // Constants and Defines
  13 //
  14
  15 include(gen_int.inc)
  16 include(selfcheck.inc)
  17 include(std.inc)
  18 include(mmrs.inc)
  19 include(symtable.inc)
  20
  21 #ifndef STACKSIZE
  22 #define STACKSIZE 0x100   // change for how much stack you need
  23 #endif
  24 #ifndef ITABLE
  25 #define ITABLE 0xF0000000
  26 #endif
  27
  28 GEN_INT_INIT(ITABLE) // set location for interrupt table
  29
  30 //
  31 // Reset/Bootstrap Code
  32 //   (Here we should set the processor operating modes, initialize registers,
  33 //    etc.)
  34 //
  35
  36 BOOT:
  37 INIT_R_REGS(0);     // initialize general purpose regs
  38
  39 INIT_P_REGS(0);     // initialize the pointers
  40
  41 INIT_I_REGS(0);     // initialize the dsp address regs
  42 INIT_M_REGS(0);
  43 INIT_L_REGS(0);
  44 INIT_B_REGS(0);
  45
  46 CLI R1;           // inhibit events during MMR writes
  47
  48 LD32_LABEL(sp, USTACK);   // setup the user stack pointer
  49 USP = SP;
  50
  51 LD32_LABEL(sp, KSTACK);   // setup the kernel stack pointer
  52 FP = SP;        // and frame pointer
  53
  54 LD32(p0, EVT0);      // Setup Event Vectors and Handlers
  55
  56     P0 += 4;            // EVT0 not used (Emulation)
  57
  58     P0 += 4;            // EVT1 not used (Reset)
  59
  60 LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
  61     [ P0 ++ ] = R0;
  62
  63 LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
  64     [ P0 ++ ] = R0;
  65
  66     P0 += 4;            // EVT4 not used (Global Interrupt Enable)
  67
  68 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
  69     [ P0 ++ ] = R0;
  70
  71 LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
  72     [ P0 ++ ] = R0;
  73
  74 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
  75     [ P0 ++ ] = R0;
  76
  77 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
  78     [ P0 ++ ] = R0;
  79
  80 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
  81     [ P0 ++ ] = R0;
  82
  83 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
  84     [ P0 ++ ] = R0;
  85
  86 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
  87     [ P0 ++ ] = R0;
  88
  89 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
  90     [ P0 ++ ] = R0;
  91
  92 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
  93     [ P0 ++ ] = R0;
  94
  95 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
  96     [ P0 ++ ] = R0;
  97
  98 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
  99     [ P0 ++ ] = R0;
 100
 101 LD32(p0, EVT_OVERRIDE);
 102     R0 = 0;
 103     [ P0 ++ ] = R0;
 104
 105     R1 = -1;     // Change this to mask interrupts (*)
 106 CSYNC;       // wait for MMR writes to finish
 107 STI R1;      // sync and reenable events (implicit write to IMASK)
 108
 109 DUMMY:
 110
 111     A0 = 0;         // reset accumulators
 112     A1 = 0;
 113
 114     R0 = 0 (Z);
 115
 116 LT0 = r0;       // set loop counters to something deterministic
 117 LB0 = r0;
 118 LC0 = r0;
 119 LT1 = r0;
 120 LB1 = r0;
 121 LC1 = r0;
 122
 123 ASTAT = r0;     // reset other internal regs
 124 SYSCFG = r0;
 125 RETS = r0;      // prevent X's breaking LINK instruction
 126
 127 // The following code sets up the test for running in USER mode
 128
 129 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
 130                         // ReturnFromInterrupt (RTI)
 131 RETI = r0;      // We need to load the return address
 132
 133 // Comment the following line for a USER Mode test
 134
 135 JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
 136
 137 RTI;
 138
 139 STARTSUP:
 140 LD32_LABEL(p1, BEGIN);
 141
 142 LD32(p0, EVT15);
 143
 144 CLI R1;   // inhibit events during write to MMR
 145     [ P0 ] = P1;  // IVG15 (General) handler (Int 15) load with start
 146 CSYNC;      // wait for it
 147 STI R1;     // reenable events with proper imask
 148
 149 RAISE 15;       // after we RTI, INT 15 should be taken
 150
 151 RTI;
 152
 153 //
 154 // The Main Program
 155 //
 156
 157 STARTUSER:
 158
 159 LINK 0;     // change for how much stack frame space you need.
 160
 161 JUMP BEGIN;
 162
 163 //*********************************************************************
 164
 165 BEGIN:
 166
 167                 // COMMENT the following line for USER MODE tests
 168     [ -- SP ] = RETI;  // enable interrupts in supervisor mode
 169
 170                 // **** YOUR CODE GOES HERE ****
 171
 172     // PUT YOUR TEST HERE!
 173
 174 // Slot 0 can only be LDST LOAD with search instruction (2 instrs)
 175
 176
 177  .dw 0xcc0d     //(R0,R1)=SEARCH R2(GT)||[P0]=R3||NOP;
 178  .dw 0x0210
 179  .dw 0x9303
 180  .dw 0x0000
 181 // (r0,r1) = search r2 gt, nop, r3 = [i0]; // nop supposedly ok
 182 ( R0 , R1 ) = SEARCH R2 (GT) || R4 = [ P0 ++ P1 ] || NOP;
 183
 184 // only nop or dspLDST allowed in slot 1 (1 instr)
 185
 186   // a0 = r0, nop, [p0] = r3;
 187   .dw 0xCC09;   // can't assemble
 188   .dw 0x2000;
 189   .dw 0x0000;
 190   .dw 0x9303;
 191
 192 // Slot 0 illegal opcodes (1 instr)
 193
 194   // a0 = r0, raise 15, nop;
 195   .dw 0xCC09;   // can't assemble
 196   .dw 0x2000;
 197   .dw 0x009F;
 198   .dw 0x0000;
 199
 200 // multiissue with two stores (8 instrs)
 201
 202
 203  .dw 0xcc09     //A0=R0||W[P3]=R5.L||[I0]=R4;
 204  .dw 0x2000
 205  .dw 0x8b5b
 206  .dw 0x9f04
 207
 208  .dw 0xcc09     //A0=R0||[I2]=R2||[I0]=R4;
 209  .dw 0x2000
 210  .dw 0x9f12
 211  .dw 0x9f04
 212
 213  .dw 0xcc09     //A0=R0||[P3]=R0||[I0]=R4;
 214  .dw 0x2000
 215  .dw 0x9318
 216  .dw 0x9f04
 217
 218  .dw 0xcc09     //A0=R0||[P3]=P0||[I0]=R4;
 219  .dw 0x2000
 220  .dw 0x9358
 221  .dw 0x9f04
 222
 223  .dw 0xcc09     //A0=R0||[FP+-36]=R0||[I0]=R4;
 224  .dw 0x2000
 225  .dw 0xbb70
 226  .dw 0x9f04
 227
 228  .dw 0xcc09     //A0=R0||[FP+-48]=P0||[I0]=R4;
 229  .dw 0x2000
 230  .dw 0xbb48
 231  .dw 0x9f04
 232
 233  .dw 0xcc09     //A0=R0||[P3+0x20]=R1||[I0]=R4;
 234  .dw 0x2000
 235  .dw 0xb219
 236  .dw 0x9f04
 237
 238  .dw 0xcc09     //A0=R0||[P3+0x20]=P1||[I0]=R4;
 239  .dw 0x2000
 240  .dw 0xbe19
 241  .dw 0x9f04
 242
 243 // multiissue two instructions can't modify same ireg (6 instrs)
 244
 245
 246  .dw 0xcc09     //A0=R0||I0+=M1(BREV)||R1.L=W[I0++];
 247  .dw 0x2000
 248  .dw 0x9ee4
 249  .dw 0x9c21
 250
 251  .dw 0xcc09     //A0=R0||I1-=M3||R0=[I1++M3];
 252  .dw 0x2000
 253  .dw 0x9e7d
 254  .dw 0x9de8
 255
 256  .dw 0xcc09     //A0=R0||I2+=2||W[I2++]=R0.L;
 257  .dw 0x2000
 258  .dw 0x9f62
 259  .dw 0x9e30
 260
 261  .dw 0xcc09     //A0=R0||I3-=4||[I3++M1]=R7;
 262  .dw 0x2000
 263  .dw 0x9f6f
 264  .dw 0x9fbf
 265
 266  .dw 0xcc09     //A0=R0||R1.L=W[I1++]||W[I1++]=R2.L;
 267  .dw 0x2000
 268  .dw 0x9c29
 269  .dw 0x9e2a
 270
 271  .dw 0xcc09     //A0=R0||[I2++M3]=R7||R6=[I2++M0];
 272  .dw 0x2000
 273  .dw 0x9ff7
 274  .dw 0x9d96
 275
 276 // multiissue two instructions can't load same dreg (9 instrs)
 277
 278
 279  .dw 0xcc09     //A0=R0||R0.L=W[P0++P2]||R0=[I0++];
 280  .dw 0x2000
 281  .dw 0x8210
 282  .dw 0x9c00
 283
 284  .dw 0xcc09     //A0=R0||R1=W[P0++P3](X)||R1.L=W[I2];
 285  .dw 0x2000
 286  .dw 0x8e58
 287  .dw 0x9d31
 288
 289  .dw 0xcc09     //A0=R0||R2=W[P0++P3](X)||R2=[I1++M3];
 290  .dw 0x2000
 291  .dw 0x8e98
 292  .dw 0x9dea
 293
 294  .dw 0xcc09     //A0=R0||R3=[I0++]||R3=[I1++];
 295  .dw 0x2000
 296  .dw 0x9c03
 297  .dw 0x9c0b
 298
 299  .dw 0xcc09     //A0=R0||R4.L=W[I2]||R4.L=W[I3];
 300  .dw 0x2000
 301  .dw 0x9d34
 302  .dw 0x9d3c
 303
 304  .dw 0xcc09     //A0=R0||R5=[I1++M3]||R5.L=W[I2++];
 305  .dw 0x2000
 306  .dw 0x9ded
 307  .dw 0x9c35
 308
 309  .dw 0xcc09     //A0=R0||R6=[P0]||R6=[I0++];
 310  .dw 0x2000
 311  .dw 0x9106
 312  .dw 0x9c06
 313
 314  .dw 0xcc09     //A0=R0||R7=[FP+-56]||R7.L=W[I1];
 315  .dw 0x2000
 316  .dw 0xb927
 317  .dw 0x9d2f
 318
 319  .dw 0xcc09     //A0=R0||R0=W[P1+0x1e](X)||R0=[I0++];
 320  .dw 0x2000
 321  .dw 0xabc8
 322  .dw 0x9c00
 323
 324 // dsp32alu instructions with one dest and slot 0 multi with same dest (1 ins)
 325
 326
 327  .dw 0xcc00     //R0=R2+|+R3||R0=W[P1+0x1e](X)||NOP;
 328  .dw 0x0013
 329  .dw 0xabc8
 330  .dw 0x0000
 331         // other slot 0 dreg cases already covered
 332
 333 // dsp32alu one dest and slot 1 multi with same dest (1 ins)
 334
 335
 336  .dw 0xcc18     //R1=BYTEPACK(R4,R5)||NOP||R1.L=W[I2];
 337  .dw 0x0225
 338  .dw 0x0000
 339  .dw 0x9d31
 340         // other slot 1 dreg dest cases already covered
 341
 342 // dsp32alu dual dests and slot 0 multi with either same dest (2 instrs)
 343
 344
 345  .dw 0xcc18     //(R2,R3)=BYTEUNPACKR1:0||R2=W[P0++P3](X)||NOP;
 346  .dw 0x4680
 347  .dw 0x8e98
 348  .dw 0x0000
 349
 350  .dw 0xcc01     //R2=R2+|+R3,R3=R2-|-R3||R3=[P3]||NOP;
 351  .dw 0x0693
 352  .dw 0x911b
 353  .dw 0x0000
 354
 355 // dsp32alu dual dests and slot 1 multi with either same dest (2 instrs)
 356
 357
 358  .dw 0xcc18     //(R4,R5)=BYTEUNPACKR1:0||NOP||R4=[I1++M3];
 359  .dw 0x4b00
 360  .dw 0x0000
 361  .dw 0x9dec
 362
 363  .dw 0xcc01     //R4=R2+|+R3,R5=R2-|-R3||NOP||R5.L=W[I2++];
 364  .dw 0x0b13
 365  .dw 0x0000
 366  .dw 0x9c35
 367
 368 // dsp32shift one dest and slot 0 multi with same dest (1 instruction)
 369
 370
 371  .dw 0xce0d     //R6=ALIGN8(R4,R5)||R6=[P0]||NOP;
 372  .dw 0x0c2c
 373  .dw 0x9106
 374  .dw 0x0000
 375
 376 // dsp32shift one dest and slot 1 multi with same dest (1 instruction)
 377
 378
 379  .dw 0xce00     //R7.L=ASHIFTR0.HBYR7.L||NOP||R7.L=W[I1];
 380  .dw 0x1e38
 381  .dw 0x0000
 382  .dw 0x9d2f
 383
 384 // dsp32shift two dests and slot 0 multi with either same dest (2 instrs)
 385
 386
 387  .dw 0xce08     //BITMUX(R0,R1,A0)(ASR)||R0.L=W[P0++P2]||NOP;
 388  .dw 0x0001
 389  .dw 0x8210
 390  .dw 0x0000
 391
 392  .dw 0xce08     //BITMUX(R2,R3,A0)(ASL)||R3=[I0++]||NOP;
 393  .dw 0x4013
 394  .dw 0x9c03
 395  .dw 0x0000
 396
 397 // dsp32shift two dests and slot 1 multi with either same dest (2 instrs)
 398
 399
 400  .dw 0xce08     //BITMUX(R4,R5,A0)(ASR)||NOP||R4.H=W[I3];
 401  .dw 0x0025
 402  .dw 0x0000
 403  .dw 0x9d5c
 404
 405  .dw 0xce08     //BITMUX(R6,R7,A0)(ASL)||NOP||R7.L=W[I1];
 406  .dw 0x4037
 407  .dw 0x0000
 408  .dw 0x9d2f
 409
 410 // dsp32shiftimm one dest and slot 0 with same dest (1 instr)
 411
 412
 413  .dw 0xce80     //R1.L=R0.H<<0x7||R1=W[P0++P3](X)||NOP;
 414  .dw 0x1238
 415  .dw 0x8e58
 416  .dw 0x0000
 417
 418 // dsp32shiftimm one dest and slot 1 with same dest (1 instr)
 419
 420
 421  .dw 0xce81     //R5=R2<<0x9(V)||NOP||R5.L=W[I2++];
 422  .dw 0x0a4a
 423  .dw 0x0000
 424  .dw 0x9c35
 425
 426 // dsp32mac one dest and slot 0 multi with same dest (1 inst)
 427
 428
 429  .dw 0xc805     //A0+=R1.H*R0.L,R6.H=(A1+=R1.L*R0.H)||R6=W[P0++P3](X)||NOP;
 430  .dw 0x4d88
 431  .dw 0x8f98
 432  .dw 0x0000
 433
 434 // dsp32mult one dest and slot 0 multi with same dest (1 inst)
 435
 436
 437  .dw 0xca04     //R7.H=R3.L*R4.H||R7=[FP+-56]||NOP;
 438  .dw 0x41dc
 439  .dw 0xb927
 440  .dw 0x0000
 441
 442 // dsp32 mac one dest and slot 1 multi with same dest (1 inst)
 443
 444
 445  .dw 0xc805     //A0+=R1.H*R0.L,R0.H=(A1+=R1.L*R0.H)||NOP||R0=[I0++];
 446  .dw 0x4c08
 447  .dw 0x0000
 448  .dw 0x9c00
 449
 450 // dsp32mult one dest and slot 1 multi with same dest (1 inst)
 451
 452
 453  .dw 0xca04     //R1.H=R3.L*R4.H||NOP||R1.H=W[I1];
 454  .dw 0x405c
 455  .dw 0x0000
 456  .dw 0x9d49
 457
 458 // dsp32mac write to register pair and slot 0 same dest - even (1 instr)
 459
 460
 461  .dw 0xc80d     //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||R2=W[P0++P3](X)||NOP;
 462  .dw 0x6c88
 463  .dw 0x8e98
 464  .dw 0x0000
 465
 466 // dsp32mult write to register pair and slot 0 same dest - even (1 instr)
 467
 468
 469  .dw 0xca0c     //R5=R1.L*R0.H,R4=R1.H*R0.L||R4=[P0++P1]||NOP;
 470  .dw 0x6508
 471  .dw 0x8108
 472  .dw 0x0000
 473
 474 // dsp32mac write to register pair and slot 1 same dest - even (1 instr)
 475
 476
 477  .dw 0xc80d     //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||NOP||R2=[I1++M3];
 478  .dw 0x6c88
 479  .dw 0x0000
 480  .dw 0x9dea
 481
 482 // dsp32mult write to register pair and slot 1 same dest - even (1 instr)
 483
 484
 485  .dw 0xca0c     //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R4=[I1++M3];
 486  .dw 0x6508
 487  .dw 0x0000
 488  .dw 0x9dec
 489
 490 // dsp32mac write to register pair and slot 0 same dest - odd (1 instr)
 491
 492
 493  .dw 0xc80d     //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||R3=W[P0++P3](X)||NOP;
 494  .dw 0x4c88
 495  .dw 0x8ed8
 496  .dw 0x0000
 497
 498 // dsp32mult write to register pair and slot 0 same dest - odd (1 instr)
 499
 500
 501  .dw 0xca0c     //R5=R1.L*R0.H,R4=R1.H*R0.L||R5=[P0++P1]||NOP;
 502  .dw 0x6508
 503  .dw 0x8148
 504  .dw 0x0000
 505
 506 // dsp32mac write to register pair and slot 1 same dest - odd (1 instr)
 507
 508
 509  .dw 0xc80d     //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||NOP||R3=[I1++M3];
 510  .dw 0x4c88
 511  .dw 0x0000
 512  .dw 0x9deb
 513
 514 // dsp32mult write to register pair and slot 1 same dest - odd (1 instr)
 515
 516
 517  .dw 0xca0c     //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R5=[I1++M3];
 518  .dw 0x6508
 519  .dw 0x0000
 520  .dw 0x9ded
 521
 522 // CHECKER
 523
 524 CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
 525                     // Xhandler counts all EXCAUSE = 0x22;
 526 CHECKREG(r5, 53); // count of all Illegal Combination Exceptions.
 527
 528 END:
 529 dbg_pass;            // End the test
 530
 531 //*********************************************************************
 532
 533 //
 534 // Handlers for Events
 535 //
 536
 537 NHANDLE:            // NMI Handler 2
 538 RTN;
 539
 540 XHANDLE:            // Exception Handler 3
 541                     // 16 bit illegal opcode handler - skips bad instruction
 542
 543     [ -- SP ] = ASTAT; // save what we damage
 544     [ -- SP ] = ( R7:6 );
 545     R7 = SEQSTAT;
 546     R7 <<= 26;
 547     R7 >>= 26;      // only want EXCAUSE
 548     R6 = 0x22;      // EXCAUSE 0x22 means I-Fetch Undefined Instruction
 549 CC = r7 == r6;
 550 IF CC JUMP ILLEGALCOMBINATION;   // If EXCAUSE != 0x22 then leave
 551
 552 dbg_fail;
 553 JUMP.S OUT;       // if the EXCAUSE is wrong the test will infinite loop
 554
 555 ILLEGALCOMBINATION:
 556     R7 = RETX;      // Fix up return address
 557
 558     R7 += 8;        // skip offending 64 bit instruction
 559
 560 RETX = r7;      // and put back in RETX
 561
 562     R5 += 1;        // Increment global counter
 563
 564 OUT:
 565     ( R7:6 ) = [ SP ++ ];
 566 ASTAT = [sp++];
 567
 568 RTX;
 569
 570 HWHANDLE:           // HW Error Handler 5
 571 RTI;
 572
 573 THANDLE:            // Timer Handler 6
 574 RTI;
 575
 576 I7HANDLE:           // IVG 7 Handler
 577 RTI;
 578
 579 I8HANDLE:           // IVG 8 Handler
 580 RTI;
 581
 582 I9HANDLE:           // IVG 9 Handler
 583 RTI;
 584
 585 I10HANDLE:          // IVG 10 Handler
 586 RTI;
 587
 588 I11HANDLE:          // IVG 11 Handler
 589 RTI;
 590
 591 I12HANDLE:          // IVG 12 Handler
 592 RTI;
 593
 594 I13HANDLE:          // IVG 13 Handler
 595 RTI;
 596
 597 I14HANDLE:          // IVG 14 Handler
 598 RTI;
 599
 600 I15HANDLE:          // IVG 15 Handler
 601 RTI;
 602
 603
 604     // padding for the icache
 605
 606 EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
 607
 608 //
 609 // Data Segment
 610 //
 611
 612 .data
 613 DATA:
 614     .space (0x10);
 615
 616 // Stack Segments (Both Kernel and User)
 617
 618     .space (STACKSIZE);
 619 KSTACK:
 620
 621     .space (STACKSIZE);
 622 USTACK: