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[binutils-gdb.git] / sim / testsuite / h8300 / addl.s
1 # Hitachi H8 testcase 'add.l'
2 # mach(): h8300h h8300s h8sx
3 # as(h8300h): --defsym sim_cpu=1
4 # as(h8300s): --defsym sim_cpu=2
5 # as(h8sx): --defsym sim_cpu=3
6 # ld(h8300h): -m h8300helf
7 # ld(h8300s): -m h8300self
8 # ld(h8sx): -m h8300sxelf
9
10 .include "testutils.inc"
11
12 # Instructions tested:
13 # add.l xx:3, erd
14 # add.l xx:16, erd
15 # add.l xx:32, erd
16 # add.l xx:16, @erd
17 # add.l xx:16, @erd+
18 # add.l xx:16, @erd-
19 # add.l xx:16, @+erd
20 # add.l xx:16, @-erd
21 # add.l xx:16, @(dd:2, erd)
22 # add.l xx:16, @(dd:16, erd)
23 # add.l xx:16, @(dd:32, erd)
24 # add.l xx:16, @aa:16
25 # add.l xx:16, @aa:32
26 # add.l xx:32, @erd+
27 # add.l xx:32, @erd-
28 # add.l xx:32, @+erd
29 # add.l xx:32, @-erd
30 # add.l xx:32, @(dd:2, erd)
31 # add.l xx:32, @(dd:16, erd)
32 # add.l xx:32, @(dd:32, erd)
33 # add.l xx:32, @aa:16
34 # add.l xx:32, @aa:32
35 # add.l ers, erd
36 # add.l ers, @erd
37 # add.l ers, @erd+
38 # add.l ers, @erd-
39 # add.l ers, @+erd
40 # add.l ers, @-erd
41 # add.l ers, @(dd:2, erd)
42 # add.l ers, @(dd:16, erd)
43 # add.l ers, @(dd:32, erd)
44 # add.l ers, @aa:16
45 # add.l ers, @aa:32
46 # add.l ers, erd
47 # add.l @ers, erd
48 # add.l @ers+, erd
49 # add.l @ers-, erd
50 # add.l @+ers, erd
51 # add.l @-ers, erd
52 # add.l @(dd:2, ers), erd
53 # add.l @(dd:16, ers), erd
54 # add.l @(dd:32, ers), erd
55 # add.l @aa:16, erd
56 # add.l @aa:32, erd
57 # add.l @ers, @erd
58 # add.l @ers+, @erd+
59 # add.l @ers-, @erd-
60 # add.l @+ers, +@erd
61 # add.l @-ers, @-erd
62 # add.l @(dd:2, ers), @(dd:2, erd)
63 # add.l @(dd:16, ers), @(dd:16, erd)
64 # add.l @(dd:32, ers), @(dd:32, erd)
65 # add.l @aa:16, @aa:16
66 # add.l @aa:32, @aa:32
67
68 start
69
70 .data
71 .align 4
72 long_src:
73 .long 0x12345678
74 long_dst:
75 .long 0x87654321
76
77 .text
78
79 ;;
80 ;; Add long from immediate source
81 ;;
82
83 .if (sim_cpu == h8sx)
84 add_l_imm3_to_reg32:
85 set_grs_a5a5 ; Fill all general regs with a fixed pattern
86 set_ccr_zero
87
88 ;; add.l #xx:3, erd
89 add.l #0x3:3, er0 ; Immediate 16-bit operand
90 ;;; .word 0x0ab8
91
92 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
93 test_neg_set
94 test_zero_clear
95 test_ovf_clear
96 test_carry_clear
97
98 test_h_gr32 0xa5a5a5a8 er0
99
100 test_gr_a5a5 1 ; Make sure other general regs not disturbed
101 test_gr_a5a5 2
102 test_gr_a5a5 3
103 test_gr_a5a5 4
104 test_gr_a5a5 5
105 test_gr_a5a5 6
106 test_gr_a5a5 7
107
108 add_l_imm16_to_reg32:
109 set_grs_a5a5 ; Fill all general regs with a fixed pattern
110 set_ccr_zero
111
112 ;; add.l #xx:16, erd
113 add.l #0x1234, er0 ; Immediate 16-bit operand
114 ;;; .word 0x7a18
115 ;;; .word 0x1234
116
117 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
118 test_neg_set
119 test_zero_clear
120 test_ovf_clear
121 test_carry_clear
122
123 test_h_gr32 0xa5a5b7d9 er0
124
125 test_gr_a5a5 1 ; Make sure other general regs not disturbed
126 test_gr_a5a5 2
127 test_gr_a5a5 3
128 test_gr_a5a5 4
129 test_gr_a5a5 5
130 test_gr_a5a5 6
131 test_gr_a5a5 7
132 .endif
133
134 add_l_imm32_to_reg32:
135 set_grs_a5a5 ; Fill all general regs with a fixed pattern
136 set_ccr_zero
137
138 ;; add.l #xx:32, erd
139 add.l #0x12345678, er0 ; Immediate 32-bit operand
140 ;;; .word 0x7a10
141 ;;; .long 0x12345678
142
143 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
144 test_neg_set
145 test_zero_clear
146 test_ovf_clear
147 test_carry_clear
148
149 test_h_gr32 0xb7d9fc1d er0
150
151 test_gr_a5a5 1 ; Make sure other general regs not disturbed
152 test_gr_a5a5 2
153 test_gr_a5a5 3
154 test_gr_a5a5 4
155 test_gr_a5a5 5
156 test_gr_a5a5 6
157 test_gr_a5a5 7
158
159 .if (sim_cpu == h8sx)
160 add_l_imm16_to_indirect:
161 set_grs_a5a5 ; Fill all general regs with a fixed pattern
162 set_ccr_zero
163
164 ;; add.l #xx:16, @erd
165 mov.l #long_dst, er1
166 add.l #0xdead:16, @er1 ; Register indirect operand
167 ;;; .word 0x010e
168 ;;; .word 0x0110
169 ;;; .word 0xdead
170
171 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
172 test_neg_set
173 test_zero_clear
174 test_ovf_clear
175 test_carry_clear
176
177 test_gr_a5a5 0 ; Make sure other general regs not disturbed
178 test_h_gr32 long_dst, er1
179 test_gr_a5a5 2
180 test_gr_a5a5 3
181 test_gr_a5a5 4
182 test_gr_a5a5 5
183 test_gr_a5a5 6
184 test_gr_a5a5 7
185
186 ;; Now check the result of the move to memory.
187 cmp.l #0x876621ce, @long_dst
188 beq .Lnext11
189 fail
190 .Lnext11:
191 mov.l #0x87654321, @long_dst ; Initialize it again for the next use.
192
193 add_l_imm16_to_postinc: ; post-increment from imm16 to mem
194 set_grs_a5a5 ; Fill all general regs with a fixed pattern
195 set_ccr_zero
196
197 ;; add.l #xx:16, @erd+
198 mov.l #long_dst, er1
199 add.l #0xdead:16, @er1+ ; Imm16, register post-incr operands.
200 ;;; .word 0x010e
201 ;;; .word 0x8110
202 ;;; .word 0xdead
203
204 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
205 test_neg_set
206 test_zero_clear
207 test_ovf_clear
208 test_carry_clear
209
210 test_gr_a5a5 0 ; Make sure other general regs not disturbed
211 test_h_gr32 long_dst+4, er1
212 test_gr_a5a5 2
213 test_gr_a5a5 3
214 test_gr_a5a5 4
215 test_gr_a5a5 5
216 test_gr_a5a5 6
217 test_gr_a5a5 7
218
219 ;; Now check the result of the move to memory.
220 cmp.l #0x876621ce, @long_dst
221 beq .Lnext12
222 fail
223 .Lnext12:
224 mov.l #0x87654321, @long_dst ; initialize it again for the next use.
225
226 add_l_imm16_to_postdec: ; post-decrement from imm16 to mem
227 set_grs_a5a5 ; Fill all general regs with a fixed pattern
228 set_ccr_zero
229
230 ;; add.l #xx:16, @erd-
231 mov.l #long_dst, er1
232 add.l #0xdead:16, @er1- ; Imm16, register post-decr operands.
233 ;;; .word 0x010e
234 ;;; .word 0xa110
235 ;;; .word 0xdead
236
237 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
238 test_neg_set
239 test_zero_clear
240 test_ovf_clear
241 test_carry_clear
242
243 test_gr_a5a5 0 ; Make sure other general regs not disturbed
244 test_h_gr32 long_dst-4, er1
245 test_gr_a5a5 2
246 test_gr_a5a5 3
247 test_gr_a5a5 4
248 test_gr_a5a5 5
249 test_gr_a5a5 6
250 test_gr_a5a5 7
251
252 ;; Now check the result of the move to memory.
253 cmp.l #0x876621ce, @long_dst
254 beq .Lnext13
255 fail
256 .Lnext13:
257 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
258
259 add_l_imm16_to_preinc: ; pre-increment from register to mem
260 set_grs_a5a5 ; Fill all general regs with a fixed pattern
261 set_ccr_zero
262
263 ;; add.l #xx:16, @+erd
264 mov.l #long_dst-4, er1
265 add.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands
266 ;;; .word 0x010e
267 ;;; .word 0x9110
268 ;;; .word 0xdead
269
270 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
271 test_neg_set
272 test_zero_clear
273 test_ovf_clear
274 test_carry_clear
275
276 test_gr_a5a5 0 ; Make sure other general regs not disturbed
277 test_h_gr32 long_dst, er1
278 test_gr_a5a5 2
279 test_gr_a5a5 3
280 test_gr_a5a5 4
281 test_gr_a5a5 5
282 test_gr_a5a5 6
283 test_gr_a5a5 7
284
285 ;; Now check the result of the move to memory.
286 cmp.l #0x876621ce, @long_dst
287 beq .Lnext14
288 fail
289 .Lnext14:
290 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
291
292 add_l_imm16_to_predec: ; pre-decrement from register to mem
293 set_grs_a5a5 ; Fill all general regs with a fixed pattern
294 set_ccr_zero
295
296 ;; add.l #xx:16, @-erd
297 mov.l #long_dst+4, er1
298 add.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands
299 ;;; .word 0x010e
300 ;;; .word 0xb110
301 ;;; .word 0xdead
302
303 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
304 test_neg_set
305 test_zero_clear
306 test_ovf_clear
307 test_carry_clear
308
309 test_gr_a5a5 0 ; Make sure other general regs not disturbed
310 test_h_gr32 long_dst, er1
311 test_gr_a5a5 2
312 test_gr_a5a5 3
313 test_gr_a5a5 4
314 test_gr_a5a5 5
315 test_gr_a5a5 6
316 test_gr_a5a5 7
317
318 ;; Now check the result of the move to memory.
319 cmp.l #0x876621ce, @long_dst
320 beq .Lnext15
321 fail
322 .Lnext15:
323 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
324
325 add_l_imm16_to_disp2:
326 set_grs_a5a5 ; Fill all general regs with a fixed pattern
327 set_ccr_zero
328
329 ;; add.l #xx:16, @(dd:2, erd)
330 mov.l #long_dst-12, er1
331 add.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand
332 ;;; .word 0x010e
333 ;;; .word 0x3110
334 ;;; .word 0xdead
335
336 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
337 test_neg_set
338 test_zero_clear
339 test_ovf_clear
340 test_carry_clear
341
342 test_gr_a5a5 0 ; Make sure other general regs not disturbed
343 test_h_gr32 long_dst-12, er1
344 test_gr_a5a5 2
345 test_gr_a5a5 3
346 test_gr_a5a5 4
347 test_gr_a5a5 5
348 test_gr_a5a5 6
349 test_gr_a5a5 7
350
351 ;; Now check the result of the move to memory.
352 cmp.l #0x876621ce, @long_dst
353 beq .Lnext16
354 fail
355 .Lnext16:
356 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
357
358 add_l_imm16_to_disp16:
359 set_grs_a5a5 ; Fill all general regs with a fixed pattern
360 set_ccr_zero
361
362 ;; add.l #xx:16, @(dd:16, erd)
363 mov.l #long_dst-4, er1
364 add.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand
365 ;;; .word 0x010e
366 ;;; .word 0xc110
367 ;;; .word 0xdead
368 ;;; .word 0x0004
369
370 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
371 test_neg_set
372 test_zero_clear
373 test_ovf_clear
374 test_carry_clear
375
376 test_gr_a5a5 0 ; Make sure other general regs not disturbed
377 test_h_gr32 long_dst-4, er1
378 test_gr_a5a5 2
379 test_gr_a5a5 3
380 test_gr_a5a5 4
381 test_gr_a5a5 5
382 test_gr_a5a5 6
383 test_gr_a5a5 7
384
385 ;; Now check the result of the move to memory.
386 cmp.l #0x876621ce, @long_dst
387 beq .Lnext17
388 fail
389 .Lnext17:
390 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
391
392 add_l_imm16_to_disp32:
393 set_grs_a5a5 ; Fill all general regs with a fixed pattern
394 set_ccr_zero
395
396 ;; add.l #xx:16, @(dd:32, erd)
397 mov.l #long_dst-8, er1
398 add.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand
399 ;;; .word 0x010e
400 ;;; .word 0xc910
401 ;;; .word 0xdead
402 ;;; .long 8
403
404 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
405 test_neg_set
406 test_zero_clear
407 test_ovf_clear
408 test_carry_clear
409
410 test_gr_a5a5 0 ; Make sure other general regs not disturbed
411 test_h_gr32 long_dst-8, er1
412 test_gr_a5a5 2
413 test_gr_a5a5 3
414 test_gr_a5a5 4
415 test_gr_a5a5 5
416 test_gr_a5a5 6
417 test_gr_a5a5 7
418
419 ;; Now check the result of the move to memory.
420 cmp.l #0x876621ce, @long_dst
421 beq .Lnext18
422 fail
423 .Lnext18:
424 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
425
426 add_l_imm16_to_abs16:
427 set_grs_a5a5 ; Fill all general regs with a fixed pattern
428 set_ccr_zero
429
430 ;; add.l #xx:16, @aa:16
431 add.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand
432 ;;; .word 0x010e
433 ;;; .word 0x4010
434 ;;; .word 0xdead
435 ;;; .word @long_dst
436
437 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
438 test_neg_set
439 test_zero_clear
440 test_ovf_clear
441 test_carry_clear
442
443 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
444 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
445 test_gr_a5a5 2 ; to examine the destination memory).
446 test_gr_a5a5 3
447 test_gr_a5a5 4
448 test_gr_a5a5 5
449 test_gr_a5a5 6
450 test_gr_a5a5 7
451
452 ;; Now check the result of the move to memory.
453 cmp.l #0x876621ce, @long_dst
454 beq .Lnext19
455 fail
456 .Lnext19:
457 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
458
459 add_l_imm16_to_abs32:
460 set_grs_a5a5 ; Fill all general regs with a fixed pattern
461 set_ccr_zero
462
463 ;; add.l #xx:16, @aa:32
464 add.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand
465 ;;; .word 0x010e
466 ;;; .word 0x4810
467 ;;; .word 0xdead
468 ;;; .long @long_dst
469
470 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
471 test_neg_set
472 test_zero_clear
473 test_ovf_clear
474 test_carry_clear
475
476 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
477 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
478 test_gr_a5a5 2 ; to examine the destination memory).
479 test_gr_a5a5 3
480 test_gr_a5a5 4
481 test_gr_a5a5 5
482 test_gr_a5a5 6
483 test_gr_a5a5 7
484
485 ;; Now check the result of the move to memory.
486 cmp.l #0x876621ce, @long_dst
487 beq .Lnext20
488 fail
489 .Lnext20:
490 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
491
492 add_l_imm32_to_indirect:
493 set_grs_a5a5 ; Fill all general regs with a fixed pattern
494 set_ccr_zero
495
496 ;; add.l #xx:32, @erd
497 mov.l #long_dst, er1
498 add.l #0xcafedead:32, @er1 ; Register indirect operand
499 ;;; .word 0x010e
500 ;;; .word 0x0118
501 ;;; .long 0xcafedead
502
503 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
504 test_neg_clear
505 test_zero_clear
506 test_ovf_set
507 test_carry_set
508
509 test_gr_a5a5 0 ; Make sure other general regs not disturbed
510 test_h_gr32 long_dst, er1
511 test_gr_a5a5 2
512 test_gr_a5a5 3
513 test_gr_a5a5 4
514 test_gr_a5a5 5
515 test_gr_a5a5 6
516 test_gr_a5a5 7
517
518 ;; Now check the result of the move to memory.
519 cmp.l #0x526421ce, @long_dst
520 beq .Lnext21
521 fail
522 .Lnext21:
523 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
524
525 add_l_imm32_to_postinc: ; post-increment from imm32 to mem
526 set_grs_a5a5 ; Fill all general regs with a fixed pattern
527 set_ccr_zero
528
529 ;; add.l #xx:32, @erd+
530 mov.l #long_dst, er1
531 add.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands.
532 ;;; .word 0x010e
533 ;;; .word 0x8118
534 ;;; .long 0xcafedead
535
536 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
537 test_neg_clear
538 test_zero_clear
539 test_ovf_set
540 test_carry_set
541
542 test_gr_a5a5 0 ; Make sure other general regs not disturbed
543 test_h_gr32 long_dst+4, er1
544 test_gr_a5a5 2
545 test_gr_a5a5 3
546 test_gr_a5a5 4
547 test_gr_a5a5 5
548 test_gr_a5a5 6
549 test_gr_a5a5 7
550
551 ;; Now check the result of the move to memory.
552 cmp.l #0x526421ce, @long_dst
553 beq .Lnext22
554 fail
555 .Lnext22:
556 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
557
558 add_l_imm32_to_postdec: ; post-decrement from imm32 to mem
559 set_grs_a5a5 ; Fill all general regs with a fixed pattern
560 set_ccr_zero
561
562 ;; add.l #xx:32, @erd-
563 mov.l #long_dst, er1
564 add.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands.
565 ;;; .word 0x010e
566 ;;; .word 0xa118
567 ;;; .long 0xcafedead
568
569 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
570 test_neg_clear
571 test_zero_clear
572 test_ovf_set
573 test_carry_set
574
575 test_gr_a5a5 0 ; Make sure other general regs not disturbed
576 test_h_gr32 long_dst-4, er1
577 test_gr_a5a5 2
578 test_gr_a5a5 3
579 test_gr_a5a5 4
580 test_gr_a5a5 5
581 test_gr_a5a5 6
582 test_gr_a5a5 7
583
584 ;; Now check the result of the move to memory.
585 cmp.l #0x526421ce, @long_dst
586 beq .Lnext23
587 fail
588 .Lnext23:
589 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
590
591 add_l_imm32_to_preinc: ; pre-increment from register to mem
592 set_grs_a5a5 ; Fill all general regs with a fixed pattern
593 set_ccr_zero
594
595 ;; add.l #xx:32, @+erd
596 mov.l #long_dst-4, er1
597 add.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands
598 ;;; .word 0x010e
599 ;;; .word 0x9118
600 ;;; .long 0xcafedead
601
602 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
603 test_neg_clear
604 test_zero_clear
605 test_ovf_set
606 test_carry_set
607
608 test_gr_a5a5 0 ; Make sure other general regs not disturbed
609 test_h_gr32 long_dst, er1
610 test_gr_a5a5 2
611 test_gr_a5a5 3
612 test_gr_a5a5 4
613 test_gr_a5a5 5
614 test_gr_a5a5 6
615 test_gr_a5a5 7
616
617 ;; Now check the result of the move to memory.
618 cmp.l #0x526421ce, @long_dst
619 beq .Lnext24
620 fail
621 .Lnext24:
622 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
623
624 add_l_imm32_to_predec: ; pre-decrement from register to mem
625 set_grs_a5a5 ; Fill all general regs with a fixed pattern
626 set_ccr_zero
627
628 ;; add.l #xx:32, @-erd
629 mov.l #long_dst+4, er1
630 add.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands
631 ;;; .word 0x010e
632 ;;; .word 0xb118
633 ;;; .long 0xcafedead
634
635 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
636 test_neg_clear
637 test_zero_clear
638 test_ovf_set
639 test_carry_set
640
641 test_gr_a5a5 0 ; Make sure other general regs not disturbed
642 test_h_gr32 long_dst, er1
643 test_gr_a5a5 2
644 test_gr_a5a5 3
645 test_gr_a5a5 4
646 test_gr_a5a5 5
647 test_gr_a5a5 6
648 test_gr_a5a5 7
649
650 ;; Now check the result of the move to memory.
651 cmp.l #0x526421ce, @long_dst
652 beq .Lnext25
653 fail
654 .Lnext25:
655 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
656
657 add_l_imm32_to_disp2:
658 set_grs_a5a5 ; Fill all general regs with a fixed pattern
659 set_ccr_zero
660
661 ;; add.l #xx:32, @(dd:2, erd)
662 mov.l #long_dst-12, er1
663 add.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand
664 ;;; .word 0x010e
665 ;;; .word 0x3118
666 ;;; .long 0xcafedead
667
668 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
669 test_neg_clear
670 test_zero_clear
671 test_ovf_set
672 test_carry_set
673
674 test_gr_a5a5 0 ; Make sure other general regs not disturbed
675 test_h_gr32 long_dst-12, er1
676 test_gr_a5a5 2
677 test_gr_a5a5 3
678 test_gr_a5a5 4
679 test_gr_a5a5 5
680 test_gr_a5a5 6
681 test_gr_a5a5 7
682
683 ;; Now check the result of the move to memory.
684 cmp.l #0x526421ce, @long_dst
685 beq .Lnext26
686 fail
687 .Lnext26:
688 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
689
690 add_l_imm32_to_disp16:
691 set_grs_a5a5 ; Fill all general regs with a fixed pattern
692 set_ccr_zero
693
694 ;; add.l #xx:32, @(dd:16, erd)
695 mov.l #long_dst-4, er1
696 add.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand
697 ;;; .word 0x010e
698 ;;; .word 0xc118
699 ;;; .long 0xcafedead
700 ;;; .word 0x0004
701
702 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
703 test_neg_clear
704 test_zero_clear
705 test_ovf_set
706 test_carry_set
707
708 test_gr_a5a5 0 ; Make sure other general regs not disturbed
709 test_h_gr32 long_dst-4, er1
710 test_gr_a5a5 2
711 test_gr_a5a5 3
712 test_gr_a5a5 4
713 test_gr_a5a5 5
714 test_gr_a5a5 6
715 test_gr_a5a5 7
716
717 ;; Now check the result of the move to memory.
718 cmp.l #0x526421ce, @long_dst
719 beq .Lnext27
720 fail
721 .Lnext27:
722 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
723
724 add_l_imm32_to_disp32:
725 set_grs_a5a5 ; Fill all general regs with a fixed pattern
726 set_ccr_zero
727
728 ;; add.l #xx:32, @(dd:32, erd)
729 mov.l #long_dst-8, er1
730 add.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand
731 ;;; .word 0x010e
732 ;;; .word 0xc918
733 ;;; .long 0xcafedead
734 ;;; .long 8
735
736 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
737 test_neg_clear
738 test_zero_clear
739 test_ovf_set
740 test_carry_set
741
742 test_gr_a5a5 0 ; Make sure other general regs not disturbed
743 test_h_gr32 long_dst-8, er1
744 test_gr_a5a5 2
745 test_gr_a5a5 3
746 test_gr_a5a5 4
747 test_gr_a5a5 5
748 test_gr_a5a5 6
749 test_gr_a5a5 7
750
751 ;; Now check the result of the move to memory.
752 cmp.l #0x526421ce, @long_dst
753 beq .Lnext28
754 fail
755 .Lnext28:
756 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
757
758 add_l_imm32_to_abs16:
759 set_grs_a5a5 ; Fill all general regs with a fixed pattern
760 set_ccr_zero
761
762 ;; add.l #xx:32, @aa:16
763 add.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand
764 ;;; .word 0x010e
765 ;;; .word 0x4018
766 ;;; .long 0xcafedead
767 ;;; .word @long_dst
768
769 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
770 test_neg_clear
771 test_zero_clear
772 test_ovf_set
773 test_carry_set
774
775 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
776 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
777 test_gr_a5a5 2 ; to examine the destination memory).
778 test_gr_a5a5 3
779 test_gr_a5a5 4
780 test_gr_a5a5 5
781 test_gr_a5a5 6
782 test_gr_a5a5 7
783
784 ;; Now check the result of the move to memory.
785 cmp.l #0x526421ce, @long_dst
786 beq .Lnext29
787 fail
788 .Lnext29:
789 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
790
791 add_l_imm32_to_abs32:
792 set_grs_a5a5 ; Fill all general regs with a fixed pattern
793 set_ccr_zero
794
795 ;; add.l #xx:32, @aa:32
796 add.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand
797 ;;; .word 0x010e
798 ;;; .word 0x4818
799 ;;; .long 0xcafedead
800 ;;; .long @long_dst
801
802 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
803 test_neg_clear
804 test_zero_clear
805 test_ovf_set
806 test_carry_set
807
808 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
809 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
810 test_gr_a5a5 2 ; to examine the destination memory).
811 test_gr_a5a5 3
812 test_gr_a5a5 4
813 test_gr_a5a5 5
814 test_gr_a5a5 6
815 test_gr_a5a5 7
816
817 ;; Now check the result of the move to memory.
818 cmp.l #0x526421ce, @long_dst
819 beq .Lnext30
820 fail
821 .Lnext30:
822 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
823 .endif
824
825 ;;
826 ;; Add long from register source
827 ;;
828
829 add_l_reg32_to_reg32:
830 set_grs_a5a5 ; Fill all general regs with a fixed pattern
831 set_ccr_zero
832
833 ;; add.l ers, erd
834 mov.l #0x12345678, er1
835 add.l er1, er0 ; Register 32-bit operand
836 ;;; .word 0x0a90
837
838 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
839 test_neg_set
840 test_zero_clear
841 test_ovf_clear
842 test_carry_clear
843
844 test_h_gr32 0xb7d9fc1d er0 ; add result
845 test_h_gr32 0x12345678 er1 ; add src unchanged
846
847 test_gr_a5a5 2 ; Make sure other general regs not disturbed
848 test_gr_a5a5 3
849 test_gr_a5a5 4
850 test_gr_a5a5 5
851 test_gr_a5a5 6
852 test_gr_a5a5 7
853
854 .if (sim_cpu == h8sx)
855 add_l_reg32_to_indirect:
856 set_grs_a5a5 ; Fill all general regs with a fixed pattern
857 set_ccr_zero
858
859 ;; add.l ers, @erd
860 mov.l #long_dst, er1
861 add.l er0, @er1 ; Register indirect operand
862 ;;; .word 0x0109
863 ;;; .word 0x0110
864
865 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
866 test_neg_clear
867 test_zero_clear
868 test_ovf_set
869 test_carry_set
870
871 test_gr_a5a5 0 ; Make sure other general regs not disturbed
872 test_h_gr32 long_dst, er1
873 test_gr_a5a5 2
874 test_gr_a5a5 3
875 test_gr_a5a5 4
876 test_gr_a5a5 5
877 test_gr_a5a5 6
878 test_gr_a5a5 7
879
880 ;; Now check the result of the move to memory.
881 cmp.l #0x2d0ae8c6, @long_dst
882 beq .Lnext44
883 fail
884 .Lnext44:
885 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
886
887 add_l_reg32_to_postinc: ; post-increment from register to mem
888 set_grs_a5a5 ; Fill all general regs with a fixed pattern
889 set_ccr_zero
890
891 ;; add.l ers, @erd+
892 mov.l #long_dst, er1
893 add.l er0, @er1+ ; Register post-incr operand
894 ;;; .word 0x0109
895 ;;; .word 0x8110
896
897 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
898 test_neg_clear
899 test_zero_clear
900 test_ovf_set
901 test_carry_set
902
903 test_gr_a5a5 0 ; Make sure other general regs not disturbed
904 test_h_gr32 long_dst+4, er1
905 test_gr_a5a5 2
906 test_gr_a5a5 3
907 test_gr_a5a5 4
908 test_gr_a5a5 5
909 test_gr_a5a5 6
910 test_gr_a5a5 7
911
912 ;; Now check the result of the move to memory.
913 cmp.l #0x2d0ae8c6, @long_dst
914 beq .Lnext49
915 fail
916 .Lnext49:
917 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
918
919 add_l_reg32_to_postdec: ; post-decrement from register to mem
920 set_grs_a5a5 ; Fill all general regs with a fixed pattern
921 set_ccr_zero
922
923 ;; add.l ers, @erd-
924 mov.l #long_dst, er1
925 add.l er0, @er1- ; Register post-decr operand
926 ;;; .word 0x0109
927 ;;; .word 0xa110
928
929 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
930 test_neg_clear
931 test_zero_clear
932 test_ovf_set
933 test_carry_set
934
935 test_gr_a5a5 0 ; Make sure other general regs not disturbed
936 test_h_gr32 long_dst-4, er1
937 test_gr_a5a5 2
938 test_gr_a5a5 3
939 test_gr_a5a5 4
940 test_gr_a5a5 5
941 test_gr_a5a5 6
942 test_gr_a5a5 7
943
944 ;; Now check the result of the move to memory.
945 cmp.l #0x2d0ae8c6, @long_dst
946 beq .Lnext50
947 fail
948 .Lnext50:
949 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
950
951 add_l_reg32_to_preinc: ; pre-increment from register to mem
952 set_grs_a5a5 ; Fill all general regs with a fixed pattern
953 set_ccr_zero
954
955 ;; add.l ers, @+erd
956 mov.l #long_dst-4, er1
957 add.l er0, @+er1 ; Register pre-incr operand
958 ;;; .word 0x0109
959 ;;; .word 0x9110
960
961 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
962 test_neg_clear
963 test_zero_clear
964 test_ovf_set
965 test_carry_set
966
967 test_gr_a5a5 0 ; Make sure other general regs not disturbed
968 test_h_gr32 long_dst, er1
969 test_gr_a5a5 2
970 test_gr_a5a5 3
971 test_gr_a5a5 4
972 test_gr_a5a5 5
973 test_gr_a5a5 6
974 test_gr_a5a5 7
975
976 ;; Now check the result of the move to memory.
977 cmp.l #0x2d0ae8c6, @long_dst
978 beq .Lnext51
979 fail
980 .Lnext51:
981 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
982
983 add_l_reg32_to_predec: ; pre-decrement from register to mem
984 set_grs_a5a5 ; Fill all general regs with a fixed pattern
985 set_ccr_zero
986
987 ;; add.l ers, @-erd
988 mov.l #long_dst+4, er1
989 add.l er0, @-er1 ; Register pre-decr operand
990 ;;; .word 0x0109
991 ;;; .word 0xb110
992
993 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
994 test_neg_clear
995 test_zero_clear
996 test_ovf_set
997 test_carry_set
998
999 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1000 test_h_gr32 long_dst, er1
1001 test_gr_a5a5 2
1002 test_gr_a5a5 3
1003 test_gr_a5a5 4
1004 test_gr_a5a5 5
1005 test_gr_a5a5 6
1006 test_gr_a5a5 7
1007
1008 ;; Now check the result of the move to memory.
1009 cmp.l #0x2d0ae8c6, @long_dst
1010 beq .Lnext48
1011 fail
1012 .Lnext48:
1013 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
1014
1015 add_l_reg32_to_disp2:
1016 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1017 set_ccr_zero
1018
1019 ;; add.l ers, @(dd:2, erd)
1020 mov.l #long_dst-12, er1
1021 add.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand
1022 ;;; .word 0x0109
1023 ;;; .word 0x3110
1024
1025 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
1026 test_neg_clear
1027 test_zero_clear
1028 test_ovf_set
1029 test_carry_set
1030
1031 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1032 test_h_gr32 long_dst-12, er1
1033 test_gr_a5a5 2
1034 test_gr_a5a5 3
1035 test_gr_a5a5 4
1036 test_gr_a5a5 5
1037 test_gr_a5a5 6
1038 test_gr_a5a5 7
1039
1040 ;; Now check the result of the move to memory.
1041 cmp.l #0x2d0ae8c6, @long_dst
1042 beq .Lnext52
1043 fail
1044 .Lnext52:
1045 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
1046
1047 add_l_reg32_to_disp16:
1048 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1049 set_ccr_zero
1050
1051 ;; add.l ers, @(dd:16, erd)
1052 mov.l #long_dst-4, er1
1053 add.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand
1054 ;;; .word 0x0109
1055 ;;; .word 0xc110
1056 ;;; .word 0x0004
1057
1058 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
1059 test_neg_clear
1060 test_zero_clear
1061 test_ovf_set
1062 test_carry_set
1063
1064 test_h_gr32 long_dst-4, er1
1065 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1066 test_gr_a5a5 2
1067 test_gr_a5a5 3
1068 test_gr_a5a5 4
1069 test_gr_a5a5 5
1070 test_gr_a5a5 6
1071 test_gr_a5a5 7
1072
1073 ;; Now check the result of the move to memory.
1074 cmp.l #0x2d0ae8c6, @long_dst
1075 beq .Lnext45
1076 fail
1077 .Lnext45:
1078 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
1079
1080 add_l_reg32_to_disp32:
1081 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1082 set_ccr_zero
1083
1084 ;; add.l ers, @(dd:32, erd)
1085 mov.l #long_dst-8, er1
1086 add.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand
1087 ;;; .word 0x0109
1088 ;;; .word 0xc910
1089 ;;; .long 8
1090
1091 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
1092 test_neg_clear
1093 test_zero_clear
1094 test_ovf_set
1095 test_carry_set
1096
1097 test_h_gr32 long_dst-8, er1
1098 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1099 test_gr_a5a5 2
1100 test_gr_a5a5 3
1101 test_gr_a5a5 4
1102 test_gr_a5a5 5
1103 test_gr_a5a5 6
1104 test_gr_a5a5 7
1105
1106 ;; Now check the result of the move to memory.
1107 cmp.l #0x2d0ae8c6, @long_dst
1108 beq .Lnext46
1109 fail
1110 .Lnext46:
1111 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
1112
1113 add_l_reg32_to_abs16:
1114 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1115 set_ccr_zero
1116
1117 ;; add.l ers, @aa:16
1118 add.l er0, @long_dst:16 ; 16-bit address-direct operand
1119 ;;; .word 0x0109
1120 ;;; .word 0x4110
1121 ;;; .word @long_dst
1122
1123 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
1124 test_neg_clear
1125 test_zero_clear
1126 test_ovf_set
1127 test_carry_set
1128
1129 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
1130 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
1131 test_gr_a5a5 2 ; to examine the destination memory).
1132 test_gr_a5a5 3
1133 test_gr_a5a5 4
1134 test_gr_a5a5 5
1135 test_gr_a5a5 6
1136 test_gr_a5a5 7
1137
1138 ;; Now check the result of the move to memory.
1139 cmp.l #0x2d0ae8c6, @long_dst
1140 beq .Lnext41
1141 fail
1142 .Lnext41:
1143 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
1144
1145 add_l_reg32_to_abs32:
1146 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1147 set_ccr_zero
1148
1149 ;; add.l ers, @aa:32
1150 add.l er0, @long_dst:32 ; 32-bit address-direct operand
1151 ;;; .word 0x0109
1152 ;;; .word 0x4910
1153 ;;; .long @long_dst
1154
1155 ;; test ccr ; H=0 N=0 Z=0 V=1 C=1
1156 test_neg_clear
1157 test_zero_clear
1158 test_ovf_set
1159 test_carry_set
1160
1161 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
1162 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
1163 test_gr_a5a5 2 ; to examine the destination memory).
1164 test_gr_a5a5 3
1165 test_gr_a5a5 4
1166 test_gr_a5a5 5
1167 test_gr_a5a5 6
1168 test_gr_a5a5 7
1169
1170 ;; Now check the result of the move to memory.
1171 cmp.l #0x2d0ae8c6, @long_dst
1172 beq .Lnext42
1173 fail
1174 .Lnext42:
1175 mov.l #0x87654321, @long_dst ; Re-initialize it for the next use.
1176
1177 ;;
1178 ;; Add long to register destination.
1179 ;;
1180
1181 add_l_indirect_to_reg32:
1182 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1183 set_ccr_zero
1184
1185 ;; add.l @ers, Rd
1186 mov.l #long_src, er1
1187 add.l @er1, er0 ; Register indirect operand
1188 ;;; .word 0x010a
1189 ;;; .word 0x0110
1190
1191 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1192 test_neg_set
1193 test_zero_clear
1194 test_ovf_clear
1195 test_carry_clear
1196
1197 test_h_gr32 0xb7d9fc1d er0
1198
1199 test_h_gr32 long_src, er1
1200 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1201 test_gr_a5a5 3
1202 test_gr_a5a5 4
1203 test_gr_a5a5 5
1204 test_gr_a5a5 6
1205 test_gr_a5a5 7
1206
1207 add_l_postinc_to_reg32: ; post-increment from mem to register
1208 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1209 set_ccr_zero
1210
1211 ;; add.l @ers+, erd
1212 mov.l #long_src, er1
1213 add.l @er1+, er0 ; Register post-incr operand
1214 ;;; .word 0x010a
1215 ;;; .word 0x8110
1216
1217 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1218 test_neg_set
1219 test_zero_clear
1220 test_ovf_clear
1221 test_carry_clear
1222
1223 test_h_gr32 0xb7d9fc1d er0
1224
1225 test_h_gr32 long_src+4, er1
1226 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1227 test_gr_a5a5 3
1228 test_gr_a5a5 4
1229 test_gr_a5a5 5
1230 test_gr_a5a5 6
1231 test_gr_a5a5 7
1232
1233 add_l_postdec_to_reg32: ; post-decrement from mem to register
1234 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1235 set_ccr_zero
1236
1237 ;; add.l @ers-, erd
1238 mov.l #long_src, er1
1239 add.l @er1-, er0 ; Register post-decr operand
1240 ;;; .word 0x010a
1241 ;;; .word 0xa110
1242
1243 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1244 test_neg_set
1245 test_zero_clear
1246 test_ovf_clear
1247 test_carry_clear
1248
1249 test_h_gr32 0xb7d9fc1d er0
1250
1251 test_h_gr32 long_src-4, er1
1252 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1253 test_gr_a5a5 3
1254 test_gr_a5a5 4
1255 test_gr_a5a5 5
1256 test_gr_a5a5 6
1257 test_gr_a5a5 7
1258
1259 add_l_preinc_to_reg32: ; pre-increment from mem to register
1260 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1261 set_ccr_zero
1262
1263 ;; add.l @+ers, erd
1264 mov.l #long_src-4, er1
1265 add.l @+er1, er0 ; Register pre-incr operand
1266 ;;; .word 0x010a
1267 ;;; .word 0x9110
1268
1269 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1270 test_neg_set
1271 test_zero_clear
1272 test_ovf_clear
1273 test_carry_clear
1274
1275 test_h_gr32 0xb7d9fc1d er0
1276
1277 test_h_gr32 long_src, er1
1278 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1279 test_gr_a5a5 3
1280 test_gr_a5a5 4
1281 test_gr_a5a5 5
1282 test_gr_a5a5 6
1283 test_gr_a5a5 7
1284
1285 add_l_predec_to_reg32: ; pre-decrement from mem to register
1286 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1287 set_ccr_zero
1288
1289 ;; add.l @-ers, erd
1290 mov.l #long_src+4, er1
1291 add.l @-er1, er0 ; Register pre-decr operand
1292 ;;; .word 0x010a
1293 ;;; .word 0xb110
1294
1295 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1296 test_neg_set
1297 test_zero_clear
1298 test_ovf_clear
1299 test_carry_clear
1300
1301 test_h_gr32 0xb7d9fc1d er0
1302
1303 test_h_gr32 long_src, er1
1304 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1305 test_gr_a5a5 3
1306 test_gr_a5a5 4
1307 test_gr_a5a5 5
1308 test_gr_a5a5 6
1309 test_gr_a5a5 7
1310
1311
1312 add_l_disp2_to_reg32:
1313 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1314 set_ccr_zero
1315
1316 ;; add.l @(dd:2, ers), erd
1317 mov.l #long_src-4, er1
1318 add.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand
1319 ;;; .word 0x010a
1320 ;;; .word 0x1110
1321
1322 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1323 test_neg_set
1324 test_zero_clear
1325 test_ovf_clear
1326 test_carry_clear
1327
1328 test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
1329
1330 test_h_gr32 long_src-4, er1
1331 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1332 test_gr_a5a5 3
1333 test_gr_a5a5 4
1334 test_gr_a5a5 5
1335 test_gr_a5a5 6
1336 test_gr_a5a5 7
1337
1338 add_l_disp16_to_reg32:
1339 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1340 set_ccr_zero
1341
1342 ;; add.l @(dd:16, ers), erd
1343 mov.l #long_src+0x1234, er1
1344 add.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand
1345 ;;; .word 0x010a
1346 ;;; .word 0xc110
1347 ;;; .word -0x1234
1348
1349 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1350 test_neg_set
1351 test_zero_clear
1352 test_ovf_clear
1353 test_carry_clear
1354
1355 test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
1356
1357 test_h_gr32 long_src+0x1234, er1
1358 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1359 test_gr_a5a5 3
1360 test_gr_a5a5 4
1361 test_gr_a5a5 5
1362 test_gr_a5a5 6
1363 test_gr_a5a5 7
1364
1365 add_l_disp32_to_reg32:
1366 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1367 set_ccr_zero
1368
1369 ;; add.l @(dd:32, ers), erd
1370 mov.l #long_src+65536, er1
1371 add.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand
1372 ;;; .word 0x010a
1373 ;;; .word 0xc910
1374 ;;; .long -65536
1375
1376 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1377 test_neg_set
1378 test_zero_clear
1379 test_ovf_clear
1380 test_carry_clear
1381
1382 test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777
1383
1384 test_h_gr32 long_src+65536, er1
1385 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1386 test_gr_a5a5 3
1387 test_gr_a5a5 4
1388 test_gr_a5a5 5
1389 test_gr_a5a5 6
1390 test_gr_a5a5 7
1391
1392 add_l_abs16_to_reg32:
1393 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1394 set_ccr_zero
1395
1396 ;; add.l @aa:16, erd
1397 add.l @long_src:16, er0 ; 16-bit address-direct operand
1398 ;;; .word 0x010a
1399 ;;; .word 0x4010
1400 ;;; .word @long_src
1401
1402 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1403 test_neg_set
1404 test_zero_clear
1405 test_ovf_clear
1406 test_carry_clear
1407
1408 test_h_gr32 0xb7d9fc1d er0
1409
1410 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1411 test_gr_a5a5 2
1412 test_gr_a5a5 3
1413 test_gr_a5a5 4
1414 test_gr_a5a5 5
1415 test_gr_a5a5 6
1416 test_gr_a5a5 7
1417
1418 add_l_abs32_to_reg32:
1419 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1420 set_ccr_zero
1421
1422 ;; add.l @aa:32, erd
1423 add.l @long_src:32, er0 ; 32-bit address-direct operand
1424 ;;; .word 0x010a
1425 ;;; .word 0x4810
1426 ;;; .long @long_src
1427
1428 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1429 test_neg_set
1430 test_zero_clear
1431 test_ovf_clear
1432 test_carry_clear
1433
1434 test_h_gr32 0xb7d9fc1d er0
1435
1436 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1437 test_gr_a5a5 2
1438 test_gr_a5a5 3
1439 test_gr_a5a5 4
1440 test_gr_a5a5 5
1441 test_gr_a5a5 6
1442 test_gr_a5a5 7
1443
1444
1445 ;;
1446 ;; Add long from memory to memory
1447 ;;
1448
1449 add_l_indirect_to_indirect: ; reg indirect, memory to memory
1450 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1451 set_ccr_zero
1452
1453 ;; add.l @ers, @erd
1454 mov.l #long_src, er1
1455 mov.l #long_dst, er0
1456 add.l @er1, @er0
1457 ;;; .word 0x0104
1458 ;;; .word 0x691c
1459 ;;; .word 0x0010
1460
1461 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1462 test_neg_set
1463 test_zero_clear
1464 test_ovf_clear
1465 test_carry_clear
1466
1467 ;; Verify the affected registers.
1468
1469 test_h_gr32 long_dst er0
1470 test_h_gr32 long_src er1
1471 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1472 test_gr_a5a5 3
1473 test_gr_a5a5 4
1474 test_gr_a5a5 5
1475 test_gr_a5a5 6
1476 test_gr_a5a5 7
1477
1478 ;; Now check the result of the move to memory.
1479 cmp.l #0x99999999, @long_dst ; FIXME
1480 beq .Lnext55
1481 fail
1482 .Lnext55:
1483 ;; Now clear the destination location, and verify that.
1484 mov.l #0x87654321, @long_dst
1485 cmp.l #0x99999999, @long_dst
1486 bne .Lnext56
1487 fail
1488 .Lnext56: ; OK, pass on.
1489
1490 add_l_postinc_to_postinc: ; reg post-increment, memory to memory
1491 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1492 set_ccr_zero
1493
1494 ;; add.l @ers+, @erd+
1495 mov.l #long_src, er1
1496 mov.l #long_dst, er0
1497 add.l @er1+, @er0+
1498 ;;; .word 0x0104
1499 ;;; .word 0x6d1c
1500 ;;; .word 0x8010
1501
1502 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1503 test_neg_set
1504 test_zero_clear
1505 test_ovf_clear
1506 test_carry_clear
1507
1508 ;; Verify the affected registers.
1509
1510 test_h_gr32 long_dst+4 er0
1511 test_h_gr32 long_src+4 er1
1512 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1513 test_gr_a5a5 3
1514 test_gr_a5a5 4
1515 test_gr_a5a5 5
1516 test_gr_a5a5 6
1517 test_gr_a5a5 7
1518
1519 ;; Now check the result of the move to memory.
1520 cmp.l #0x99999999, @long_dst
1521 beq .Lnext65
1522 fail
1523 .Lnext65:
1524 ;; Now clear the destination location, and verify that.
1525 mov.l #0x87654321, @long_dst
1526 cmp.l #0x99999999, @long_dst
1527 bne .Lnext66
1528 fail
1529 .Lnext66: ; OK, pass on.
1530
1531 add_l_postdec_to_postdec: ; reg post-decrement, memory to memory
1532 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1533 set_ccr_zero
1534
1535 ;; add.l @ers-, @erd-
1536 mov.l #long_src, er1
1537 mov.l #long_dst, er0
1538 add.l @er1-, @er0-
1539 ;;; .word 0x0106
1540 ;;; .word 0x6d1c
1541 ;;; .word 0xa010
1542
1543 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1544 test_neg_set
1545 test_zero_clear
1546 test_ovf_clear
1547 test_carry_clear
1548
1549 ;; Verify the affected registers.
1550
1551 test_h_gr32 long_dst-4 er0
1552 test_h_gr32 long_src-4 er1
1553 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1554 test_gr_a5a5 3
1555 test_gr_a5a5 4
1556 test_gr_a5a5 5
1557 test_gr_a5a5 6
1558 test_gr_a5a5 7
1559
1560 ;; Now check the result of the move to memory.
1561 cmp.l #0x99999999, @long_dst
1562 beq .Lnext75
1563 fail
1564 .Lnext75:
1565 ;; Now clear the destination location, and verify that.
1566 mov.l #0x87654321, @long_dst
1567 cmp.l #0x99999999, @long_dst
1568 bne .Lnext76
1569 fail
1570 .Lnext76: ; OK, pass on.
1571
1572 add_l_preinc_to_preinc: ; reg pre-increment, memory to memory
1573 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1574 set_ccr_zero
1575
1576 ;; add.l @+ers, @+erd
1577 mov.l #long_src-4, er1
1578 mov.l #long_dst-4, er0
1579 add.l @+er1, @+er0
1580 ;;; .word 0x0105
1581 ;;; .word 0x6d1c
1582 ;;; .word 0x9010
1583
1584 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1585 test_neg_set
1586 test_zero_clear
1587 test_ovf_clear
1588 test_carry_clear
1589
1590 ;; Verify the affected registers.
1591
1592 test_h_gr32 long_dst er0
1593 test_h_gr32 long_src er1
1594 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1595 test_gr_a5a5 3
1596 test_gr_a5a5 4
1597 test_gr_a5a5 5
1598 test_gr_a5a5 6
1599 test_gr_a5a5 7
1600
1601 ;; Now check the result of the move to memory.
1602 cmp.l #0x99999999, @long_dst
1603 beq .Lnext85
1604 fail
1605 .Lnext85:
1606 ;; Now clear the destination location, and verify that.
1607 mov.l #0x87654321, @long_dst
1608 cmp.l #0x99999999, @long_dst
1609 bne .Lnext86
1610 fail
1611 .Lnext86: ; OK, pass on.
1612
1613 add_l_predec_to_predec: ; reg pre-decrement, memory to memory
1614 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1615 set_ccr_zero
1616
1617 ;; add.l @-ers, @-erd
1618 mov.l #long_src+4, er1
1619 mov.l #long_dst+4, er0
1620 add.l @-er1, @-er0
1621 ;;; .word 0x0107
1622 ;;; .word 0x6d1c
1623 ;;; .word 0xb010
1624
1625 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1626 test_neg_set
1627 test_zero_clear
1628 test_ovf_clear
1629 test_carry_clear
1630
1631 ;; Verify the affected registers.
1632
1633 test_h_gr32 long_dst er0
1634 test_h_gr32 long_src er1
1635 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1636 test_gr_a5a5 3
1637 test_gr_a5a5 4
1638 test_gr_a5a5 5
1639 test_gr_a5a5 6
1640 test_gr_a5a5 7
1641
1642 ;; Now check the result of the move to memory.
1643 cmp.l #0x99999999, @long_dst
1644 beq .Lnext95
1645 fail
1646 .Lnext95:
1647 ;; Now clear the destination location, and verify that.
1648 mov.l #0x87654321, @long_dst
1649 cmp.l #0x99999999, @long_dst
1650 bne .Lnext96
1651 fail
1652 .Lnext96: ; OK, pass on.
1653
1654 add_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory
1655 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1656 set_ccr_zero
1657
1658 ;; add.l @(dd:2, ers), @(dd:2, erd)
1659 mov.l #long_src-4, er1
1660 mov.l #long_dst-8, er0
1661 add.l @(4:2, er1), @(8:2, er0)
1662 ;;; .word 0x0105
1663 ;;; .word 0x691c
1664 ;;; .word 0x2010
1665
1666 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1667 test_neg_set
1668 test_zero_clear
1669 test_ovf_clear
1670 test_carry_clear
1671
1672 ;; Verify the affected registers.
1673
1674 test_h_gr32 long_dst-8 er0
1675 test_h_gr32 long_src-4 er1
1676 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1677 test_gr_a5a5 3
1678 test_gr_a5a5 4
1679 test_gr_a5a5 5
1680 test_gr_a5a5 6
1681 test_gr_a5a5 7
1682
1683 ;; Now check the result of the move to memory.
1684 cmp.l #0x99999999, @long_dst
1685 beq .Lnext105
1686 fail
1687 .Lnext105:
1688 ;; Now clear the destination location, and verify that.
1689 mov.l #0x87654321, @long_dst
1690 cmp.l #0x99999999, @long_dst
1691 bne .Lnext106
1692 fail
1693 .Lnext106: ; OK, pass on.
1694
1695 add_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory
1696 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1697 set_ccr_zero
1698
1699 ;; add.l @(dd:16, ers), @(dd:16, erd)
1700 mov.l #long_src-1, er1
1701 mov.l #long_dst-2, er0
1702 add.l @(1:16, er1), @(2:16, er0)
1703 ;;; .word 0x0104
1704 ;;; .word 0x6f1c
1705 ;;; .word 0x0001
1706 ;;; .word 0xc010
1707 ;;; .word 0x0002
1708
1709 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1710 test_neg_set
1711 test_zero_clear
1712 test_ovf_clear
1713 test_carry_clear
1714
1715 ;; Verify the affected registers.
1716
1717 test_h_gr32 long_dst-2 er0
1718 test_h_gr32 long_src-1 er1
1719 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1720 test_gr_a5a5 3
1721 test_gr_a5a5 4
1722 test_gr_a5a5 5
1723 test_gr_a5a5 6
1724 test_gr_a5a5 7
1725
1726 ;; Now check the result of the move to memory.
1727 cmp.l #0x99999999, @long_dst
1728 beq .Lnext115
1729 fail
1730 .Lnext115:
1731 ;; Now clear the destination location, and verify that.
1732 mov.l #0x87654321, @long_dst
1733 cmp.l #0x99999999, @long_dst
1734 bne .Lnext116
1735 fail
1736 .Lnext116: ; OK, pass on.
1737
1738 add_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory
1739 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1740 set_ccr_zero
1741
1742 ;; add.l @(dd:32, ers), @(dd:32, erd)
1743 mov.l #long_src-1, er1
1744 mov.l #long_dst-2, er0
1745 add.l @(1:32, er1), @(2:32, er0)
1746 ;;; .word 0x7894
1747 ;;; .word 0x6b2c
1748 ;;; .word 0xc9c8
1749 ;;; .long 1
1750 ;;; .word 0xc810
1751 ;;; .long 2
1752
1753 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1754 test_neg_set
1755 test_zero_clear
1756 test_ovf_clear
1757 test_carry_clear
1758
1759 ;; Verify the affected registers.
1760
1761 test_h_gr32 long_dst-2 er0
1762 test_h_gr32 long_src-1 er1
1763 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1764 test_gr_a5a5 3
1765 test_gr_a5a5 4
1766 test_gr_a5a5 5
1767 test_gr_a5a5 6
1768 test_gr_a5a5 7
1769
1770 ;; Now check the result of the move to memory.
1771 cmp.l #0x99999999, @long_dst
1772 beq .Lnext125
1773 fail
1774 .Lnext125:
1775 ;; Now clear the destination location, and verify that.
1776 mov.l #0x87654321, @long_dst
1777 cmp.l #0x99999999, @long_dst
1778 bne .Lnext126
1779 fail
1780 .Lnext126: ; OK, pass on.
1781
1782 add_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
1783 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1784 set_ccr_zero
1785
1786 ;; add.l @aa:16, @aa:16
1787 add.l @long_src:16, @long_dst:16
1788 ;;; .word 0x0104
1789 ;;; .word 0x6b0c
1790 ;;; .word @long_src
1791 ;;; .word 0x4010
1792 ;;; .word @long_dst
1793
1794 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1795 test_neg_set
1796 test_zero_clear
1797 test_ovf_clear
1798 test_carry_clear
1799
1800
1801 test_gr_a5a5 0 ; Make sure *NO* general registers are changed
1802 test_gr_a5a5 1
1803 test_gr_a5a5 2
1804 test_gr_a5a5 3
1805 test_gr_a5a5 4
1806 test_gr_a5a5 5
1807 test_gr_a5a5 6
1808 test_gr_a5a5 7
1809
1810 ;; Now check the result of the move to memory.
1811 cmp.l #0x99999999, @long_dst
1812 beq .Lnext135
1813 fail
1814 .Lnext135:
1815 ;; Now clear the destination location, and verify that.
1816 mov.l #0x87654321, @long_dst
1817 cmp.l #0x99999999, @long_dst
1818 bne .Lnext136
1819 fail
1820 .Lnext136: ; OK, pass on.
1821
1822 add_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
1823 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1824 set_ccr_zero
1825
1826 ;; add.l @aa:32, @aa:32
1827 add.l @long_src:32, @long_dst:32
1828 ;;; .word 0x0104
1829 ;;; .word 0x6b2c
1830 ;;; .long @long_src
1831 ;;; .word 0x4810
1832 ;;; .long @long_dst
1833
1834 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1835 test_neg_set
1836 test_zero_clear
1837 test_ovf_clear
1838 test_carry_clear
1839
1840 test_gr_a5a5 0 ; Make sure *NO* general registers are changed
1841 test_gr_a5a5 1
1842 test_gr_a5a5 2
1843 test_gr_a5a5 3
1844 test_gr_a5a5 4
1845 test_gr_a5a5 5
1846 test_gr_a5a5 6
1847 test_gr_a5a5 7
1848
1849 ;; Now check the result of the move to memory.
1850 cmp.l #0x99999999, @long_dst
1851 beq .Lnext145
1852 fail
1853 .Lnext145:
1854 ;; Now clear the destination location, and verify that.
1855 mov.l #0x87654321, @long_dst
1856 cmp.l #0x99999999, @long_dst
1857 bne .Lnext146
1858 fail
1859 .Lnext146: ; OK, pass on.
1860
1861 .endif
1862
1863 pass
1864
1865 exit 0