sim/testsuite/h8300/addw.s

   1 # Hitachi H8 testcase 'add.w'
   2 # mach(): all
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12
  13         # Instructions tested:
  14         # add.w xx:3, rd        ; 0 a 0xxx rd   (sx only)
  15         # add.w xx:16, rd       ; 7 9 1 rd imm16
  16         # add.w rs, rd          ; 0 9 rs rd
  17         #
  18
  19         start
  20
  21 .if (sim_cpu == h8sx)           ; 3-bit immediate mode only for h8sx
  22 add_w_imm3:
  23         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  24         ;;  fixme set ccr
  25
  26         ;;  add.w #xx:3,Rd      ; Immediate 3-bit operand
  27         add.w   #7, r0          ; FIXME will not assemble yet
  28 ;       .word   0x0a70          ; Fake it until assembler will take it.
  29
  30         ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
  31         test_h_gr16 0xa5ac r0   ; add result:   a5a5 + 7
  32         test_h_gr32 0xa5a5a5ac er0      ; add result:   a5a5 + 7
  33         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  34         test_gr_a5a5 2
  35         test_gr_a5a5 3
  36         test_gr_a5a5 4
  37         test_gr_a5a5 5
  38         test_gr_a5a5 6
  39         test_gr_a5a5 7
  40 .endif
  41
  42 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
  43 add_w_imm16:
  44         ;; add.w immediate not available in h8300 mode.
  45         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  46         ;;  fixme set ccr
  47
  48         ;;  add.w #xx:16,Rd
  49         add.w   #0x111, r0      ; Immediate 16-bit operand
  50
  51         ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
  52         test_h_gr16 0xa6b6 r0   ; add result:   a5a5 + 111
  53         test_h_gr32 0xa5a5a6b6 er0      ; add result:   a5a5 + 111
  54         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  55         test_gr_a5a5 2
  56         test_gr_a5a5 3
  57         test_gr_a5a5 4
  58         test_gr_a5a5 5
  59         test_gr_a5a5 6
  60         test_gr_a5a5 7
  61 .endif
  62
  63 add_w_reg:
  64         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  65         ;;  fixme set ccr
  66
  67         ;;  add.w Rs,Rd
  68         mov.w   #0x111, r1
  69         add.w   r1, r0          ; Register operand
  70
  71         ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
  72         test_h_gr16 0xa6b6 r0   ; add result:   a5a5 + 111
  73         test_h_gr16 0x0111 r1
  74 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
  75         test_h_gr32 0xa5a5a6b6 er0      ; add result:   a5a5 + 111
  76         test_h_gr32 0xa5a50111 er1
  77 .endif
  78         test_gr_a5a5 2          ; Make sure other general regs not disturbed
  79         test_gr_a5a5 3
  80         test_gr_a5a5 4
  81         test_gr_a5a5 5
  82         test_gr_a5a5 6
  83         test_gr_a5a5 7
  84
  85         pass
  86
  87         exit 0