sim/testsuite/h8300/andb.s

   1 # Hitachi H8 testcase 'and.b'
   2 # mach(): all
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12
  13         # Instructions tested:
  14         # and.b #xx:8, rd       ;                     e rd   xxxxxxxx
  15         # and.b #xx:8, @erd     ;         7 d rd ???? e ???? xxxxxxxx
  16         # and.b #xx:8, @erd+    ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
  17         # and.b #xx:8, @erd-    ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
  18         # and.b #xx:8, @+erd    ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
  19         # and.b #xx:8, @-erd    ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
  20         # and.b rs, rd          ;                     1 6 rs rd
  21         # and.b reg8, @erd      ;         7 d rd ???? 1 6 rs ????
  22         # and.b reg8, @erd+     ;         0 1 7     9 8 rd 6 rs
  23         # and.b reg8, @erd-     ;         0 1 7     9 a rd 6 rs
  24         # and.b reg8, @+erd     ;         0 1 7     9 9 rd 6 rs
  25         # and.b reg8, @-erd     ;         0 1 7     9 b rd 6 rs
  26         #
  27         # andc #xx:8, ccr       ;         0 6 xxxxxxxx
  28         # andc #xx:8, exr       ; 0 1 4 1 0 6 xxxxxxxx
  29
  30         # Coming soon:
  31         # ...
  32
  33 .data
  34 pre_byte:       .byte 0
  35 byte_dest:      .byte 0xa5
  36 post_byte:      .byte 0
  37
  38         start
  39
  40 and_b_imm8_reg8:
  41         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  42         ;;  fixme set ccr
  43
  44         ;;  and.b #xx:8,Rd
  45         and.b   #0xaa, r0l      ; Immediate 8-bit operand
  46
  47         ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
  48         test_h_gr16 0xa5a0 r0   ; and result:   a5 & aa
  49 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
  50         test_h_gr32 0xa5a5a5a0 er0      ; and result:    a5 & aa
  51 .endif
  52         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  53         test_gr_a5a5 2
  54         test_gr_a5a5 3
  55         test_gr_a5a5 4
  56         test_gr_a5a5 5
  57         test_gr_a5a5 6
  58         test_gr_a5a5 7
  59
  60 .if (sim_cpu == h8sx)
  61 and_b_imm8_rdind:
  62         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  63         set_ccr_zero
  64
  65         ;;  and.b #xx:8,@eRd
  66         mov     #byte_dest, er0
  67         and.b   #0xaa:8, @er0   ; Immediate 8-bit src, reg indirect dst
  68 ;;;     .word   0x7d00
  69 ;;;     .word   0xe0aa
  70
  71         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
  72         test_ovf_clear
  73         test_zero_clear
  74         test_neg_set
  75
  76         test_h_gr32 byte_dest, er0      ; er0 still contains address
  77         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  78         test_gr_a5a5 2
  79         test_gr_a5a5 3
  80         test_gr_a5a5 4
  81         test_gr_a5a5 5
  82         test_gr_a5a5 6
  83         test_gr_a5a5 7
  84
  85         ;; Now check the result of the and to memory.
  86         sub.b   r0l, r0l
  87         mov.b   @byte_dest, r0l
  88         cmp.b   #0xa0, r0l
  89         beq     .L1
  90         fail
  91 .L1:
  92
  93 and_b_imm8_rdpostinc:
  94         mov     #byte_dest, er0
  95         mov.b   #0xa5, r1l
  96         mov.b   r1l, @er0
  97
  98         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  99         set_ccr_zero
 100
 101         ;;  and.b #xx:8,@eRd+
 102         mov     #byte_dest, er0
 103         and.b   #0x55:8, @er0+  ; Immediate 8-bit src, reg post-incr dest
 104 ;;;     .word   0x0174
 105 ;;;     .word   0x6c08
 106 ;;;     .word   0xe055
 107
 108         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 109         test_ovf_clear
 110         test_zero_clear
 111         test_neg_clear
 112
 113         test_h_gr32 post_byte, er0      ; er0 contains address plus one
 114         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 115         test_gr_a5a5 2
 116         test_gr_a5a5 3
 117         test_gr_a5a5 4
 118         test_gr_a5a5 5
 119         test_gr_a5a5 6
 120         test_gr_a5a5 7
 121
 122         ;; Now check the result of the and to memory.
 123         sub.b   r0l, r0l
 124         mov.b   @byte_dest, r0l
 125         cmp.b   #0x05, r0l
 126         beq     .L2
 127         fail
 128 .L2:
 129         ;; special case same register
 130         mov.l   #byte_dest, er0
 131         mov.b   @er0, r1h
 132         mov.b   r0l, r1l
 133         and.b   r0l, @er0+
 134         inc.b   r1l
 135         and.b   r1h, r1l
 136         mov.b   @byte_dest, r0l
 137         cmp.b   r1l, r0l
 138         beq     .L22
 139         fail
 140 .L22:
 141
 142 and_b_imm8_rdpostdec:
 143         mov     #byte_dest, er0
 144         mov.b   #0xa5, r1l
 145         mov.b   r1l, @er0
 146
 147         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 148         set_ccr_zero
 149
 150         ;;  and.b #xx:8,@eRd-
 151         mov     #byte_dest, er0
 152         and.b   #0xaa:8, @er0-  ; Immediate 8-bit src, reg post-decr dest
 153 ;;;     .word   0x0176
 154 ;;;     .word   0x6c08
 155 ;;;     .word   0xe0aa
 156
 157         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 158         test_ovf_clear
 159         test_zero_clear
 160         test_neg_set
 161
 162         test_h_gr32 pre_byte, er0       ; er0 contains address minus one
 163         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 164         test_gr_a5a5 2
 165         test_gr_a5a5 3
 166         test_gr_a5a5 4
 167         test_gr_a5a5 5
 168         test_gr_a5a5 6
 169         test_gr_a5a5 7
 170
 171         ;; Now check the result of the and to memory.
 172         sub.b   r0l, r0l
 173         mov.b   @byte_dest, r0l
 174         cmp.b   #0xa0, r0l
 175         beq     .L3
 176         fail
 177 .L3:
 178         ;; special case same register
 179         mov.l   #byte_dest, er0
 180         mov.b   @er0, r1h
 181         mov.b   r0l, r1l
 182         and.b   r0l, @er0-
 183         dec.b   r1l
 184         and.b   r1h, r1l
 185         mov.b   @byte_dest, r0l
 186         cmp.b   r1l, r0l
 187         beq     .L23
 188         fail
 189 .L23:
 190
 191 and_b_imm8_rdpreinc:
 192         mov     #byte_dest, er0
 193         mov.b   #0xa5, r1l
 194         mov.b   r1l, @er0
 195
 196         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 197         set_ccr_zero
 198
 199         ;;  and.b #xx:8,@+eRd
 200         mov     #pre_byte, er0
 201         and.b   #0x55:8, @+er0  ; Immediate 8-bit src, reg pre-incr dest
 202 ;;;     .word   0x0175
 203 ;;;     .word   0x6c08
 204 ;;;     .word   0xe055
 205
 206         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 207         test_ovf_clear
 208         test_zero_clear
 209         test_neg_clear
 210
 211         test_h_gr32 byte_dest, er0      ; er0 contains destination address
 212         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 213         test_gr_a5a5 2
 214         test_gr_a5a5 3
 215         test_gr_a5a5 4
 216         test_gr_a5a5 5
 217         test_gr_a5a5 6
 218         test_gr_a5a5 7
 219
 220         ;; Now check the result of the and to memory.
 221         sub.b   r0l, r0l
 222         mov.b   @byte_dest, r0l
 223         cmp.b   #0x05, r0l
 224         beq     .L4
 225         fail
 226 .L4:
 227         ;; special case same register
 228         mov.l   #pre_byte, er0
 229         mov.b   @byte_dest, r1h
 230         mov.b   r0l, r1l
 231         and.b   r0l, @+er0
 232         inc.b   r1l
 233         and.b   r1h, r1l
 234         mov.b   @byte_dest, r0l
 235         cmp.b   r1l, r0l
 236         beq     .L24
 237         fail
 238 .L24:
 239
 240 and_b_imm8_rdpredec:
 241         mov     #byte_dest, er0
 242         mov.b   #0xa5, r1l
 243         mov.b   r1l, @er0
 244
 245         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 246         set_ccr_zero
 247
 248         ;;  and.b #xx:8,@-eRd
 249         mov     #post_byte, er0
 250         and.b   #0xaa:8, @-er0  ; Immediate 8-bit src, reg pre-decr dest
 251 ;;;     .word   0x0177
 252 ;;;     .word   0x6c08
 253 ;;;     .word   0xe0aa
 254
 255         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 256         test_ovf_clear
 257         test_zero_clear
 258         test_neg_set
 259
 260         test_h_gr32 byte_dest, er0      ; er0 contains destination address
 261         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 262         test_gr_a5a5 2
 263         test_gr_a5a5 3
 264         test_gr_a5a5 4
 265         test_gr_a5a5 5
 266         test_gr_a5a5 6
 267         test_gr_a5a5 7
 268
 269         ;; Now check the result of the and to memory.
 270         sub.b   r0l, r0l
 271         mov.b   @byte_dest, r0l
 272         cmp.b   #0xa0, r0l
 273         beq     .L5
 274         fail
 275 .L5:
 276         ;; special case same register
 277         mov.l   #post_byte, er0
 278         mov.b   @byte_dest, r1h
 279         mov.b   r0l, r1l
 280         and.b   r0l, @-er0
 281         dec.b   r1l
 282         and.b   r1h, r1l
 283         mov.b   @byte_dest, r0l
 284         cmp.b   r1l, r0l
 285         beq     .L25
 286         fail
 287 .L25:
 288
 289 .endif                          ; h8sx
 290
 291 and_b_reg8_reg8:
 292         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 293         ;;  fixme set ccr
 294
 295         ;;  and.b Rs,Rd
 296         mov.b   #0xaa, r0h
 297         and.b   r0h, r0l        ; Register operand
 298
 299         ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
 300         test_h_gr16 0xaaa0 r0   ; and result:   a5 & aa
 301 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
 302         test_h_gr32 0xa5a5aaa0 er0      ; and result:   a5 & aa
 303 .endif
 304         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 305         test_gr_a5a5 2
 306         test_gr_a5a5 3
 307         test_gr_a5a5 4
 308         test_gr_a5a5 5
 309         test_gr_a5a5 6
 310         test_gr_a5a5 7
 311
 312 .if (sim_cpu == h8sx)
 313 and_b_reg8_rdind:
 314         mov     #byte_dest, er0
 315         mov.b   #0xa5, r1l
 316         mov.b   r1l, @er0
 317
 318         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 319         set_ccr_zero
 320
 321         ;;  and.b rs8,@eRd      ; And to register indirect
 322         mov     #byte_dest, er0
 323         mov     #0x55, r1l
 324         and.b   r1l, @er0       ; reg8 src, reg indirect dest
 325 ;;;     .word   0x7d00
 326 ;;;     .word   0x1690
 327
 328         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 329         test_ovf_clear
 330         test_zero_clear
 331         test_neg_clear
 332
 333         test_h_gr32 byte_dest er0       ; er0 still contains address
 334         test_h_gr32 0xa5a5a555 er1      ; er1 has the test load
 335
 336         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 337         test_gr_a5a5 3
 338         test_gr_a5a5 4
 339         test_gr_a5a5 5
 340         test_gr_a5a5 6
 341         test_gr_a5a5 7
 342
 343         ;; Now check the result of the and to memory.
 344         sub.b   r0l, r0l
 345         mov.b   @byte_dest, r0l
 346         cmp.b   #0x05, r0l
 347         beq     .L6
 348         fail
 349 .L6:
 350
 351 and_b_reg8_rdpostinc:
 352         mov     #byte_dest, er0
 353         mov.b   #0xa5, r1l
 354         mov.b   r1l, @er0
 355
 356         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 357         set_ccr_zero
 358
 359         ;;  and.b rs8,@eRd+     ; And to register post-incr
 360         mov     #byte_dest, er0
 361         mov     #0xaa, r1l
 362         and.b   r1l, @er0+      ; reg8 src, reg post-incr dest
 363 ;;;     .word   0x0179
 364 ;;;     .word   0x8069
 365
 366         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 367         test_ovf_clear
 368         test_zero_clear
 369         test_neg_set
 370
 371         test_h_gr32 post_byte er0       ; er0 contains address plus one
 372         test_h_gr32 0xa5a5a5aa er1      ; er1 has the test load
 373
 374         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 375         test_gr_a5a5 3
 376         test_gr_a5a5 4
 377         test_gr_a5a5 5
 378         test_gr_a5a5 6
 379         test_gr_a5a5 7
 380
 381         ;; Now check the result of the and to memory.
 382         sub.b   r0l, r0l
 383         mov.b   @byte_dest, r0l
 384         cmp.b   #0xa0, r0l
 385         beq     .L7
 386         fail
 387 .L7:
 388
 389 and_b_reg8_rdpostdec:
 390         mov     #byte_dest, er0
 391         mov.b   #0xa5, r1l
 392         mov.b   r1l, @er0
 393
 394         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 395         set_ccr_zero
 396
 397         ;;  and.b rs8,@eRd-     ; And to register post-decr
 398         mov     #byte_dest, er0
 399         mov     #0x55, r1l
 400         and.b   r1l, @er0-      ; reg8 src, reg post-decr dest
 401 ;;;     .word   0x0179
 402 ;;;     .word   0xa069
 403
 404         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 405         test_ovf_clear
 406         test_zero_clear
 407         test_neg_clear
 408
 409         test_h_gr32 pre_byte er0        ; er0 contains address minus one
 410         test_h_gr32 0xa5a5a555 er1      ; er1 has the test load
 411
 412         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 413         test_gr_a5a5 3
 414         test_gr_a5a5 4
 415         test_gr_a5a5 5
 416         test_gr_a5a5 6
 417         test_gr_a5a5 7
 418
 419         ;; Now check the result of the and to memory.
 420         sub.b   r0l, r0l
 421         mov.b   @byte_dest, r0l
 422         cmp.b   #0x05, r0l
 423         beq     .L8
 424         fail
 425 .L8:
 426
 427 and_b_reg8_rdpreinc:
 428         mov     #byte_dest, er0
 429         mov.b   #0xa5, r1l
 430         mov.b   r1l, @er0
 431
 432         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 433         set_ccr_zero
 434
 435         ;;  and.b rs8,@+eRd     ; And to register post-incr
 436         mov     #pre_byte, er0
 437         mov     #0xaa, r1l
 438         and.b   r1l, @+er0      ; reg8 src, reg post-incr dest
 439 ;;;     .word   0x0179
 440 ;;;     .word   0x9069
 441
 442         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 443         test_ovf_clear
 444         test_zero_clear
 445         test_neg_set
 446
 447         test_h_gr32 byte_dest er0       ; er0 contains destination address
 448         test_h_gr32 0xa5a5a5aa er1      ; er1 has the test load
 449
 450         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 451         test_gr_a5a5 3
 452         test_gr_a5a5 4
 453         test_gr_a5a5 5
 454         test_gr_a5a5 6
 455         test_gr_a5a5 7
 456
 457         ;; Now check the result of the and to memory.
 458         sub.b   r0l, r0l
 459         mov.b   @byte_dest, r0l
 460         cmp.b   #0xa0, r0l
 461         beq     .L9
 462         fail
 463 .L9:
 464
 465 and_b_reg8_rdpredec:
 466         mov     #byte_dest, er0
 467         mov.b   #0xa5, r1l
 468         mov.b   r1l, @er0
 469
 470         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 471         set_ccr_zero
 472
 473         ;;  and.b rs8,@-eRd     ; And to register post-decr
 474         mov     #post_byte, er0
 475         mov     #0x55, r1l
 476         and.b   r1l, @-er0      ; reg8 src, reg post-decr dest
 477 ;;;     .word   0x0179
 478 ;;;     .word   0xb069
 479
 480         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 481         test_ovf_clear
 482         test_zero_clear
 483         test_neg_clear
 484
 485         test_h_gr32 byte_dest er0       ; er0 contains destination address
 486         test_h_gr32 0xa5a5a555 er1      ; er1 has the test load
 487
 488         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 489         test_gr_a5a5 3
 490         test_gr_a5a5 4
 491         test_gr_a5a5 5
 492         test_gr_a5a5 6
 493         test_gr_a5a5 7
 494
 495         ;; Now check the result of the and to memory.
 496         sub.b   r0l, r0l
 497         mov.b   @byte_dest, r0l
 498         cmp.b   #0x05, r0l
 499         beq     .L10
 500         fail
 501 .L10:
 502 .endif                          ; h8sx
 503
 504 andc_imm8_ccr:
 505         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 506         set_ccr_zero
 507
 508         ;;  andc #xx:8,ccr
 509         set_ccr 0xff
 510
 511         test_neg_set
 512         andc    #0xf7, ccr      ; Immediate 8-bit operand (neg flag)
 513         test_neg_clear
 514
 515         test_zero_set
 516         andc    #0xfb, ccr      ; Immediate 8-bit operand (zero flag)
 517         test_zero_clear
 518
 519         test_ovf_set
 520         andc    #0xfd, ccr      ; Immediate 8-bit operand (overflow flag)
 521         test_ovf_clear
 522
 523         test_carry_set
 524         andc    #0xfe, ccr      ; Immediate 8-bit operand (carry flag)
 525         test_carry_clear
 526
 527         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 528         test_gr_a5a5 1
 529         test_gr_a5a5 2
 530         test_gr_a5a5 3
 531         test_gr_a5a5 4
 532         test_gr_a5a5 5
 533         test_gr_a5a5 6
 534         test_gr_a5a5 7
 535
 536 .if (sim_cpu == h8300s || sim_cpu == h8sx)      ; Earlier versions, no exr
 537 andc_imm8_exr:
 538         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 539
 540         ldc     #0xff, exr
 541         stc     exr, r0l
 542         test_h_gr8 0x87, r0l
 543
 544         ;;  andc #xx:8,exr
 545         set_ccr_zero
 546         andc    #0x7f, exr
 547         test_cc_clear
 548         stc     exr, r0l
 549         test_h_gr8 0x7, r0l
 550
 551         andc    #0x3, exr
 552         stc     exr, r0l
 553         test_h_gr8 0x3, r0l
 554
 555         andc    #0x1, exr
 556         stc     exr, r0l
 557         test_h_gr8 0x1, r0l
 558
 559         andc    #0x0, exr
 560         stc     exr, r0l
 561         test_h_gr8 0x0, r0l
 562
 563         test_h_gr32  0xa5a5a500 er0
 564         test_gr_a5a5 1
 565         test_gr_a5a5 2
 566         test_gr_a5a5 3
 567         test_gr_a5a5 4
 568         test_gr_a5a5 5
 569         test_gr_a5a5 6
 570         test_gr_a5a5 7
 571 .endif                          ; not h8300 or h8300h
 572
 573         pass
 574
 575         exit 0