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[binutils-gdb.git] / sim / testsuite / h8300 / cmpb.s
1 # Hitachi H8 testcase 'cmp.b'
2 # mach(): all
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
10
11 .include "testutils.inc"
12
13 # Instructions tested:
14 # cmp.b #xx:8, rd ; a rd xxxxxxxx
15 # cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx
16 # cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
17 # cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
18 # cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
19 # cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
20 # cmp.b rs, rd ; 1 c rs rd
21 # cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ????
22 # cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs
23 # cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs
24 # cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs
25 # cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs
26 # cmp.b rsind, rdind ; 7 c 0rs 5 0 ?rd 2 ????
27 # cmp.b rspostinc, rdpostinc ; 0 1 7 4 6 c 0rs c 8 ?rd 2 ????
28 # cmp.b rspostdec, rdpostdec ; 0 1 7 6 6 c 0rs c a ?rd 2 ????
29 # cmp.b rspreinc, rdpreinc ; 0 1 7 5 6 c 0rs c 9 ?rd 2 ????
30 # cmp.b rspredec, rdpredec ; 0 1 7 7 6 c 0rs c b ?rd 2 ????
31 # cmp.b disp2, disp2 ; 0 1 7 01dd:2 6 8 0rs c 00dd:2 ?rd 2 ????
32 # cmp.b disp16, disp16 ; 0 1 7 4 6 e 0rs c dd:16 c 0rd 2 ???? dd:16
33 # cmp.b disp32, disp32 ; 7 8 0rs 4 6 a 2 c dd:32 c 1rd 2 ???? dd:32
34 # cmp.b indexb16, indexb16 ; 0 1 7 5 6 e 0rs c dd:16 d 0rd 2 ???? dd:16
35 # cmp.b indexw16, indexw16 ; 0 1 7 6 6 e 0rs c dd:16 e 0rd 2 ???? dd:16
36 # cmp.b indexl16, indexl16 ; 0 1 7 7 6 e 0rs c dd:16 f 0rd 2 ???? dd:16
37 # cmp.b indexb32, indexb32 ; 7 8 0rs 5 6 a 2 c dd:32 d 1rd 2 ???? dd:32
38 # cmp.b indexw32, indexw32 ; 7 8 0rs 6 6 a 2 c dd:32 e 1rd 2 ???? dd:32
39 # cmp.b indexl32, indexl32 ; 7 8 0rs 7 6 a 2 c dd:32 f 1rd 2 ???? dd:32
40 # cmp.b abs16, abs16 ; 6 a 1 5 aa:16 4 0??? 2 ???? aa:16
41 # cmp.b abs32, abs32 ; 6 a 3 5 aa:32 4 1??? 2 ???? aa:32
42 #
43
44 # Coming soon:
45
46 # ...
47
48 .data
49 byte_src: .byte 0x5a
50 pre_byte: .byte 0
51 byte_dst: .byte 0xa5
52 post_byte: .byte 0
53
54 start
55
56 cmp_b_imm8_reg8:
57 set_grs_a5a5 ; Fill all general regs with a fixed pattern
58 ;; fixme set ccr
59
60 ;; cmp.b #xx:8,Rd
61 cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest
62 beq .Leq1
63 fail
64 .Leq1: cmp.b #0xa6, r0l
65 blt .Llt1
66 fail
67 .Llt1: cmp.b #0xa4, r0l
68 bgt .Lgt1
69 fail
70 .Lgt1:
71 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
72 test_h_gr16 0xa5a5 r0 ; r0 unchanged
73 .if (sim_cpu) ; non-zero means h8300h, s, or sx
74 test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
75 .endif
76 test_gr_a5a5 1 ; Make sure other general regs not disturbed
77 test_gr_a5a5 2
78 test_gr_a5a5 3
79 test_gr_a5a5 4
80 test_gr_a5a5 5
81 test_gr_a5a5 6
82 test_gr_a5a5 7
83
84 .if (sim_cpu == h8sx)
85 cmp_b_imm8_rdind:
86 set_grs_a5a5 ; Fill all general regs with a fixed pattern
87 set_ccr_zero
88
89 ;; cmp.b #xx:8,@eRd
90 mov #byte_dst, er0
91 cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst
92 ;;; .word 0x7d00
93 ;;; .word 0xa0a5
94 beq .Leq2
95 fail
96 .Leq2: set_ccr_zero
97 cmp.b #0xa6, @er0
98 ;;; .word 0x7d00
99 ;;; .word 0xa0a6
100 blt .Llt2
101 fail
102 .Llt2: set_ccr_zero
103 cmp.b #0xa4, @er0
104 ;;; .word 0x7d00
105 ;;; .word 0xa0a4
106 bgt .Lgt2
107 fail
108 .Lgt2:
109 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
110 test_ovf_clear
111 test_zero_clear
112 test_neg_clear
113
114 test_h_gr32 byte_dst er0 ; er0 still contains address
115 test_gr_a5a5 1 ; Make sure other general regs not disturbed
116 test_gr_a5a5 2
117 test_gr_a5a5 3
118 test_gr_a5a5 4
119 test_gr_a5a5 5
120 test_gr_a5a5 6
121 test_gr_a5a5 7
122
123 ;; Now check the result of the cmp to memory (memory unchanged).
124 sub.b r0l, r0l
125 mov.b @byte_dst, r0l
126 cmp.b #0xa5, r0l
127 beq .L2
128 fail
129 .L2:
130
131 cmp_b_imm8_rdpostinc:
132 set_grs_a5a5 ; Fill all general regs with a fixed pattern
133 set_ccr_zero
134
135 ;; cmp.b #xx:8,@eRd+
136 mov #byte_dst, er0
137 cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst
138 ;;; .word 0x0174
139 ;;; .word 0x6c08
140 ;;; .word 0xa0a5
141 beq .Leq3
142 fail
143 .Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one
144 mov #byte_dst, er0
145 set_ccr_zero
146 cmp.b #0xa6, @er0+
147 ;;; .word 0x0174
148 ;;; .word 0x6c08
149 ;;; .word 0xa0a6
150 blt .Llt3
151 fail
152 .Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one
153 mov #byte_dst, er0
154 set_ccr_zero
155 cmp.b #0xa4, @er0+
156 ;;; .word 0x0174
157 ;;; .word 0x6c08
158 ;;; .word 0xa0a4
159 bgt .Lgt3
160 fail
161 .Lgt3:
162 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
163 test_ovf_clear
164 test_zero_clear
165 test_neg_clear
166
167 test_h_gr32 post_byte er0 ; er0 contains address plus one
168 test_gr_a5a5 1 ; Make sure other general regs not disturbed
169 test_gr_a5a5 2
170 test_gr_a5a5 3
171 test_gr_a5a5 4
172 test_gr_a5a5 5
173 test_gr_a5a5 6
174 test_gr_a5a5 7
175
176 ;; Now check the result of the cmp to memory (memory unchanged).
177 sub.b r0l, r0l
178 mov.b @byte_dst, r0l
179 cmp.b #0xa5, r0l
180 beq .L3
181 fail
182 .L3:
183
184 cmp_b_imm8_rdpostdec:
185 set_grs_a5a5 ; Fill all general regs with a fixed pattern
186 set_ccr_zero
187
188 ;; cmp.b #xx:8,@eRd-
189 mov #byte_dst, er0
190 cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst
191 ;;; .word 0x0176
192 ;;; .word 0x6c08
193 ;;; .word 0xa0a5
194 beq .Leq4
195 fail
196 .Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one
197 mov #byte_dst, er0
198 set_ccr_zero
199 cmp.b #0xa6, @er0-
200 ;;; .word 0x0176
201 ;;; .word 0x6c08
202 ;;; .word 0xa0a6
203 blt .Llt4
204 fail
205 .Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one
206 mov #byte_dst, er0
207 set_ccr_zero
208 cmp.b #0xa4, @er0-
209 ;;; .word 0x0176
210 ;;; .word 0x6c08
211 ;;; .word 0xa0a4
212 bgt .Lgt4
213 fail
214 .Lgt4:
215 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
216 test_ovf_clear
217 test_zero_clear
218 test_neg_clear
219
220 test_h_gr32 pre_byte er0 ; er0 contains address minus one
221 test_gr_a5a5 1 ; Make sure other general regs not disturbed
222 test_gr_a5a5 2
223 test_gr_a5a5 3
224 test_gr_a5a5 4
225 test_gr_a5a5 5
226 test_gr_a5a5 6
227 test_gr_a5a5 7
228
229 ;; Now check the result of the cmp to memory (memory unchanged).
230 sub.b r0l, r0l
231 mov.b @byte_dst, r0l
232 cmp.b #0xa5, r0l
233 beq .L4
234 fail
235 .L4:
236
237 cmp_b_imm8_rdpreinc:
238 set_grs_a5a5 ; Fill all general regs with a fixed pattern
239 set_ccr_zero
240
241 ;; cmp.b #xx:8,@+eRd
242 mov #pre_byte, er0
243 cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst
244 ;;; .word 0x0175
245 ;;; .word 0x6c08
246 ;;; .word 0xa0a5
247 beq .Leq5
248 fail
249 .Leq5: test_h_gr32 byte_dst er0 ; er0 contains destination address
250 mov #pre_byte, er0
251 set_ccr_zero
252 cmp.b #0xa6, @+er0
253 ;;; .word 0x0175
254 ;;; .word 0x6c08
255 ;;; .word 0xa0a6
256 blt .Llt5
257 fail
258 .Llt5: test_h_gr32 byte_dst er0 ; er0 contains destination address
259 mov #pre_byte, er0
260 set_ccr_zero
261 cmp.b #0xa4, @+er0
262 ;;; .word 0x0175
263 ;;; .word 0x6c08
264 ;;; .word 0xa0a4
265 bgt .Lgt5
266 fail
267 .Lgt5:
268 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
269 test_ovf_clear
270 test_zero_clear
271 test_neg_clear
272
273 test_h_gr32 byte_dst er0 ; er0 contains destination address
274 test_gr_a5a5 1 ; Make sure other general regs not disturbed
275 test_gr_a5a5 2
276 test_gr_a5a5 3
277 test_gr_a5a5 4
278 test_gr_a5a5 5
279 test_gr_a5a5 6
280 test_gr_a5a5 7
281
282 ;; Now check the result of the cmp to memory (memory unchanged).
283 sub.b r0l, r0l
284 mov.b @byte_dst, r0l
285 cmp.b #0xa5, r0l
286 beq .L5
287 fail
288 .L5:
289
290 cmp_b_imm8_rdpredec:
291 set_grs_a5a5 ; Fill all general regs with a fixed pattern
292 set_ccr_zero
293
294 ;; cmp.b #xx:8,@-eRd
295 mov #post_byte, er0
296 cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst
297 ;;; .word 0x0177
298 ;;; .word 0x6c08
299 ;;; .word 0xa0a5
300 beq .Leq6
301 fail
302 .Leq6: test_h_gr32 byte_dst er0 ; er0 contains destination address
303 mov #post_byte, er0
304 set_ccr_zero
305 cmp.b #0xa6, @-er0
306 ;;; .word 0x0177
307 ;;; .word 0x6c08
308 ;;; .word 0xa0a6
309 blt .Llt6
310 fail
311 .Llt6: test_h_gr32 byte_dst er0 ; er0 contains destination address
312 mov #post_byte, er0
313 set_ccr_zero
314 cmp.b #0xa4, @-er0
315 ;;; .word 0x0177
316 ;;; .word 0x6c08
317 ;;; .word 0xa0a4
318 bgt .Lgt6
319 fail
320 .Lgt6:
321 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
322 test_ovf_clear
323 test_zero_clear
324 test_neg_clear
325
326 test_h_gr32 byte_dst er0 ; er0 contains destination address
327 test_gr_a5a5 1 ; Make sure other general regs not disturbed
328 test_gr_a5a5 2
329 test_gr_a5a5 3
330 test_gr_a5a5 4
331 test_gr_a5a5 5
332 test_gr_a5a5 6
333 test_gr_a5a5 7
334
335 ;; Now check the result of the cmp to memory (memory unchanged).
336 sub.b r0l, r0l
337 mov.b @byte_dst, r0l
338 cmp.b #0xa5, r0l
339 beq .L6
340 fail
341 .L6:
342
343
344 .endif
345
346 cmp_b_reg8_reg8:
347 set_grs_a5a5 ; Fill all general regs with a fixed pattern
348 ;; fixme set ccr
349
350 ;; cmp.b Rs,Rd
351 mov.b #0xa5, r0h
352 cmp.b r0h, r0l ; Reg8 src, reg8 dst
353 beq .Leq7
354 fail
355 .Leq7: mov.b #0xa6, r0h
356 cmp.b r0h, r0l
357 blt .Llt7
358 fail
359 .Llt7: mov.b #0xa4, r0h
360 cmp.b r0h, r0l
361 bgt .Lgt7
362 fail
363 .Lgt7:
364 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
365 test_h_gr16 0xa4a5 r0 ; r0l unchanged.
366 .if (sim_cpu) ; non-zero means h8300h, s, or sx
367 test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged
368 .endif
369 test_gr_a5a5 1 ; Make sure other general regs not disturbed
370 test_gr_a5a5 2
371 test_gr_a5a5 3
372 test_gr_a5a5 4
373 test_gr_a5a5 5
374 test_gr_a5a5 6
375 test_gr_a5a5 7
376
377 .if (sim_cpu == h8sx)
378 cmp_b_reg8_rdind:
379 set_grs_a5a5 ; Fill all general regs with a fixed pattern
380 set_ccr_zero
381
382 ;; cmp.b rs8,@eRd ; cmp reg8 to register indirect
383 mov #byte_dst, er0
384 mov #0xa5, r1l
385 cmp.b r1l, @er0 ; reg8 src, reg indirect dest
386 ;;; .word 0x7d00
387 ;;; .word 0x1c90
388 beq .Leq8
389 fail
390 .Leq8: set_ccr_zero
391 mov #0xa6, r1l
392 cmp.b r1l, @er0
393 ;;; .word 0x7d00
394 ;;; .word 0x1c90
395 blt .Llt8
396 fail
397 .Llt8: set_ccr_zero
398 mov #0xa4, r1l
399 cmp.b r1l, @er0
400 ;;; .word 0x7d00
401 ;;; .word 0x1c90
402 bgt .Lgt8
403 fail
404 .Lgt8:
405 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
406 test_ovf_clear
407 test_zero_clear
408 test_neg_clear
409
410 test_h_gr32 byte_dst er0 ; er0 still contains address
411 test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load
412
413 test_gr_a5a5 2 ; Make sure other general regs not disturbed
414 test_gr_a5a5 3
415 test_gr_a5a5 4
416 test_gr_a5a5 5
417 test_gr_a5a5 6
418 test_gr_a5a5 7
419
420 ;; Now check the result of the cmp to memory (no change).
421 sub.b r0l, r0l
422 mov.b @byte_dst, r0l
423 cmp.b #0xa5, r0l
424 beq .L8
425 fail
426 .L8:
427
428 cmp_b_reg8_rdpostinc:
429 set_grs_a5a5 ; Fill all general regs with a fixed pattern
430 set_ccr_zero
431
432 ;; cmp.b reg8,@eRd+
433 mov #byte_dst, er0
434 mov #0xa5, r1l
435 cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst
436 ;;; .word 0x0179
437 ;;; .word 0x8029
438 beq .Leq9
439 fail
440 .Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one
441 mov #byte_dst er0
442 mov #0xa6, r1l
443 set_ccr_zero
444 cmp.b r1l, @er0+
445 ;;; .word 0x0179
446 ;;; .word 0x8029
447 blt .Llt9
448 fail
449 .Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one
450 mov #byte_dst er0
451 mov #0xa4, r1l
452 set_ccr_zero
453 cmp.b r1l, @er0+
454 ;;; .word 0x0179
455 ;;; .word 0x8029
456 bgt .Lgt9
457 fail
458 .Lgt9:
459 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
460 test_ovf_clear
461 test_zero_clear
462 test_neg_clear
463
464 test_h_gr32 post_byte er0 ; er0 contains address plus one
465 test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
466 test_gr_a5a5 2 ; Make sure other general regs not disturbed
467 test_gr_a5a5 3
468 test_gr_a5a5 4
469 test_gr_a5a5 5
470 test_gr_a5a5 6
471 test_gr_a5a5 7
472
473 ;; Now check the result of the cmp to memory (memory unchanged).
474 sub.b r0l, r0l
475 mov.b @byte_dst, r0l
476 cmp.b #0xa5, r0l
477 beq .L9
478 fail
479 .L9:
480 ;; special case same register
481 mov.l #byte_dst, er0
482 mov.b @er0, r1h
483 mov.b r0l, r1l
484 inc.b r1l
485 mov.b r1l,@er0
486 cmp.b r0l,@er0+
487 beq .L19
488 fail
489 .L19:
490 mov.b r1h, @byte_dst
491
492 cmp_b_reg8_rdpostdec:
493 set_grs_a5a5 ; Fill all general regs with a fixed pattern
494 set_ccr_zero
495
496 ;; cmp.b reg8,@eRd-
497 mov #byte_dst, er0
498 mov #0xa5, r1l
499 cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst
500 ;;; .word 0x0179
501 ;;; .word 0xa029
502 beq .Leq10
503 fail
504 .Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one
505 mov #byte_dst er0
506 mov #0xa6, r1l
507 set_ccr_zero
508 cmp.b r1l, @er0-
509 ;;; .word 0x0179
510 ;;; .word 0xa029
511 blt .Llt10
512 fail
513 .Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one
514 mov #byte_dst er0
515 mov #0xa4, r1l
516 set_ccr_zero
517 cmp.b r1l, @er0-
518 ;;; .word 0x0179
519 ;;; .word 0xa029
520 bgt .Lgt10
521 fail
522 .Lgt10:
523 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
524 test_ovf_clear
525 test_zero_clear
526 test_neg_clear
527
528 test_h_gr32 pre_byte er0 ; er0 contains address minus one
529 test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
530 test_gr_a5a5 2 ; Make sure other general regs not disturbed
531 test_gr_a5a5 3
532 test_gr_a5a5 4
533 test_gr_a5a5 5
534 test_gr_a5a5 6
535 test_gr_a5a5 7
536
537 ;; Now check the result of the cmp to memory (memory unchanged).
538 sub.b r0l, r0l
539 mov.b @byte_dst, r0l
540 cmp.b #0xa5, r0l
541 beq .L10
542 fail
543 .L10:
544 ;; special case same register
545 mov.l #byte_dst, er0
546 mov.b @er0, r1h
547 mov.b r0l, r1l
548 dec.b r1l
549 mov.b r1l,@er0
550 cmp.b r0l,@er0-
551 beq .L20
552 fail
553 .L20:
554 mov.b r1h, @byte_dst
555
556 cmp_b_reg8_rdpreinc:
557 set_grs_a5a5 ; Fill all general regs with a fixed pattern
558 set_ccr_zero
559
560 ;; cmp.b reg8,@+eRd
561 mov #pre_byte, er0
562 mov #0xa5, r1l
563 cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst
564 ;;; .word 0x0179
565 ;;; .word 0x9029
566 beq .Leq11
567 fail
568 .Leq11: test_h_gr32 byte_dst er0 ; er0 contains destination address
569 mov #pre_byte er0
570 mov #0xa6, r1l
571 set_ccr_zero
572 cmp.b r1l, @+er0
573 ;;; .word 0x0179
574 ;;; .word 0x9029
575 blt .Llt11
576 fail
577 .Llt11: test_h_gr32 byte_dst er0 ; er0 contains destination address
578 mov #pre_byte er0
579 mov #0xa4, r1l
580 set_ccr_zero
581 cmp.b r1l, @+er0
582 ;;; .word 0x0179
583 ;;; .word 0x9029
584 bgt .Lgt11
585 fail
586 .Lgt11:
587 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
588 test_ovf_clear
589 test_zero_clear
590 test_neg_clear
591
592 test_h_gr32 byte_dst er0 ; er0 contains destination address
593 test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
594 test_gr_a5a5 2 ; Make sure other general regs not disturbed
595 test_gr_a5a5 3
596 test_gr_a5a5 4
597 test_gr_a5a5 5
598 test_gr_a5a5 6
599 test_gr_a5a5 7
600
601 ;; Now check the result of the cmp to memory (memory unchanged).
602 sub.b r0l, r0l
603 mov.b @byte_dst, r0l
604 cmp.b #0xa5, r0l
605 beq .L11
606 fail
607 .L11:
608 ;; special case same register
609 mov.l #pre_byte, er0
610 mov.b @byte_dst, r1h
611 mov.b r0l, r1l
612 inc.b r1l
613 mov.b r1l,@(1,er0)
614 cmp.b r0l,@+er0
615 beq .L21
616 fail
617 .L21:
618 mov.b r1h, @byte_dst
619
620 cmp_b_reg8_rdpredec:
621 set_grs_a5a5 ; Fill all general regs with a fixed pattern
622 set_ccr_zero
623
624 ;; cmp.b reg8,@-eRd
625 mov #post_byte, er0
626 mov #0xa5, r1l
627 cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst
628 ;;; .word 0x0179
629 ;;; .word 0xb029
630 beq .Leq12
631 fail
632 .Leq12: test_h_gr32 byte_dst er0 ; er0 contains destination address
633 mov #post_byte er0
634 mov #0xa6, r1l
635 set_ccr_zero
636 cmp.b r1l, @-er0
637 ;;; .word 0x0179
638 ;;; .word 0xb029
639 blt .Llt12
640 fail
641 .Llt12: test_h_gr32 byte_dst er0 ; er0 contains destination address
642 mov #post_byte er0
643 mov #0xa4, r1l
644 set_ccr_zero
645 cmp.b r1l, @-er0
646 ;;; .word 0x0179
647 ;;; .word 0xb029
648 bgt .Lgt12
649 fail
650 .Lgt12:
651 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
652 test_ovf_clear
653 test_zero_clear
654 test_neg_clear
655
656 test_h_gr32 byte_dst er0 ; er0 contains destination address
657 test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
658 test_gr_a5a5 2 ; Make sure other general regs not disturbed
659 test_gr_a5a5 3
660 test_gr_a5a5 4
661 test_gr_a5a5 5
662 test_gr_a5a5 6
663 test_gr_a5a5 7
664
665 ;; Now check the result of the cmp to memory (memory unchanged).
666 sub.b r0l, r0l
667 mov.b @byte_dst, r0l
668 cmp.b #0xa5, r0l
669 beq .L12
670 fail
671 .L12:
672 ;; special case same register
673 mov.l #post_byte, er0
674 mov.b @byte_dst, r1h
675 mov.b r0l, r1l
676 dec.b r1l
677 mov.b r1l,@(-1,er0)
678 cmp.b r0l,@-er0
679 beq .L22
680 fail
681 .L22:
682 mov.b r1h, @byte_dst
683
684 cmp_b_rsind_rdind:
685 set_grs_a5a5 ; Fill all general regs with a fixed pattern
686 mov #byte_src, er1
687 mov #byte_dst, er2
688 set_ccr_zero
689 cmp.b @er1, @er2
690 test_neg_clear ; N=0, Z=0, V=1, C=0
691 test_zero_clear
692 test_ovf_set
693 test_carry_clear
694
695 test_gr_a5a5 0
696 test_h_gr32 byte_src er1
697 test_h_gr32 byte_dst er2
698 test_gr_a5a5 3
699 test_gr_a5a5 4
700 test_gr_a5a5 5
701 test_gr_a5a5 6
702 test_gr_a5a5 7
703 cmp.b #0x5a, @byte_src:16
704 bne fail1
705 cmp.b #0xa5, @byte_dst:16
706 bne fail1
707 .if 1 ; ambiguous
708 cmp_b_rspostinc_rdpostinc:
709 set_grs_a5a5 ; Fill all general regs with a fixed pattern
710 mov #byte_src, er1
711 mov #byte_dst, er2
712 set_ccr_zero
713 cmp.b @er1+, @er2+
714 ;;; .word 0x0174
715 ;;; .word 0x6c1c
716 ;;; .word 0x8220
717
718 test_neg_clear ; N=0, Z=0, V=1, C=0
719 test_zero_clear
720 test_ovf_set
721 test_carry_clear
722
723 test_gr_a5a5 0
724 test_h_gr32 byte_src+1 er1
725 test_h_gr32 byte_dst+1 er2
726 test_gr_a5a5 3
727 test_gr_a5a5 4
728 test_gr_a5a5 5
729 test_gr_a5a5 6
730 test_gr_a5a5 7
731 cmp.b #0x5a, @byte_src:16
732 bne fail1
733 cmp.b #0xa5, @byte_dst:16
734 bne fail1
735 .endif
736 .if 1 ; ambiguous
737 cmp_b_rspostdec_rdpostdec:
738 set_grs_a5a5 ; Fill all general regs with a fixed pattern
739 mov #byte_src, er1
740 mov #byte_dst, er2
741 set_ccr_zero
742 cmp.b @er1-, @er2-
743 ;;; .word 0x0176
744 ;;; .word 0x6c1c
745 ;;; .word 0xa220
746
747 test_neg_clear ; N=0, Z=0, V=1, C=0
748 test_zero_clear
749 test_ovf_set
750 test_carry_clear
751
752 test_gr_a5a5 0
753 test_h_gr32 byte_src-1 er1
754 test_h_gr32 byte_dst-1 er2
755 test_gr_a5a5 3
756 test_gr_a5a5 4
757 test_gr_a5a5 5
758 test_gr_a5a5 6
759 test_gr_a5a5 7
760 cmp.b #0x5a, @byte_src:16
761 bne fail1
762 cmp.b #0xa5, @byte_dst:16
763 bne fail1
764 .endif
765
766 cmp_b_rspreinc_rdpreinc:
767 set_grs_a5a5 ; Fill all general regs with a fixed pattern
768 mov #byte_src-1, er1
769 mov #byte_dst-1, er2
770 set_ccr_zero
771 cmp.b @+er1, @+er2
772 ;;; .word 0x0175
773 ;;; .word 0x6c1c
774 ;;; .word 0x9220
775
776 test_neg_clear ; N=0, Z=0, V=1, C=0
777 test_zero_clear
778 test_ovf_set
779 test_carry_clear
780
781 test_gr_a5a5 0
782 test_h_gr32 byte_src er1
783 test_h_gr32 byte_dst er2
784 test_gr_a5a5 3
785 test_gr_a5a5 4
786 test_gr_a5a5 5
787 test_gr_a5a5 6
788 test_gr_a5a5 7
789 cmp.b #0x5a, @byte_src:16
790 bne fail1
791 cmp.b #0xa5, @byte_dst:16
792 bne fail1
793
794 cmp_b_rspredec_predec:
795 set_grs_a5a5 ; Fill all general regs with a fixed pattern
796 mov #byte_src+1, er1
797 mov #byte_dst+1, er2
798 set_ccr_zero
799 cmp.b @-er1, @-er2
800 ;;; .word 0x0177
801 ;;; .word 0x6c1c
802 ;;; .word 0xb220
803
804 test_neg_clear ; N=0, Z=0, V=1, C=0
805 test_zero_clear
806 test_ovf_set
807 test_carry_clear
808
809 test_gr_a5a5 0
810 test_h_gr32 byte_src er1
811 test_h_gr32 byte_dst er2
812 test_gr_a5a5 3
813 test_gr_a5a5 4
814 test_gr_a5a5 5
815 test_gr_a5a5 6
816 test_gr_a5a5 7
817 cmp.b #0x5a, @byte_src:16
818 bne fail1
819 cmp.b #0xa5, @byte_dst:16
820 bne fail1
821
822 cmp_b_disp2_disp2:
823 set_grs_a5a5 ; Fill all general regs with a fixed pattern
824 mov #byte_src-1, er1
825 mov #byte_dst-2, er2
826 set_ccr_zero
827 cmp.b @(1:2, er1), @(2:2, er2)
828 ;;; .word 0x0175
829 ;;; .word 0x681c
830 ;;; .word 0x2220
831
832 test_neg_clear ; N=0, Z=0, V=1, C=0
833 test_zero_clear
834 test_ovf_set
835 test_carry_clear
836
837 test_gr_a5a5 0
838 test_h_gr32 byte_src-1 er1
839 test_h_gr32 byte_dst-2 er2
840 test_gr_a5a5 3
841 test_gr_a5a5 4
842 test_gr_a5a5 5
843 test_gr_a5a5 6
844 test_gr_a5a5 7
845 cmp.b #0x5a, @byte_src:16
846 bne fail1
847 cmp.b #0xa5, @byte_dst:16
848 bne fail1
849
850 cmp_b_disp16_disp16:
851 set_grs_a5a5 ; Fill all general regs with a fixed pattern
852 mov #byte_src-3, er1
853 mov #byte_dst-4, er2
854 set_ccr_zero
855 cmp.b @(3:16, er1), @(4:16, er2)
856 ;;; .word 0x0174
857 ;;; .word 0x6e1c
858 ;;; .word 3
859 ;;; .word 0xc220
860 ;;; .word 4
861
862 test_neg_clear ; N=0, Z=0, V=1, C=0
863 test_zero_clear
864 test_ovf_set
865 test_carry_clear
866
867 test_gr_a5a5 0
868 test_h_gr32 byte_src-3 er1
869 test_h_gr32 byte_dst-4 er2
870 test_gr_a5a5 3
871 test_gr_a5a5 4
872 test_gr_a5a5 5
873 test_gr_a5a5 6
874 test_gr_a5a5 7
875 cmp.b #0x5a, @byte_src:16
876 bne fail1
877 cmp.b #0xa5, @byte_dst:16
878 bne fail1
879
880 cmp_b_disp32_disp32:
881 set_grs_a5a5 ; Fill all general regs with a fixed pattern
882 mov #byte_src+5, er1
883 mov #byte_dst+6, er2
884 set_ccr_zero
885 cmp.b @(-5:32, er1), @(-6:32, er2)
886 ;;; .word 0x7814
887 ;;; .word 0x6a2c
888 ;;; .long -5
889 ;;; .word 0xca20
890 ;;; .long -6
891
892 test_neg_clear ; N=0, Z=0, V=1, C=0
893 test_zero_clear
894 test_ovf_set
895 test_carry_clear
896
897 test_gr_a5a5 0
898 test_h_gr32 byte_src+5 er1
899 test_h_gr32 byte_dst+6 er2
900 test_gr_a5a5 3
901 test_gr_a5a5 4
902 test_gr_a5a5 5
903 test_gr_a5a5 6
904 test_gr_a5a5 7
905 cmp.b #0x5a, @byte_src:16
906 bne fail1
907 cmp.b #0xa5, @byte_dst:16
908 bne fail1
909
910 cmp_b_indexb16_indexb16:
911 set_grs_a5a5 ; Fill all general regs with a fixed pattern
912 mov #0xffffff01, er1
913 mov #0xffffff02, er2
914 set_ccr_zero
915 cmp.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r2.b)
916 ;;; .word 0x0175
917 ;;; .word 0x6e1c
918 ;;; .word byte_src-1
919 ;;; .word 0xd220
920 ;;; .word byte_dst-2
921
922 test_neg_clear ; N=0, Z=0, V=1, C=0
923 test_zero_clear
924 test_ovf_set
925 test_carry_clear
926
927 test_gr_a5a5 0
928 test_h_gr32 0xffffff01 er1
929 test_h_gr32 0xffffff02 er2
930 test_gr_a5a5 3
931 test_gr_a5a5 4
932 test_gr_a5a5 5
933 test_gr_a5a5 6
934 test_gr_a5a5 7
935 cmp.b #0x5a, @byte_src:16
936 bne fail1
937 cmp.b #0xa5, @byte_dst:16
938 bne fail1
939 .if 1 ; ambiguous
940 cmp_b_indexw16_indexw16:
941 set_grs_a5a5 ; Fill all general regs with a fixed pattern
942 mov #0xffff0003, er1
943 mov #0xffff0004, er2
944 set_ccr_zero
945 cmp.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r2.w)
946 ;;; .word 0x0176
947 ;;; .word 0x6e1c
948 ;;; .word byte_src-3
949 ;;; .word 0xe220
950 ;;; .word byte_dst-4
951
952 test_neg_clear ; N=0, Z=0, V=1, C=0
953 test_zero_clear
954 test_ovf_set
955 test_carry_clear
956
957 test_gr_a5a5 0
958 test_h_gr32 0xffff0003 er1
959 test_h_gr32 0xffff0004 er2
960 test_gr_a5a5 3
961 test_gr_a5a5 4
962 test_gr_a5a5 5
963 test_gr_a5a5 6
964 test_gr_a5a5 7
965 cmp.b #0x5a, @byte_src:16
966 bne fail1
967 cmp.b #0xa5, @byte_dst:16
968 bne fail1
969 .endif
970
971 cmp_b_indexl16_indexl16:
972 set_grs_a5a5 ; Fill all general regs with a fixed pattern
973 mov #0x00000005, er1
974 mov #0x00000006, er2
975 set_ccr_zero
976 cmp.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er2.l)
977 ;;; .word 0x0177
978 ;;; .word 0x6e1c
979 ;;; .word byte_src-5
980 ;;; .word 0xf220
981 ;;; .word byte_dst-6
982
983 test_neg_clear ; N=0, Z=0, V=1, C=0
984 test_zero_clear
985 test_ovf_set
986 test_carry_clear
987
988 test_gr_a5a5 0
989 test_h_gr32 0x00000005 er1
990 test_h_gr32 0x00000006 er2
991 test_gr_a5a5 3
992 test_gr_a5a5 4
993 test_gr_a5a5 5
994 test_gr_a5a5 6
995 test_gr_a5a5 7
996 cmp.b #0x5a, @byte_src:16
997 bne fail1
998 cmp.b #0xa5, @byte_dst:16
999 bne fail1
1000
1001 cmp_b_indexb32_indexb32:
1002 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1003 mov #0xffffff01, er1
1004 mov #0xffffff02, er2
1005 set_ccr_zero
1006 cmp.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r2.b)
1007 ;;; .word 0x7815
1008 ;;; .word 0x6a2c
1009 ;;; .long byte_src-1
1010 ;;; .word 0xda20
1011 ;;; .long byte_dst-2
1012
1013 test_neg_clear ; N=0, Z=0, V=1, C=0
1014 test_zero_clear
1015 test_ovf_set
1016 test_carry_clear
1017
1018 test_gr_a5a5 0
1019 test_h_gr32 0xffffff01 er1
1020 test_h_gr32 0xffffff02 er2
1021 test_gr_a5a5 3
1022 test_gr_a5a5 4
1023 test_gr_a5a5 5
1024 test_gr_a5a5 6
1025 test_gr_a5a5 7
1026 cmp.b #0x5a, @byte_src:16
1027 bne fail1
1028 cmp.b #0xa5, @byte_dst:16
1029 bne fail1
1030
1031 .if 1 ; ambiguous
1032 cmp_b_indexw32_indexw32:
1033 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1034 mov #0xffff0003, er1
1035 mov #0xffff0004, er2
1036 set_ccr_zero
1037 cmp.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r2.w)
1038 ;;; .word 0x7816
1039 ;;; .word 0x6a2c
1040 ;;; .long byte_src-3
1041 ;;; .word 0xea20
1042 ;;; .long byte_dst-4
1043
1044 test_neg_clear ; N=0, Z=0, V=1, C=0
1045 test_zero_clear
1046 test_ovf_set
1047 test_carry_clear
1048
1049 test_gr_a5a5 0
1050 test_h_gr32 0xffff0003 er1
1051 test_h_gr32 0xffff0004 er2
1052 test_gr_a5a5 3
1053 test_gr_a5a5 4
1054 test_gr_a5a5 5
1055 test_gr_a5a5 6
1056 test_gr_a5a5 7
1057 cmp.b #0x5a, @byte_src:16
1058 bne fail1
1059 cmp.b #0xa5, @byte_dst:16
1060 bne fail1
1061 .endif
1062
1063 cmp_b_indexl32_indexl32:
1064 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1065 mov #0x00000005, er1
1066 mov #0x00000006, er2
1067 set_ccr_zero
1068 cmp.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er2.l)
1069 ;;; .word 0x7817
1070 ;;; .word 0x6a2c
1071 ;;; .long byte_src-5
1072 ;;; .word 0xfa20
1073 ;;; .long byte_dst-6
1074
1075 test_neg_clear ; N=0, Z=0, V=1, C=0
1076 test_zero_clear
1077 test_ovf_set
1078 test_carry_clear
1079
1080 test_gr_a5a5 0
1081 test_h_gr32 0x00000005 er1
1082 test_h_gr32 0x00000006 er2
1083 test_gr_a5a5 3
1084 test_gr_a5a5 4
1085 test_gr_a5a5 5
1086 test_gr_a5a5 6
1087 test_gr_a5a5 7
1088 cmp.b #0x5a, @byte_src:16
1089 bne fail1
1090 cmp.b #0xa5, @byte_dst:16
1091 bne fail1
1092
1093 cmp_b_abs16_abs16:
1094 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1095 set_ccr_zero
1096 cmp.b @byte_src:16, @byte_dst:16
1097
1098 test_neg_clear ; N=0, Z=0, V=1, C=0
1099 test_zero_clear
1100 test_ovf_set
1101 test_carry_clear
1102
1103 test_grs_a5a5
1104 cmp.b #0x5a, @byte_src:16
1105 bne fail1
1106 cmp.b #0xa5, @byte_dst:16
1107 bne fail1
1108
1109 cmp_b_abs32_abs32:
1110 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1111 set_ccr_zero
1112 cmp.b @byte_src:32, @byte_dst:32
1113
1114 test_neg_clear ; N=0, Z=0, V=1, C=0
1115 test_zero_clear
1116 test_ovf_set
1117 test_carry_clear
1118
1119 test_grs_a5a5
1120 cmp.b #0x5a, @byte_src:16
1121 bne fail1
1122 cmp.b #0xa5, @byte_dst:16
1123 bne fail1
1124
1125 .endif
1126 pass
1127
1128 exit 0
1129
1130 fail1: fail