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[binutils-gdb.git] / sim / testsuite / h8300 / movb.s
1 # Hitachi H8 testcase 'mov.b'
2 # mach(): h8300h h8300s h8sx
3 # as(h8300h): --defsym sim_cpu=1
4 # as(h8300s): --defsym sim_cpu=2
5 # as(h8sx): --defsym sim_cpu=3
6 # ld(h8300h): -m h8300helf
7 # ld(h8300s): -m h8300self
8 # ld(h8sx): -m h8300sxelf
9
10 .include "testutils.inc"
11
12 start
13
14 .data
15 .align 4
16 byte_dst_dec:
17 .byte 0
18 byte_src:
19 .byte 0x77
20 byte_dst:
21 .byte 0
22
23 .text
24
25 ;;
26 ;; Move byte from immediate source
27 ;;
28
29 .if (sim_cpu == h8sx)
30 mov_b_imm8_to_reg8:
31 set_grs_a5a5 ; Fill all general regs with a fixed pattern
32 set_ccr_zero
33
34 ;; mov.b #xx:8, rd
35 mov.b #0x77:8, r0l ; Immediate 3-bit operand
36 ;;; .word 0xf877
37
38 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
39 test_neg_clear
40 test_zero_clear
41 test_ovf_clear
42 test_carry_clear
43
44 test_h_gr32 0xa5a5a577 er0
45
46 test_gr_a5a5 1 ; Make sure other general regs not disturbed
47 test_gr_a5a5 2
48 test_gr_a5a5 3
49 test_gr_a5a5 4
50 test_gr_a5a5 5
51 test_gr_a5a5 6
52 test_gr_a5a5 7
53 .endif
54
55 .if (sim_cpu == h8sx)
56 mov_b_imm4_to_abs16:
57 set_grs_a5a5 ; Fill all general regs with a fixed pattern
58 set_ccr_zero
59
60 ;; mov.b #xx:4, @aa:16
61 mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand
62 ;;; .word 0x6adf
63 ;;; .word @byte_dst
64
65 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
66 test_neg_clear
67 test_zero_clear
68 test_ovf_clear
69 test_carry_clear
70
71 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
72 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
73 test_gr_a5a5 2 ; to examine the destination memory).
74 test_gr_a5a5 3
75 test_gr_a5a5 4
76 test_gr_a5a5 5
77 test_gr_a5a5 6
78 test_gr_a5a5 7
79
80 ;; Now check the result of the move to memory.
81 cmp.b #0xf, @byte_dst
82 beq .Lnext21
83 fail
84 .Lnext21:
85 mov.b #0, @byte_dst ; zero it again for the next use.
86
87 mov_b_imm4_to_abs32:
88 set_grs_a5a5 ; Fill all general regs with a fixed pattern
89 set_ccr_zero
90
91 ;; mov.b #xx:4, @aa:32
92 mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand
93 ;;; .word 0x6aff
94 ;;; .long @byte_dst
95
96 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
97 test_neg_clear
98 test_zero_clear
99 test_ovf_clear
100 test_carry_clear
101
102 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
103 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
104 test_gr_a5a5 2 ; to examine the destination memory).
105 test_gr_a5a5 3
106 test_gr_a5a5 4
107 test_gr_a5a5 5
108 test_gr_a5a5 6
109 test_gr_a5a5 7
110
111 ;; Now check the result of the move to memory.
112 cmp.b #0xf, @byte_dst
113 beq .Lnext22
114 fail
115 .Lnext22:
116 mov.b #0, @byte_dst ; zero it again for the next use.
117
118 mov_b_imm8_to_indirect:
119 set_grs_a5a5 ; Fill all general regs with a fixed pattern
120 set_ccr_zero
121
122 ;; mov.b #xx:8, @erd
123 mov.l #byte_dst, er1
124 mov.b #0xa5:8, @er1 ; Register indirect operand
125 ;;; .word 0x017d
126 ;;; .word 0x01a5
127
128 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
129 test_neg_set
130 test_zero_clear
131 test_ovf_clear
132 test_carry_clear
133
134 test_gr_a5a5 0 ; Make sure other general regs not disturbed
135 test_h_gr32 byte_dst, er1
136 test_gr_a5a5 2
137 test_gr_a5a5 3
138 test_gr_a5a5 4
139 test_gr_a5a5 5
140 test_gr_a5a5 6
141 test_gr_a5a5 7
142
143 ;; Now check the result of the move to memory.
144 cmp.b #0xa5, @byte_dst
145 beq .Lnext1
146 fail
147 .Lnext1:
148 mov.b #0, @byte_dst ; zero it again for the next use.
149
150 mov_b_imm8_to_postinc: ; post-increment from imm8 to mem
151 set_grs_a5a5 ; Fill all general regs with a fixed pattern
152 set_ccr_zero
153
154 ;; mov.b #xx:8, @erd+
155 mov.l #byte_dst, er1
156 mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands.
157 ;;; .word 0x017d
158 ;;; .word 0x81a5
159
160 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
161 test_neg_set
162 test_zero_clear
163 test_ovf_clear
164 test_carry_clear
165
166 test_gr_a5a5 0 ; Make sure other general regs not disturbed
167 test_h_gr32 byte_dst+1, er1
168 test_gr_a5a5 2
169 test_gr_a5a5 3
170 test_gr_a5a5 4
171 test_gr_a5a5 5
172 test_gr_a5a5 6
173 test_gr_a5a5 7
174
175 ;; Now check the result of the move to memory.
176 cmp.b #0xa5, @byte_dst
177 beq .Lnext2
178 fail
179 .Lnext2:
180 mov.b #0, @byte_dst ; zero it again for the next use.
181
182 mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem
183 set_grs_a5a5 ; Fill all general regs with a fixed pattern
184 set_ccr_zero
185
186 ;; mov.b #xx:8, @erd-
187 mov.l #byte_dst, er1
188 mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands.
189 ;;; .word 0x017d
190 ;;; .word 0xa1a5
191
192 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
193 test_neg_set
194 test_zero_clear
195 test_ovf_clear
196 test_carry_clear
197
198 test_gr_a5a5 0 ; Make sure other general regs not disturbed
199 test_h_gr32 byte_dst-1, er1
200 test_gr_a5a5 2
201 test_gr_a5a5 3
202 test_gr_a5a5 4
203 test_gr_a5a5 5
204 test_gr_a5a5 6
205 test_gr_a5a5 7
206
207 ;; Now check the result of the move to memory.
208 cmp.b #0xa5, @byte_dst
209 beq .Lnext3
210 fail
211 .Lnext3:
212 mov.b #0, @byte_dst ; zero it again for the next use.
213
214 mov_b_imm8_to_preinc: ; pre-increment from register to mem
215 set_grs_a5a5 ; Fill all general regs with a fixed pattern
216 set_ccr_zero
217
218 ;; mov.b #xx:8, @+erd
219 mov.l #byte_dst-1, er1
220 mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands
221 ;;; .word 0x017d
222 ;;; .word 0x91a5
223
224 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
225 test_neg_set
226 test_zero_clear
227 test_ovf_clear
228 test_carry_clear
229
230 test_gr_a5a5 0 ; Make sure other general regs not disturbed
231 test_h_gr32 byte_dst, er1
232 test_gr_a5a5 2
233 test_gr_a5a5 3
234 test_gr_a5a5 4
235 test_gr_a5a5 5
236 test_gr_a5a5 6
237 test_gr_a5a5 7
238
239 ;; Now check the result of the move to memory.
240 cmp.b #0xa5, @byte_dst
241 beq .Lnext4
242 fail
243 .Lnext4:
244 mov.b #0, @byte_dst ; zero it again for the next use.
245
246 mov_b_imm8_to_predec: ; pre-decrement from register to mem
247 set_grs_a5a5 ; Fill all general regs with a fixed pattern
248 set_ccr_zero
249
250 ;; mov.b #xx:8, @-erd
251 mov.l #byte_dst+1, er1
252 mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands
253 ;;; .word 0x017d
254 ;;; .word 0xb1a5
255
256 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
257 test_neg_set
258 test_zero_clear
259 test_ovf_clear
260 test_carry_clear
261
262 test_gr_a5a5 0 ; Make sure other general regs not disturbed
263 test_h_gr32 byte_dst, er1
264 test_gr_a5a5 2
265 test_gr_a5a5 3
266 test_gr_a5a5 4
267 test_gr_a5a5 5
268 test_gr_a5a5 6
269 test_gr_a5a5 7
270
271 ;; Now check the result of the move to memory.
272 cmp.b #0xa5, @byte_dst
273 beq .Lnext5
274 fail
275 .Lnext5:
276 mov.b #0, @byte_dst ; zero it again for the next use.
277
278 mov_b_imm8_to_disp2:
279 set_grs_a5a5 ; Fill all general regs with a fixed pattern
280 set_ccr_zero
281
282 ;; mov.b #xx:8, @(dd:2, erd)
283 mov.l #byte_dst-3, er1
284 mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand
285 ;;; .word 0x017d
286 ;;; .word 0x31a5
287
288 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
289 test_neg_set
290 test_zero_clear
291 test_ovf_clear
292 test_carry_clear
293
294 test_gr_a5a5 0 ; Make sure other general regs not disturbed
295 test_h_gr32 byte_dst-3, er1
296 test_gr_a5a5 2
297 test_gr_a5a5 3
298 test_gr_a5a5 4
299 test_gr_a5a5 5
300 test_gr_a5a5 6
301 test_gr_a5a5 7
302
303 ;; Now check the result of the move to memory.
304 cmp.b #0xa5, @byte_dst
305 beq .Lnext6
306 fail
307 .Lnext6:
308 mov.b #0, @byte_dst ; zero it again for the next use.
309
310 mov_b_imm8_to_disp16:
311 set_grs_a5a5 ; Fill all general regs with a fixed pattern
312 set_ccr_zero
313
314 ;; mov.b #xx:8, @(dd:16, erd)
315 mov.l #byte_dst-4, er1
316 mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand
317 ;;; .word 0x017d
318 ;;; .word 0x6f90
319 ;;; .word 0x0004
320
321 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
322 test_neg_set
323 test_zero_clear
324 test_ovf_clear
325 test_carry_clear
326
327 test_gr_a5a5 0 ; Make sure other general regs not disturbed
328 test_h_gr32 byte_dst-4, er1
329 test_gr_a5a5 2
330 test_gr_a5a5 3
331 test_gr_a5a5 4
332 test_gr_a5a5 5
333 test_gr_a5a5 6
334 test_gr_a5a5 7
335
336 ;; Now check the result of the move to memory.
337 cmp.b #0xa5, @byte_dst
338 beq .Lnext7
339 fail
340 .Lnext7:
341 mov.b #0, @byte_dst ; zero it again for the next use.
342
343 mov_b_imm8_to_disp32:
344 set_grs_a5a5 ; Fill all general regs with a fixed pattern
345 set_ccr_zero
346
347 ;; mov.b #xx:8, @(dd:32, erd)
348 mov.l #byte_dst-8, er1
349 mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand
350 ;;; .word 0x017d
351 ;;; .word 0xc9a5
352 ;;; .long 8
353
354 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
355 test_neg_set
356 test_zero_clear
357 test_ovf_clear
358 test_carry_clear
359
360 test_gr_a5a5 0 ; Make sure other general regs not disturbed
361 test_h_gr32 byte_dst-8, er1
362 test_gr_a5a5 2
363 test_gr_a5a5 3
364 test_gr_a5a5 4
365 test_gr_a5a5 5
366 test_gr_a5a5 6
367 test_gr_a5a5 7
368
369 ;; Now check the result of the move to memory.
370 cmp.b #0xa5, @byte_dst
371 beq .Lnext8
372 fail
373 .Lnext8:
374 mov.b #0, @byte_dst ; zero it again for the next use.
375
376 mov_b_imm8_to_indexb16:
377 set_grs_a5a5 ; Fill all general regs with a fixed pattern
378 mov.l #0xffffff01, er1
379 set_ccr_zero
380 ;; mov.b #xx:8, @(dd:16, rd.b)
381 mov.b #0xa5:8, @(byte_dst-1:16, r1.b) ; byte indexed operand
382
383 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
384 test_neg_set
385 test_zero_clear
386 test_ovf_clear
387 test_carry_clear
388
389 test_gr_a5a5 0 ; Make sure other general regs not disturbed
390 test_h_gr32 0xffffff01, er1
391 test_gr_a5a5 2
392 test_gr_a5a5 3
393 test_gr_a5a5 4
394 test_gr_a5a5 5
395 test_gr_a5a5 6
396 test_gr_a5a5 7
397
398 ;; Now check the result of the move to memory.
399 cmp.b #0xa5, @byte_dst
400 bne fail1
401 mov.b #0, @byte_dst ; zero it again for the next use.
402
403 mov_b_imm8_to_indexw16:
404 set_grs_a5a5 ; Fill all general regs with a fixed pattern
405 mov.l #0xffff0002, er1
406 set_ccr_zero
407 ;; mov.b #xx:8, @(dd:16, rd.w)
408 mov.b #0xa5:8, @(byte_dst-2:16, r1.w) ; byte indexed operand
409
410 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
411 test_neg_set
412 test_zero_clear
413 test_ovf_clear
414 test_carry_clear
415
416 test_gr_a5a5 0 ; Make sure other general regs not disturbed
417 test_h_gr32 0xffff0002, er1
418 test_gr_a5a5 2
419 test_gr_a5a5 3
420 test_gr_a5a5 4
421 test_gr_a5a5 5
422 test_gr_a5a5 6
423 test_gr_a5a5 7
424
425 ;; Now check the result of the move to memory.
426 cmp.b #0xa5, @byte_dst
427 bne fail1
428 mov.b #0, @byte_dst ; zero it again for the next use.
429
430 mov_b_imm8_to_indexl16:
431 set_grs_a5a5 ; Fill all general regs with a fixed pattern
432 mov.l #0x00000003, er1
433 set_ccr_zero
434 ;; mov.b #xx:8, @(dd:16, erd.l)
435 mov.b #0xa5:8, @(byte_dst-3:16, er1.l) ; byte indexed operand
436
437 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
438 test_neg_set
439 test_zero_clear
440 test_ovf_clear
441 test_carry_clear
442
443 test_gr_a5a5 0 ; Make sure other general regs not disturbed
444 test_h_gr32 0x00000003, er1
445 test_gr_a5a5 2
446 test_gr_a5a5 3
447 test_gr_a5a5 4
448 test_gr_a5a5 5
449 test_gr_a5a5 6
450 test_gr_a5a5 7
451
452 ;; Now check the result of the move to memory.
453 cmp.b #0xa5, @byte_dst
454 bne fail1
455 mov.b #0, @byte_dst ; zero it again for the next use.
456
457 mov_b_imm8_to_indexb32:
458 set_grs_a5a5 ; Fill all general regs with a fixed pattern
459 mov.l #0xffffff04, er1
460 set_ccr_zero
461 ;; mov.b #xx:8, @(dd:32, rd.b)
462 mov.b #0xa5:8, @(byte_dst-4:32, r1.b) ; byte indexed operand
463
464 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
465 test_neg_set
466 test_zero_clear
467 test_ovf_clear
468 test_carry_clear
469
470 test_gr_a5a5 0 ; Make sure other general regs not disturbed
471 test_h_gr32 0xffffff04 er1
472 test_gr_a5a5 2
473 test_gr_a5a5 3
474 test_gr_a5a5 4
475 test_gr_a5a5 5
476 test_gr_a5a5 6
477 test_gr_a5a5 7
478
479 ;; Now check the result of the move to memory.
480 cmp.b #0xa5, @byte_dst
481 bne fail1
482 mov.b #0, @byte_dst ; zero it again for the next use.
483
484 mov_b_imm8_to_indexw32:
485 set_grs_a5a5 ; Fill all general regs with a fixed pattern
486 mov.l #0xffff0005, er1
487 set_ccr_zero
488 ;; mov.b #xx:8, @(dd:32, rd.w)
489 mov.b #0xa5:8, @(byte_dst-5:32, r1.w) ; byte indexed operand
490
491 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
492 test_neg_set
493 test_zero_clear
494 test_ovf_clear
495 test_carry_clear
496
497 test_gr_a5a5 0 ; Make sure other general regs not disturbed
498 test_h_gr32 0xffff0005 er1
499 test_gr_a5a5 2
500 test_gr_a5a5 3
501 test_gr_a5a5 4
502 test_gr_a5a5 5
503 test_gr_a5a5 6
504 test_gr_a5a5 7
505
506 ;; Now check the result of the move to memory.
507 cmp.b #0xa5, @byte_dst
508 bne fail1
509 mov.b #0, @byte_dst ; zero it again for the next use.
510
511 mov_b_imm8_to_indexl32:
512 set_grs_a5a5 ; Fill all general regs with a fixed pattern
513 mov.l #0x00000006, er1
514 set_ccr_zero
515 ;; mov.b #xx:8, @(dd:32, erd.l)
516 mov.b #0xa5:8, @(byte_dst-6:32, er1.l) ; byte indexed operand
517
518 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
519 test_neg_set
520 test_zero_clear
521 test_ovf_clear
522 test_carry_clear
523
524 test_gr_a5a5 0 ; Make sure other general regs not disturbed
525 test_h_gr32 0x00000006 er1
526 test_gr_a5a5 2
527 test_gr_a5a5 3
528 test_gr_a5a5 4
529 test_gr_a5a5 5
530 test_gr_a5a5 6
531 test_gr_a5a5 7
532
533 ;; Now check the result of the move to memory.
534 cmp.b #0xa5, @byte_dst
535 bne fail1
536 mov.b #0, @byte_dst ; zero it again for the next use.
537
538 mov_b_imm8_to_abs16:
539 set_grs_a5a5 ; Fill all general regs with a fixed pattern
540 set_ccr_zero
541
542 ;; mov.b #xx:8, @aa:16
543 mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand
544 ;;; .word 0x017d
545 ;;; .word 0x40a5
546 ;;; .word @byte_dst
547
548 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
549 test_neg_set
550 test_zero_clear
551 test_ovf_clear
552 test_carry_clear
553
554 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
555 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
556 test_gr_a5a5 2 ; to examine the destination memory).
557 test_gr_a5a5 3
558 test_gr_a5a5 4
559 test_gr_a5a5 5
560 test_gr_a5a5 6
561 test_gr_a5a5 7
562
563 ;; Now check the result of the move to memory.
564 cmp.b #0xa5, @byte_dst
565 beq .Lnext9
566 fail
567 .Lnext9:
568 mov.b #0, @byte_dst ; zero it again for the next use.
569
570 mov_b_imm8_to_abs32:
571 set_grs_a5a5 ; Fill all general regs with a fixed pattern
572 set_ccr_zero
573
574 ;; mov.b #xx:8, @aa:32
575 mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand
576 ;;; .word 0x017d
577 ;;; .word 0x48a5
578 ;;; .long @byte_dst
579
580 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
581 test_neg_set
582 test_zero_clear
583 test_ovf_clear
584 test_carry_clear
585
586 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
587 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
588 test_gr_a5a5 2 ; to examine the destination memory).
589 test_gr_a5a5 3
590 test_gr_a5a5 4
591 test_gr_a5a5 5
592 test_gr_a5a5 6
593 test_gr_a5a5 7
594
595 ;; Now check the result of the move to memory.
596 cmp.b #0xa5, @byte_dst
597 beq .Lnext10
598 fail
599 .Lnext10:
600 mov.b #0, @byte_dst ; zero it again for the next use.
601
602 .endif
603
604 ;;
605 ;; Move byte from register source
606 ;;
607
608 mov_b_reg8_to_reg8:
609 set_grs_a5a5 ; Fill all general regs with a fixed pattern
610 set_ccr_zero
611
612 ;; mov.b ers, erd
613 mov.b #0x12, r1l
614 mov.b r1l, r0l ; Register 8-bit operand
615 ;;; .word 0x0c98
616
617 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
618 test_neg_clear
619 test_zero_clear
620 test_ovf_clear
621 test_carry_clear
622 test_h_gr16 0xa512 r0
623 test_h_gr16 0xa512 r1 ; mov src unchanged
624 .if (sim_cpu)
625 test_h_gr32 0xa5a5a512 er0
626 test_h_gr32 0xa5a5a512 er1 ; mov src unchanged
627 .endif
628 test_gr_a5a5 2 ; Make sure other general regs not disturbed
629 test_gr_a5a5 3
630 test_gr_a5a5 4
631 test_gr_a5a5 5
632 test_gr_a5a5 6
633 test_gr_a5a5 7
634
635
636 mov_b_reg8_to_indirect:
637 set_grs_a5a5 ; Fill all general regs with a fixed pattern
638 set_ccr_zero
639
640 ;; mov.b ers, @erd
641 mov.l #byte_dst, er1
642 mov.b r0l, @er1 ; Register indirect operand
643 ;;; .word 0x6898
644
645 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
646 test_neg_set
647 test_zero_clear
648 test_ovf_clear
649 test_carry_clear
650
651 test_gr_a5a5 0 ; Make sure other general regs not disturbed
652 test_h_gr32 byte_dst, er1
653 test_gr_a5a5 2
654 test_gr_a5a5 3
655 test_gr_a5a5 4
656 test_gr_a5a5 5
657 test_gr_a5a5 6
658 test_gr_a5a5 7
659
660 ;; Now check the result of the move to memory.
661 mov.b @byte_dst, r0l
662 cmp.b r2l, r0l
663 beq .Lnext44
664 fail
665 .Lnext44:
666 mov.b #0, r0l
667 mov.b r0l, @byte_dst ; zero it again for the next use.
668
669 .if (sim_cpu == h8sx)
670 mov_b_reg8_to_postinc: ; post-increment from register to mem
671 set_grs_a5a5 ; Fill all general regs with a fixed pattern
672 set_ccr_zero
673
674 ;; mov.b ers, @erd+
675 mov.l #byte_dst, er1
676 mov.b r0l, @er1+ ; Register post-incr operand
677 ;;; .word 0x0173
678 ;;; .word 0x6c98
679
680 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
681 test_neg_set
682 test_zero_clear
683 test_ovf_clear
684 test_carry_clear
685
686 test_gr_a5a5 0 ; Make sure other general regs not disturbed
687 test_h_gr32 byte_dst+1, er1
688 test_gr_a5a5 2
689 test_gr_a5a5 3
690 test_gr_a5a5 4
691 test_gr_a5a5 5
692 test_gr_a5a5 6
693 test_gr_a5a5 7
694
695 ;; Now check the result of the move to memory.
696 cmp.b r2l, @byte_dst
697 beq .Lnext49
698 fail
699 .Lnext49:
700 ;; special case same register
701 mov.l #byte_dst, er0
702 mov.b r0l, r1l
703 inc.b r1l
704 mov.b r0l, @er0+
705 mov.b @byte_dst, r0l
706 cmp.b r0l, r1l
707 beq .Lnext53
708 fail
709 .Lnext53:
710 mov.b #0, @byte_dst ; zero it again for the next use.
711
712 mov_b_reg8_to_postdec: ; post-decrement from register to mem
713 set_grs_a5a5 ; Fill all general regs with a fixed pattern
714 set_ccr_zero
715
716 ;; mov.b ers, @erd-
717 mov.l #byte_dst, er1
718 mov.b r0l, @er1- ; Register post-decr operand
719 ;;; .word 0x0171
720 ;;; .word 0x6c98
721
722 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
723 test_neg_set
724 test_zero_clear
725 test_ovf_clear
726 test_carry_clear
727
728 test_gr_a5a5 0 ; Make sure other general regs not disturbed
729 test_h_gr32 byte_dst-1, er1
730 test_gr_a5a5 2
731 test_gr_a5a5 3
732 test_gr_a5a5 4
733 test_gr_a5a5 5
734 test_gr_a5a5 6
735 test_gr_a5a5 7
736
737 ;; Now check the result of the move to memory.
738 cmp.b r2l, @byte_dst
739 beq .Lnext50
740 fail
741 .Lnext50:
742 ;; special case same register
743 mov.l #byte_dst, er0
744 mov.b r0l, r1l
745 dec.b r1l
746 mov.b r0l, @er0-
747 mov.b @byte_dst, r0l
748 cmp.b r0l, r1l
749 beq .Lnext54
750 fail
751 .Lnext54:
752 mov.b #0, @byte_dst ; zero it again for the next use.
753
754 mov_b_reg8_to_preinc: ; pre-increment from register to mem
755 set_grs_a5a5 ; Fill all general regs with a fixed pattern
756 set_ccr_zero
757
758 ;; mov.b ers, @+erd
759 mov.l #byte_dst-1, er1
760 mov.b r0l, @+er1 ; Register pre-incr operand
761 ;;; .word 0x0172
762 ;;; .word 0x6c98
763
764 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
765 test_neg_set
766 test_zero_clear
767 test_ovf_clear
768 test_carry_clear
769
770 test_gr_a5a5 0 ; Make sure other general regs not disturbed
771 test_h_gr32 byte_dst, er1
772 test_gr_a5a5 2
773 test_gr_a5a5 3
774 test_gr_a5a5 4
775 test_gr_a5a5 5
776 test_gr_a5a5 6
777 test_gr_a5a5 7
778
779 ;; Now check the result of the move to memory.
780 cmp.b r2l, @byte_dst
781 beq .Lnext51
782 fail
783 .Lnext51:
784 ;; special case same register
785 mov.l #byte_dst-1, er0
786 mov.b r0l, r1l
787 inc.b r1l
788 mov.b r0l, @+er0
789 mov.b @byte_dst, r0l
790 cmp.b r0l, r1l
791 beq .Lnext55
792 fail
793 .Lnext55:
794 mov.b #0, @byte_dst ; zero it again for the next use.
795 .endif
796
797 mov_b_reg8_to_predec: ; pre-decrement from register to mem
798 set_grs_a5a5 ; Fill all general regs with a fixed pattern
799 set_ccr_zero
800
801 ;; mov.b ers, @-erd
802 mov.l #byte_dst+1, er1
803 mov.b r0l, @-er1 ; Register pre-decr operand
804 ;;; .word 0x6c98
805
806 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
807 test_neg_set
808 test_zero_clear
809 test_ovf_clear
810 test_carry_clear
811
812 test_gr_a5a5 0 ; Make sure other general regs not disturbed
813 test_h_gr32 byte_dst, er1
814 test_gr_a5a5 2
815 test_gr_a5a5 3
816 test_gr_a5a5 4
817 test_gr_a5a5 5
818 test_gr_a5a5 6
819 test_gr_a5a5 7
820
821 ;; Now check the result of the move to memory.
822 mov.b @byte_dst, r0l
823 cmp.b r2l, r0l
824 beq .Lnext48
825 fail
826 .Lnext48:
827 ;; Special case in same register
828 ;; CCR confirmation omitted
829 mov.l #byte_dst+1, er1
830 mov.l er1, er0
831 dec.b r1l
832 mov.b r0l, @-er0
833 mov.b @byte_dst, r0l
834 cmp.b r1l, r0l
835 beq .Lnext47
836 fail
837 .Lnext47:
838 mov.b #0, r0l
839 mov.b r0l, @byte_dst ; zero it again for the next use.
840
841 .if (sim_cpu == h8sx)
842 mov_b_reg8_to_disp2:
843 set_grs_a5a5 ; Fill all general regs with a fixed pattern
844 set_ccr_zero
845
846 ;; mov.b ers, @(dd:2, erd)
847 mov.l #byte_dst-3, er1
848 mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand
849 ;;; .word 0x0173
850 ;;; .word 0x6898
851
852 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
853 test_neg_set
854 test_zero_clear
855 test_ovf_clear
856 test_carry_clear
857
858 test_gr_a5a5 0 ; Make sure other general regs not disturbed
859 test_h_gr32 byte_dst-3, er1
860 test_gr_a5a5 2
861 test_gr_a5a5 3
862 test_gr_a5a5 4
863 test_gr_a5a5 5
864 test_gr_a5a5 6
865 test_gr_a5a5 7
866
867 ;; Now check the result of the move to memory.
868 cmp.b r2l, @byte_dst
869 beq .Lnext52
870 fail
871 .Lnext52:
872 mov.b #0, @byte_dst ; zero it again for the next use.
873 .endif
874
875 mov_b_reg8_to_disp16:
876 set_grs_a5a5 ; Fill all general regs with a fixed pattern
877 set_ccr_zero
878
879 ;; mov.b ers, @(dd:16, erd)
880 mov.l #byte_dst-4, er1
881 mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand
882 ;;; .word 0x6e98
883 ;;; .word 0x0004
884
885 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
886 test_neg_set
887 test_zero_clear
888 test_ovf_clear
889 test_carry_clear
890
891 test_h_gr32 byte_dst-4, er1
892 test_gr_a5a5 0 ; Make sure other general regs not disturbed
893 test_gr_a5a5 2
894 test_gr_a5a5 3
895 test_gr_a5a5 4
896 test_gr_a5a5 5
897 test_gr_a5a5 6
898 test_gr_a5a5 7
899
900 ;; Now check the result of the move to memory.
901 mov.b @byte_dst, r0l
902 cmp.b r2l, r0l
903 beq .Lnext45
904 fail
905 .Lnext45:
906 mov.b #0, r0l
907 mov.b r0l, @byte_dst ; zero it again for the next use.
908
909 mov_b_reg8_to_disp32:
910 set_grs_a5a5 ; Fill all general regs with a fixed pattern
911 set_ccr_zero
912
913 ;; mov.b ers, @(dd:32, erd)
914 mov.l #byte_dst-8, er1
915 mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand
916 ;;; .word 0x7810
917 ;;; .word 0x6aa8
918 ;;; .long 8
919
920 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
921 test_neg_set
922 test_zero_clear
923 test_ovf_clear
924 test_carry_clear
925
926 test_h_gr32 byte_dst-8, er1
927 test_gr_a5a5 0 ; Make sure other general regs not disturbed
928 test_gr_a5a5 2
929 test_gr_a5a5 3
930 test_gr_a5a5 4
931 test_gr_a5a5 5
932 test_gr_a5a5 6
933 test_gr_a5a5 7
934
935 ;; Now check the result of the move to memory.
936 mov.b @byte_dst, r0l
937 cmp.b r2l, r0l
938 beq .Lnext46
939 fail
940 .Lnext46:
941 mov.b #0, r0l
942 mov.b r0l, @byte_dst ; zero it again for the next use.
943
944 .if (sim_cpu == h8sx)
945 mov_b_reg8_to_indexb16:
946 set_grs_a5a5 ; Fill all general regs with a fixed pattern
947 mov.l #0xffffff01, er1
948 set_ccr_zero
949 ;; mov.b ers, @(dd:16, rd.b)
950 mov.b r0l, @(byte_dst-1:16, r1.b) ; byte indexed operand
951
952 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
953 test_neg_set
954 test_zero_clear
955 test_ovf_clear
956 test_carry_clear
957
958 test_h_gr32 0xffffff01 er1
959 test_gr_a5a5 0 ; Make sure other general regs not disturbed
960 test_gr_a5a5 2
961 test_gr_a5a5 3
962 test_gr_a5a5 4
963 test_gr_a5a5 5
964 test_gr_a5a5 6
965 test_gr_a5a5 7
966
967 ;; Now check the result of the move to memory.
968 cmp.b @byte_dst, r0l
969 bne fail1
970 mov.b #0, @byte_dst ; zero it again for the next use.
971
972 mov_b_reg8_to_indexw16:
973 set_grs_a5a5 ; Fill all general regs with a fixed pattern
974 mov.l #0xffff0002, er1
975 set_ccr_zero
976 ;; mov.b ers, @(dd:16, rd.w)
977 mov.b r0l, @(byte_dst-2:16, r1.w) ; byte indexed operand
978
979 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
980 test_neg_set
981 test_zero_clear
982 test_ovf_clear
983 test_carry_clear
984
985 test_h_gr32 0xffff0002 er1
986 test_gr_a5a5 0 ; Make sure other general regs not disturbed
987 test_gr_a5a5 2
988 test_gr_a5a5 3
989 test_gr_a5a5 4
990 test_gr_a5a5 5
991 test_gr_a5a5 6
992 test_gr_a5a5 7
993
994 ;; Now check the result of the move to memory.
995 cmp.b @byte_dst, r0l
996 bne fail1
997 mov.b #0, @byte_dst ; zero it again for the next use.
998
999 mov_b_reg8_to_indexl16:
1000 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1001 mov.l #0x00000003, er1
1002 set_ccr_zero
1003 ;; mov.b ers, @(dd:16, erd.l)
1004 mov.b r0l, @(byte_dst-3:16, er1.l) ; byte indexed operand
1005
1006 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1007 test_neg_set
1008 test_zero_clear
1009 test_ovf_clear
1010 test_carry_clear
1011
1012 test_h_gr32 0x00000003 er1
1013 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1014 test_gr_a5a5 2
1015 test_gr_a5a5 3
1016 test_gr_a5a5 4
1017 test_gr_a5a5 5
1018 test_gr_a5a5 6
1019 test_gr_a5a5 7
1020
1021 ;; Now check the result of the move to memory.
1022 cmp.b @byte_dst, r0l
1023 bne fail1
1024 mov.b #0, @byte_dst ; zero it again for the next use.
1025
1026 mov_b_reg8_to_indexb32:
1027 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1028 mov.l #0xffffff04 er1
1029 set_ccr_zero
1030 ;; mov.b ers, @(dd:32, rd.b)
1031 mov.b r0l, @(byte_dst-4:32, r1.b) ; byte indexed operand
1032
1033 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1034 test_neg_set
1035 test_zero_clear
1036 test_ovf_clear
1037 test_carry_clear
1038
1039 test_h_gr32 0xffffff04, er1
1040 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1041 test_gr_a5a5 2
1042 test_gr_a5a5 3
1043 test_gr_a5a5 4
1044 test_gr_a5a5 5
1045 test_gr_a5a5 6
1046 test_gr_a5a5 7
1047
1048 ;; Now check the result of the move to memory.
1049 cmp.b @byte_dst, r0l
1050 bne fail1
1051 mov.b #0, @byte_dst ; zero it again for the next use.
1052
1053 mov_b_reg8_to_indexw32:
1054 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1055 mov.l #0xffff0005 er1
1056 set_ccr_zero
1057 ;; mov.b ers, @(dd:32, rd.w)
1058 mov.b r0l, @(byte_dst-5:32, r1.w) ; byte indexed operand
1059
1060 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1061 test_neg_set
1062 test_zero_clear
1063 test_ovf_clear
1064 test_carry_clear
1065
1066 test_h_gr32 0xffff0005, er1
1067 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1068 test_gr_a5a5 2
1069 test_gr_a5a5 3
1070 test_gr_a5a5 4
1071 test_gr_a5a5 5
1072 test_gr_a5a5 6
1073 test_gr_a5a5 7
1074
1075 ;; Now check the result of the move to memory.
1076 cmp.b @byte_dst, r0l
1077 bne fail1
1078 mov.b #0, @byte_dst ; zero it again for the next use.
1079
1080 mov_b_reg8_to_indexl32:
1081 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1082 mov.l #0x00000006 er1
1083 set_ccr_zero
1084 ;; mov.b ers, @(dd:32, erd.l)
1085 mov.b r0l, @(byte_dst-6:32, er1.l) ; byte indexed operand
1086
1087 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1088 test_neg_set
1089 test_zero_clear
1090 test_ovf_clear
1091 test_carry_clear
1092
1093 test_h_gr32 0x00000006, er1
1094 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1095 test_gr_a5a5 2
1096 test_gr_a5a5 3
1097 test_gr_a5a5 4
1098 test_gr_a5a5 5
1099 test_gr_a5a5 6
1100 test_gr_a5a5 7
1101
1102 ;; Now check the result of the move to memory.
1103 cmp.b @byte_dst, r0l
1104 bne fail1
1105 mov.b #0, @byte_dst ; zero it again for the next use.
1106 .endif
1107
1108 .if (sim_cpu == h8sx)
1109 mov_b_reg8_to_abs8:
1110 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1111
1112 mov.l #byte_dst-20, er0
1113 ldc er0, sbr
1114 set_ccr_zero
1115 ;; mov.b ers, @aa:8
1116 mov.b r1l, @20:8 ; 8-bit address-direct (sbr-relative) operand
1117
1118 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1119 test_neg_set
1120 test_zero_clear
1121 test_ovf_clear
1122 test_carry_clear
1123
1124 test_h_gr32 byte_dst-20, er0
1125 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1126 test_gr_a5a5 2
1127 test_gr_a5a5 3
1128 test_gr_a5a5 4
1129 test_gr_a5a5 5
1130 test_gr_a5a5 6
1131 test_gr_a5a5 7
1132
1133 ;; Now check the result of the move to memory.
1134 cmp.b @byte_dst, r1l
1135 bne fail1
1136 mov.b #0, @byte_dst ; zero it again for the next use.
1137 .endif
1138
1139 mov_b_reg8_to_abs16:
1140 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1141 set_ccr_zero
1142
1143 ;; mov.b ers, @aa:16
1144 mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand
1145 ;;; .word 0x6a88
1146 ;;; .word @byte_dst
1147
1148 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1149 test_neg_set
1150 test_zero_clear
1151 test_ovf_clear
1152 test_carry_clear
1153
1154 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
1155 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
1156 test_gr_a5a5 2 ; to examine the destination memory).
1157 test_gr_a5a5 3
1158 test_gr_a5a5 4
1159 test_gr_a5a5 5
1160 test_gr_a5a5 6
1161 test_gr_a5a5 7
1162
1163 ;; Now check the result of the move to memory.
1164 mov.b @byte_dst, r0l
1165 cmp.b r0l, r1l
1166 beq .Lnext41
1167 fail
1168 .Lnext41:
1169 mov.b #0, r0l
1170 mov.b r0l, @byte_dst ; zero it again for the next use.
1171
1172 mov_b_reg8_to_abs32:
1173 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1174 set_ccr_zero
1175
1176 ;; mov.b ers, @aa:32
1177 mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand
1178 ;;; .word 0x6aa8
1179 ;;; .long @byte_dst
1180
1181 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1182 test_neg_set
1183 test_zero_clear
1184 test_ovf_clear
1185 test_carry_clear
1186
1187 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
1188 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
1189 test_gr_a5a5 2 ; to examine the destination memory).
1190 test_gr_a5a5 3
1191 test_gr_a5a5 4
1192 test_gr_a5a5 5
1193 test_gr_a5a5 6
1194 test_gr_a5a5 7
1195
1196 ;; Now check the result of the move to memory.
1197 mov.b @byte_dst, r0l
1198 cmp.b r0l, r1l
1199 beq .Lnext42
1200 fail
1201 .Lnext42:
1202 mov.b #0, r0l
1203 mov.b r0l, @byte_dst ; zero it again for the next use.
1204
1205 ;;
1206 ;; Move byte to register destination.
1207 ;;
1208
1209 mov_b_indirect_to_reg8:
1210 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1211 set_ccr_zero
1212
1213 ;; mov.b @ers, rd
1214 mov.l #byte_src, er1
1215 mov.b @er1, r0l ; Register indirect operand
1216 ;;; .word 0x6818
1217
1218 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1219 test_neg_clear
1220 test_zero_clear
1221 test_ovf_clear
1222 test_carry_clear
1223
1224 test_h_gr32 0xa5a5a577 er0
1225
1226 test_h_gr32 byte_src, er1
1227 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1228 test_gr_a5a5 3
1229 test_gr_a5a5 4
1230 test_gr_a5a5 5
1231 test_gr_a5a5 6
1232 test_gr_a5a5 7
1233
1234 mov_b_postinc_to_reg8: ; post-increment from mem to register
1235 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1236 set_ccr_zero
1237
1238 ;; mov.b @ers+, rd
1239
1240 mov.l #byte_src, er1
1241 mov.b @er1+, r0l ; Register post-incr operand
1242 ;;; .word 0x6c18
1243
1244 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1245 test_neg_clear
1246 test_zero_clear
1247 test_ovf_clear
1248 test_carry_clear
1249
1250 test_h_gr32 0xa5a5a577 er0
1251
1252 test_h_gr32 byte_src+1, er1
1253 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1254 test_gr_a5a5 3
1255 test_gr_a5a5 4
1256 test_gr_a5a5 5
1257 test_gr_a5a5 6
1258 test_gr_a5a5 7
1259
1260 .if (sim_cpu == h8sx)
1261 mov_b_postdec_to_reg8: ; post-decrement from mem to register
1262 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1263 set_ccr_zero
1264
1265 ;; mov.b @ers-, rd
1266
1267 mov.l #byte_src, er1
1268 mov.b @er1-, r0l ; Register post-decr operand
1269 ;;; .word 0x0172
1270 ;;; .word 0x6c18
1271
1272 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1273 test_neg_clear
1274 test_zero_clear
1275 test_ovf_clear
1276 test_carry_clear
1277
1278 test_h_gr32 0xa5a5a577 er0
1279
1280 test_h_gr32 byte_src-1, er1
1281 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1282 test_gr_a5a5 3
1283 test_gr_a5a5 4
1284 test_gr_a5a5 5
1285 test_gr_a5a5 6
1286 test_gr_a5a5 7
1287
1288 mov_b_preinc_to_reg8: ; pre-increment from mem to register
1289 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1290 set_ccr_zero
1291
1292 ;; mov.b @+ers, rd
1293
1294 mov.l #byte_src-1, er1
1295 mov.b @+er1, r0l ; Register pre-incr operand
1296 ;;; .word 0x0171
1297 ;;; .word 0x6c18
1298
1299 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1300 test_neg_clear
1301 test_zero_clear
1302 test_ovf_clear
1303 test_carry_clear
1304
1305 test_h_gr32 0xa5a5a577 er0
1306
1307 test_h_gr32 byte_src, er1
1308 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1309 test_gr_a5a5 3
1310 test_gr_a5a5 4
1311 test_gr_a5a5 5
1312 test_gr_a5a5 6
1313 test_gr_a5a5 7
1314
1315 mov_b_predec_to_reg8: ; pre-decrement from mem to register
1316 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1317 set_ccr_zero
1318
1319 ;; mov.b @-ers, rd
1320
1321 mov.l #byte_src+1, er1
1322 mov.b @-er1, r0l ; Register pre-decr operand
1323 ;;; .word 0x0173
1324 ;;; .word 0x6c18
1325
1326 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1327 test_neg_clear
1328 test_zero_clear
1329 test_ovf_clear
1330 test_carry_clear
1331
1332 test_h_gr32 0xa5a5a577 er0
1333
1334 test_h_gr32 byte_src, er1
1335 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1336 test_gr_a5a5 3
1337 test_gr_a5a5 4
1338 test_gr_a5a5 5
1339 test_gr_a5a5 6
1340 test_gr_a5a5 7
1341
1342
1343 mov_b_disp2_to_reg8:
1344 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1345 set_ccr_zero
1346
1347 ;; mov.b @(dd:2, ers), rd
1348 mov.l #byte_src-1, er1
1349 mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand
1350 ;;; .word 0x0171
1351 ;;; .word 0x6818
1352
1353 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1354 test_neg_clear
1355 test_zero_clear
1356 test_ovf_clear
1357 test_carry_clear
1358
1359 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
1360
1361 test_h_gr32 byte_src-1, er1
1362 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1363 test_gr_a5a5 3
1364 test_gr_a5a5 4
1365 test_gr_a5a5 5
1366 test_gr_a5a5 6
1367 test_gr_a5a5 7
1368 .endif
1369
1370 mov_b_disp16_to_reg8:
1371 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1372 set_ccr_zero
1373
1374 ;; mov.b @(dd:16, ers), rd
1375 mov.l #byte_src+0x1234, er1
1376 mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand
1377 ;;; .word 0x6e18
1378 ;;; .word -0x1234
1379
1380 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1381 test_neg_clear
1382 test_zero_clear
1383 test_ovf_clear
1384 test_carry_clear
1385
1386 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
1387
1388 test_h_gr32 byte_src+0x1234, er1
1389 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1390 test_gr_a5a5 3
1391 test_gr_a5a5 4
1392 test_gr_a5a5 5
1393 test_gr_a5a5 6
1394 test_gr_a5a5 7
1395
1396 mov_b_disp32_to_reg8:
1397 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1398 set_ccr_zero
1399
1400 ;; mov.b @(dd:32, ers), rd
1401 mov.l #byte_src+65536, er1
1402 mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand
1403 ;;; .word 0x7810
1404 ;;; .word 0x6a28
1405 ;;; .long -65536
1406
1407 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1408 test_neg_clear
1409 test_zero_clear
1410 test_ovf_clear
1411 test_carry_clear
1412
1413 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
1414
1415 test_h_gr32 byte_src+65536, er1
1416 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1417 test_gr_a5a5 3
1418 test_gr_a5a5 4
1419 test_gr_a5a5 5
1420 test_gr_a5a5 6
1421 test_gr_a5a5 7
1422
1423 .if (sim_cpu == h8sx)
1424 mov_b_indexb16_to_reg8:
1425 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1426 mov.l #0xffffff01, er1
1427 set_ccr_zero
1428 ;; mov.b @(dd:16, rs.b), rd
1429 mov.b @(byte_src-1:16, r1.b), r0l ; indexed byte operand
1430
1431 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1432 test_neg_clear
1433 test_zero_clear
1434 test_ovf_clear
1435 test_carry_clear
1436
1437 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77
1438
1439 test_h_gr32 0xffffff01, er1
1440 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1441 test_gr_a5a5 3
1442 test_gr_a5a5 4
1443 test_gr_a5a5 5
1444 test_gr_a5a5 6
1445 test_gr_a5a5 7
1446
1447 mov_b_indexw16_to_reg8:
1448 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1449 mov.l #0xffff0002, er1
1450 set_ccr_zero
1451 ;; mov.b @(dd:16, rs.w), rd
1452 mov.b @(byte_src-2:16, r1.w), r0l ; indexed byte operand
1453
1454 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1455 test_neg_clear
1456 test_zero_clear
1457 test_ovf_clear
1458 test_carry_clear
1459
1460 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77
1461
1462 test_h_gr32 0xffff0002, er1
1463 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1464 test_gr_a5a5 3
1465 test_gr_a5a5 4
1466 test_gr_a5a5 5
1467 test_gr_a5a5 6
1468 test_gr_a5a5 7
1469
1470 mov_b_indexl16_to_reg8:
1471 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1472 mov.l #0x00000003, er1
1473 set_ccr_zero
1474 ;; mov.b @(dd:16, ers.l), rd
1475 mov.b @(byte_src-3:16, er1.l), r0l ; indexed byte operand
1476
1477 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1478 test_neg_clear
1479 test_zero_clear
1480 test_ovf_clear
1481 test_carry_clear
1482
1483 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77
1484
1485 test_h_gr32 0x00000003, er1
1486 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1487 test_gr_a5a5 3
1488 test_gr_a5a5 4
1489 test_gr_a5a5 5
1490 test_gr_a5a5 6
1491 test_gr_a5a5 7
1492
1493 mov_b_indexb32_to_reg8:
1494 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1495 mov.l #0xffffff04, er1
1496 set_ccr_zero
1497 ;; mov.b @(dd:32, rs.b), rd
1498 mov.b @(byte_src-4:32, r1.b), r0l ; indexed byte operand
1499
1500 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1501 test_neg_clear
1502 test_zero_clear
1503 test_ovf_clear
1504 test_carry_clear
1505
1506 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
1507
1508 test_h_gr32 0xffffff04 er1
1509 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1510 test_gr_a5a5 3
1511 test_gr_a5a5 4
1512 test_gr_a5a5 5
1513 test_gr_a5a5 6
1514 test_gr_a5a5 7
1515
1516 mov_b_indexw32_to_reg8:
1517 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1518 mov.l #0xffff0005, er1
1519 set_ccr_zero
1520 ;; mov.b @(dd:32, rs.w), rd
1521 mov.b @(byte_src-5:32, r1.w), r0l ; indexed byte operand
1522
1523 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1524 test_neg_clear
1525 test_zero_clear
1526 test_ovf_clear
1527 test_carry_clear
1528
1529 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
1530
1531 test_h_gr32 0xffff0005 er1
1532 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1533 test_gr_a5a5 3
1534 test_gr_a5a5 4
1535 test_gr_a5a5 5
1536 test_gr_a5a5 6
1537 test_gr_a5a5 7
1538
1539 mov_b_indexl32_to_reg8:
1540 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1541 mov.l #0x00000006, er1
1542 set_ccr_zero
1543 ;; mov.b @(dd:32, ers.l), rd
1544 mov.b @(byte_src-6:32, er1.l), r0l ; indexed byte operand
1545
1546 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1547 test_neg_clear
1548 test_zero_clear
1549 test_ovf_clear
1550 test_carry_clear
1551
1552 test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777
1553
1554 test_h_gr32 0x00000006 er1
1555 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1556 test_gr_a5a5 3
1557 test_gr_a5a5 4
1558 test_gr_a5a5 5
1559 test_gr_a5a5 6
1560 test_gr_a5a5 7
1561
1562 .endif
1563
1564 .if (sim_cpu == h8sx)
1565 mov_b_abs8_to_reg8:
1566 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1567 mov.l #byte_src-255, er1
1568 ldc er1, sbr
1569 set_ccr_zero
1570 ;; mov.b @aa:8, rd
1571 mov.b @0xff:8, r0l ; 8-bit (sbr relative) address-direct operand
1572
1573 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1574 test_neg_clear
1575 test_zero_clear
1576 test_ovf_clear
1577 test_carry_clear
1578
1579 test_h_gr32 0xa5a5a577 er0
1580
1581 test_h_gr32 byte_src-255, er1
1582 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1583 test_gr_a5a5 3
1584 test_gr_a5a5 4
1585 test_gr_a5a5 5
1586 test_gr_a5a5 6
1587 test_gr_a5a5 7
1588 .endif
1589
1590 mov_b_abs16_to_reg8:
1591 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1592 set_ccr_zero
1593
1594 ;; mov.b @aa:16, rd
1595 mov.b @byte_src:16, r0l ; 16-bit address-direct operand
1596 ;;; .word 0x6a08
1597 ;;; .word @byte_src
1598
1599 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1600 test_neg_clear
1601 test_zero_clear
1602 test_ovf_clear
1603 test_carry_clear
1604
1605 test_h_gr32 0xa5a5a577 er0
1606
1607 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1608 test_gr_a5a5 2
1609 test_gr_a5a5 3
1610 test_gr_a5a5 4
1611 test_gr_a5a5 5
1612 test_gr_a5a5 6
1613 test_gr_a5a5 7
1614
1615 mov_b_abs32_to_reg8:
1616 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1617 set_ccr_zero
1618
1619 ;; mov.b @aa:32, rd
1620 mov.b @byte_src:32, r0l ; 32-bit address-direct operand
1621 ;;; .word 0x6a28
1622 ;;; .long @byte_src
1623
1624 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1625 test_neg_clear
1626 test_zero_clear
1627 test_ovf_clear
1628 test_carry_clear
1629
1630 test_h_gr32 0xa5a5a577 er0
1631
1632 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1633 test_gr_a5a5 2
1634 test_gr_a5a5 3
1635 test_gr_a5a5 4
1636 test_gr_a5a5 5
1637 test_gr_a5a5 6
1638 test_gr_a5a5 7
1639
1640 .if (sim_cpu == h8sx)
1641
1642 ;;
1643 ;; Move byte from memory to memory
1644 ;;
1645
1646 mov_b_indirect_to_indirect: ; reg indirect, memory to memory
1647 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1648 set_ccr_zero
1649
1650 ;; mov.b @ers, @erd
1651
1652 mov.l #byte_src, er1
1653 mov.l #byte_dst, er0
1654 mov.b @er1, @er0
1655 ;;; .word 0x0178
1656 ;;; .word 0x0100
1657
1658 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1659 test_neg_clear
1660 test_zero_clear
1661 test_ovf_clear
1662 test_carry_clear
1663
1664 ;; Verify the affected registers.
1665
1666 test_h_gr32 byte_dst er0
1667 test_h_gr32 byte_src er1
1668 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1669 test_gr_a5a5 3
1670 test_gr_a5a5 4
1671 test_gr_a5a5 5
1672 test_gr_a5a5 6
1673 test_gr_a5a5 7
1674
1675 ;; Now check the result of the move to memory.
1676 cmp.b @byte_src, @byte_dst
1677 beq .Lnext56
1678 fail
1679 .Lnext56:
1680 ;; Now clear the destination location, and verify that.
1681 mov.b #0, @byte_dst
1682 cmp.b @byte_src, @byte_dst
1683 bne .Lnext57
1684 fail
1685 .Lnext57: ; OK, pass on.
1686
1687 mov_b_postinc_to_postinc: ; reg post-increment, memory to memory
1688 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1689 set_ccr_zero
1690
1691 ;; mov.b @ers+, @erd+
1692
1693 mov.l #byte_src, er1
1694 mov.l #byte_dst, er0
1695 mov.b @er1+, @er0+
1696 ;;; .word 0x0178
1697 ;;; .word 0x8180
1698
1699 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1700 test_neg_clear
1701 test_zero_clear
1702 test_ovf_clear
1703 test_carry_clear
1704
1705 ;; Verify the affected registers.
1706
1707 test_h_gr32 byte_dst+1 er0
1708 test_h_gr32 byte_src+1 er1
1709 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1710 test_gr_a5a5 3
1711 test_gr_a5a5 4
1712 test_gr_a5a5 5
1713 test_gr_a5a5 6
1714 test_gr_a5a5 7
1715
1716 ;; Now check the result of the move to memory.
1717 cmp.b @byte_src, @byte_dst
1718 beq .Lnext65
1719 fail
1720 .Lnext65:
1721 ;; Now clear the destination location, and verify that.
1722 mov.b #0, @byte_dst
1723 cmp.b @byte_src, @byte_dst
1724 bne .Lnext66
1725 fail
1726 .Lnext66: ; OK, pass on.
1727 ;; special case same register
1728 mov.l #byte_src, er0
1729 mov.b @er0+, @er0+ ; copying byte_src to byte_dst
1730 test_h_gr32 byte_src+2 er0
1731 cmp.b @byte_src, @byte_dst
1732 beq .Lnext67
1733 fail
1734 .Lnext67:
1735 ;; Now clear the destination location, and verify that.
1736 mov.b #0, @byte_dst
1737 cmp.b @byte_src, @byte_dst
1738 bne .Lnext68
1739 fail
1740 .Lnext68:
1741
1742 mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory
1743 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1744 set_ccr_zero
1745
1746 ;; mov.b @ers-, @erd-
1747
1748 mov.l #byte_src, er1
1749 mov.l #byte_dst, er0
1750 mov.b @er1-, @er0-
1751 ;;; .word 0x0178
1752 ;;; .word 0xa1a0
1753
1754 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1755 test_neg_clear
1756 test_zero_clear
1757 test_ovf_clear
1758 test_carry_clear
1759
1760 ;; Verify the affected registers.
1761
1762 test_h_gr32 byte_dst-1 er0
1763 test_h_gr32 byte_src-1 er1
1764 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1765 test_gr_a5a5 3
1766 test_gr_a5a5 4
1767 test_gr_a5a5 5
1768 test_gr_a5a5 6
1769 test_gr_a5a5 7
1770
1771 ;; Now check the result of the move to memory.
1772 cmp.b @byte_src, @byte_dst
1773 beq .Lnext75
1774 fail
1775 .Lnext75:
1776 ;; Now clear the destination location, and verify that.
1777 mov.b #0, @byte_dst
1778 cmp.b @byte_src, @byte_dst
1779 bne .Lnext76
1780 fail
1781 .Lnext76: ; OK, pass on.
1782 ;; special case same register
1783 mov.l #byte_src, er0
1784 mov.b @er0-, @er0- ; copying byte_src to byte_dst_dec
1785 test_h_gr32 byte_src-2 er0
1786 cmp.b @byte_src, @byte_dst_dec
1787 beq .Lnext77
1788 fail
1789 .Lnext77:
1790 ;; Now clear the destination location, and verify that.
1791 mov.b #0, @byte_dst_dec
1792 cmp.b @byte_src, @byte_dst_dec
1793 bne .Lnext78
1794 fail
1795 .Lnext78:
1796
1797 mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory
1798 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1799 set_ccr_zero
1800
1801 ;; mov.b @+ers, @+erd
1802
1803 mov.l #byte_src-1, er1
1804 mov.l #byte_dst-1, er0
1805 mov.b @+er1, @+er0
1806 ;;; .word 0x0178
1807 ;;; .word 0x9190
1808
1809 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1810 test_neg_clear
1811 test_zero_clear
1812 test_ovf_clear
1813 test_carry_clear
1814
1815 ;; Verify the affected registers.
1816
1817 test_h_gr32 byte_dst er0
1818 test_h_gr32 byte_src er1
1819 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1820 test_gr_a5a5 3
1821 test_gr_a5a5 4
1822 test_gr_a5a5 5
1823 test_gr_a5a5 6
1824 test_gr_a5a5 7
1825
1826 ;; Now check the result of the move to memory.
1827 cmp.b @byte_src, @byte_dst
1828 beq .Lnext85
1829 fail
1830 .Lnext85:
1831 ;; Now clear the destination location, and verify that.
1832 mov.b #0, @byte_dst
1833 cmp.b @byte_src, @byte_dst
1834 bne .Lnext86
1835 fail
1836 .Lnext86: ; OK, pass on.
1837 ;; special case same register
1838 mov.l #byte_src-1, er0
1839 mov.b @+er0, @+er0 ; copying byte_src to byte_dst
1840 test_h_gr32 byte_src+1 er0
1841 cmp.b @byte_src, @byte_dst
1842 beq .Lnext87
1843 fail
1844 .Lnext87:
1845 ;; Now clear the destination location, and verify that.
1846 mov.b #0, @byte_dst
1847 cmp.b @byte_src, @byte_dst
1848 bne .Lnext88
1849 fail
1850 .Lnext88:
1851
1852 mov_b_predec_to_predec: ; reg pre-decrement, memory to memory
1853 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1854 set_ccr_zero
1855
1856 ;; mov.b @-ers, @-erd
1857
1858 mov.l #byte_src+1, er1
1859 mov.l #byte_dst+1, er0
1860 mov.b @-er1, @-er0
1861 ;;; .word 0x0178
1862 ;;; .word 0xb1b0
1863
1864 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1865 test_neg_clear
1866 test_zero_clear
1867 test_ovf_clear
1868 test_carry_clear
1869
1870 ;; Verify the affected registers.
1871
1872 test_h_gr32 byte_dst er0
1873 test_h_gr32 byte_src er1
1874 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1875 test_gr_a5a5 3
1876 test_gr_a5a5 4
1877 test_gr_a5a5 5
1878 test_gr_a5a5 6
1879 test_gr_a5a5 7
1880
1881 ;; Now check the result of the move to memory.
1882 cmp.b @byte_src, @byte_dst
1883 beq .Lnext95
1884 fail
1885 .Lnext95:
1886 ;; Now clear the destination location, and verify that.
1887 mov.b #0, @byte_dst
1888 cmp.b @byte_src, @byte_dst
1889 bne .Lnext96
1890 fail
1891 .Lnext96: ; OK, pass on.
1892 ;; special case same register
1893 mov.l #byte_src+1, er0
1894 mov.b @-er0, @-er0 ; copying byte_src to byte_dst_dec
1895 test_h_gr32 byte_src-1 er0
1896 cmp.b @byte_src, @byte_dst_dec
1897 beq .Lnext97
1898 fail
1899 .Lnext97:
1900 ;; Now clear the destination location, and verify that.
1901 mov.b #0, @byte_dst_dec
1902 cmp.b @byte_src, @byte_dst_dec
1903 bne .Lnext98
1904 fail
1905 .Lnext98:
1906
1907 mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory
1908 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1909 set_ccr_zero
1910
1911 ;; mov.b @(dd:2, ers), @(dd:2, erd)
1912
1913 mov.l #byte_src-1, er1
1914 mov.l #byte_dst-2, er0
1915 mov.b @(1:2, er1), @(2:2, er0)
1916 ;;; .word 0x0178
1917 ;;; .word 0x1120
1918
1919 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1920 test_neg_clear
1921 test_zero_clear
1922 test_ovf_clear
1923 test_carry_clear
1924
1925 ;; Verify the affected registers.
1926
1927 test_h_gr32 byte_dst-2 er0
1928 test_h_gr32 byte_src-1 er1
1929 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1930 test_gr_a5a5 3
1931 test_gr_a5a5 4
1932 test_gr_a5a5 5
1933 test_gr_a5a5 6
1934 test_gr_a5a5 7
1935
1936 ;; Now check the result of the move to memory.
1937 cmp.b @byte_src, @byte_dst
1938 beq .Lnext105
1939 fail
1940 .Lnext105:
1941 ;; Now clear the destination location, and verify that.
1942 mov.b #0, @byte_dst
1943 cmp.b @byte_src, @byte_dst
1944 bne .Lnext106
1945 fail
1946 .Lnext106: ; OK, pass on.
1947
1948 mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory
1949 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1950 set_ccr_zero
1951
1952 ;; mov.b @(dd:16, ers), @(dd:16, erd)
1953
1954 mov.l #byte_src-1, er1
1955 mov.l #byte_dst-2, er0
1956 mov.b @(1:16, er1), @(2:16, er0)
1957 ;;; .word 0x0178
1958 ;;; .word 0xc1c0
1959 ;;; .word 0x0001
1960 ;;; .word 0x0002
1961
1962 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1963 test_neg_clear
1964 test_zero_clear
1965 test_ovf_clear
1966 test_carry_clear
1967
1968 ;; Verify the affected registers.
1969
1970 test_h_gr32 byte_dst-2 er0
1971 test_h_gr32 byte_src-1 er1
1972 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1973 test_gr_a5a5 3
1974 test_gr_a5a5 4
1975 test_gr_a5a5 5
1976 test_gr_a5a5 6
1977 test_gr_a5a5 7
1978
1979 ;; Now check the result of the move to memory.
1980 cmp.b @byte_src, @byte_dst
1981 beq .Lnext115
1982 fail
1983 .Lnext115:
1984 ;; Now clear the destination location, and verify that.
1985 mov.b #0, @byte_dst
1986 cmp.b @byte_src, @byte_dst
1987 bne .Lnext116
1988 fail
1989 .Lnext116: ; OK, pass on.
1990
1991 mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory
1992 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1993 set_ccr_zero
1994
1995 ;; mov.b @(dd:32, ers), @(dd:32, erd)
1996
1997 mov.l #byte_src-1, er1
1998 mov.l #byte_dst-2, er0
1999 mov.b @(1:32, er1), @(2:32, er0)
2000 ;;; .word 0x0178
2001 ;;; .word 0xc9c8
2002 ;;; .long 1
2003 ;;; .long 2
2004
2005 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2006 test_neg_clear
2007 test_zero_clear
2008 test_ovf_clear
2009 test_carry_clear
2010
2011 ;; Verify the affected registers.
2012
2013 test_h_gr32 byte_dst-2 er0
2014 test_h_gr32 byte_src-1 er1
2015 test_gr_a5a5 2 ; Make sure other general regs not disturbed
2016 test_gr_a5a5 3
2017 test_gr_a5a5 4
2018 test_gr_a5a5 5
2019 test_gr_a5a5 6
2020 test_gr_a5a5 7
2021
2022 ;; Now check the result of the move to memory.
2023 cmp.b @byte_src, @byte_dst
2024 beq .Lnext125
2025 fail
2026 .Lnext125:
2027 ;; Now clear the destination location, and verify that.
2028 mov.b #0, @byte_dst
2029 cmp.b @byte_src, @byte_dst
2030 bne .Lnext126
2031 fail
2032 .Lnext126: ; OK, pass on.
2033
2034 mov_b_indexb16_to_indexb16: ; reg 16-bit indexed, memory to memory
2035 set_grs_a5a5 ; Fill all general regs with a fixed pattern
2036 mov.l #0xffffff01, er1
2037 mov.l #0xffffff02, er0
2038 ;; mov.b @(dd:16, rs.b), @(dd:16, rd.b)
2039 set_ccr_zero
2040 mov.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r0.b)
2041
2042 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2043 test_neg_clear
2044 test_zero_clear
2045 test_ovf_clear
2046 test_carry_clear
2047
2048 ;; Verify the affected registers.
2049
2050 test_h_gr32 0xffffff02 er0
2051 test_h_gr32 0xffffff01 er1
2052 test_gr_a5a5 2 ; Make sure other general regs not disturbed
2053 test_gr_a5a5 3
2054 test_gr_a5a5 4
2055 test_gr_a5a5 5
2056 test_gr_a5a5 6
2057 test_gr_a5a5 7
2058
2059 ;; Now check the result of the move to memory.
2060 cmp.b @byte_src, @byte_dst
2061 bne fail1
2062 ;; Now clear the destination location, and verify that.
2063 mov.b #0, @byte_dst
2064 cmp.b @byte_src, @byte_dst
2065 beq fail1
2066
2067 mov_b_indexw16_to_indewb16: ; reg 16-bit indexed, memory to memory
2068 set_grs_a5a5 ; Fill all general regs with a fixed pattern
2069 mov.l #0xffff0003, er1
2070 mov.l #0xffff0004, er0
2071 ;; mov.b @(dd:16, rs.w), @(dd:16, rd.w)
2072 set_ccr_zero
2073 mov.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r0.w)
2074
2075 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2076 test_neg_clear
2077 test_zero_clear
2078 test_ovf_clear
2079 test_carry_clear
2080
2081 ;; Verify the affected registers.
2082
2083 test_h_gr32 0xffff0004 er0
2084 test_h_gr32 0xffff0003 er1
2085 test_gr_a5a5 2 ; Make sure other general regs not disturbed
2086 test_gr_a5a5 3
2087 test_gr_a5a5 4
2088 test_gr_a5a5 5
2089 test_gr_a5a5 6
2090 test_gr_a5a5 7
2091
2092 ;; Now check the result of the move to memory.
2093 cmp.b @byte_src, @byte_dst
2094 bne fail1
2095 ;; Now clear the destination location, and verify that.
2096 mov.b #0, @byte_dst
2097 cmp.b @byte_src, @byte_dst
2098 beq fail1
2099
2100 mov_b_indexl16_to_indexl16: ; reg 16-bit indexed, memory to memory
2101 set_grs_a5a5 ; Fill all general regs with a fixed pattern
2102 mov.l #0x00000005, er1
2103 mov.l #0x00000006, er0
2104 ;; mov.b @(dd:16, ers.l), @(dd:16, erd.l)
2105 set_ccr_zero
2106 mov.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er0.l)
2107
2108 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2109 test_neg_clear
2110 test_zero_clear
2111 test_ovf_clear
2112 test_carry_clear
2113
2114 ;; Verify the affected registers.
2115
2116 test_h_gr32 0x00000006 er0
2117 test_h_gr32 0x00000005 er1
2118 test_gr_a5a5 2 ; Make sure other general regs not disturbed
2119 test_gr_a5a5 3
2120 test_gr_a5a5 4
2121 test_gr_a5a5 5
2122 test_gr_a5a5 6
2123 test_gr_a5a5 7
2124
2125 ;; Now check the result of the move to memory.
2126 cmp.b @byte_src, @byte_dst
2127 bne fail1
2128 ;; Now clear the destination location, and verify that.
2129 mov.b #0, @byte_dst
2130 cmp.b @byte_src, @byte_dst
2131 beq fail1
2132
2133 mov_b_indexb32_to_indexb32: ; reg 32-bit indexed, memory to memory
2134 set_grs_a5a5 ; Fill all general regs with a fixed pattern
2135 mov.l #0xffffff01, er1
2136 mov.l #0xffffff02, er0
2137 set_ccr_zero
2138 ;; mov.b @(dd:32, rs.b), @(dd:32, rd.b)
2139 mov.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r0.b)
2140
2141 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2142 test_neg_clear
2143 test_zero_clear
2144 test_ovf_clear
2145 test_carry_clear
2146
2147 ;; Verify the affected registers.
2148
2149 test_h_gr32 0xffffff02 er0
2150 test_h_gr32 0xffffff01 er1
2151 test_gr_a5a5 2 ; Make sure other general regs not disturbed
2152 test_gr_a5a5 3
2153 test_gr_a5a5 4
2154 test_gr_a5a5 5
2155 test_gr_a5a5 6
2156 test_gr_a5a5 7
2157
2158 ;; Now check the result of the move to memory.
2159 cmp.b @byte_src, @byte_dst
2160 bne fail1
2161 ;; Now clear the destination location, and verify that.
2162 mov.b #0, @byte_dst
2163 cmp.b @byte_src, @byte_dst
2164 beq fail1
2165
2166 mov_b_indexw32_to_indexw32: ; reg 32-bit indexed, memory to memory
2167 set_grs_a5a5 ; Fill all general regs with a fixed pattern
2168 mov.l #0xffff0003, er1
2169 mov.l #0xffff0004, er0
2170 set_ccr_zero
2171 ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w)
2172 mov.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r0.w)
2173
2174 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2175 test_neg_clear
2176 test_zero_clear
2177 test_ovf_clear
2178 test_carry_clear
2179
2180 ;; Verify the affected registers.
2181
2182 test_h_gr32 0xffff0004 er0
2183 test_h_gr32 0xffff0003 er1
2184 test_gr_a5a5 2 ; Make sure other general regs not disturbed
2185 test_gr_a5a5 3
2186 test_gr_a5a5 4
2187 test_gr_a5a5 5
2188 test_gr_a5a5 6
2189 test_gr_a5a5 7
2190
2191 ;; Now check the result of the move to memory.
2192 cmp.b @byte_src, @byte_dst
2193 bne fail1
2194 ;; Now clear the destination location, and verify that.
2195 mov.b #0, @byte_dst
2196 cmp.b @byte_src, @byte_dst
2197 beq fail1
2198
2199 mov_b_indexl32_to_indexl32: ; reg 32-bit indexed, memory to memory
2200 set_grs_a5a5 ; Fill all general regs with a fixed pattern
2201 mov.l #0x00000005, er1
2202 mov.l #0x00000006, er0
2203 set_ccr_zero
2204 ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w)
2205 mov.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er0.l)
2206
2207 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2208 test_neg_clear
2209 test_zero_clear
2210 test_ovf_clear
2211 test_carry_clear
2212
2213 ;; Verify the affected registers.
2214
2215 test_h_gr32 0x00000006 er0
2216 test_h_gr32 0x00000005 er1
2217 test_gr_a5a5 2 ; Make sure other general regs not disturbed
2218 test_gr_a5a5 3
2219 test_gr_a5a5 4
2220 test_gr_a5a5 5
2221 test_gr_a5a5 6
2222 test_gr_a5a5 7
2223
2224 ;; Now check the result of the move to memory.
2225 cmp.b @byte_src, @byte_dst
2226 bne fail1
2227 ;; Now clear the destination location, and verify that.
2228 mov.b #0, @byte_dst
2229 cmp.b @byte_src, @byte_dst
2230 beq fail1
2231
2232 mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
2233 set_grs_a5a5 ; Fill all general regs with a fixed pattern
2234 set_ccr_zero
2235
2236 ;; mov.b @aa:16, @aa:16
2237
2238 mov.b @byte_src:16, @byte_dst:16
2239 ;;; .word 0x0178
2240 ;;; .word 0x4040
2241 ;;; .word @byte_src
2242 ;;; .word @byte_dst
2243
2244 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2245 test_neg_clear
2246 test_zero_clear
2247 test_ovf_clear
2248 test_carry_clear
2249
2250
2251 test_gr_a5a5 0 ; Make sure *NO* general registers are changed
2252 test_gr_a5a5 1
2253 test_gr_a5a5 2
2254 test_gr_a5a5 3
2255 test_gr_a5a5 4
2256 test_gr_a5a5 5
2257 test_gr_a5a5 6
2258 test_gr_a5a5 7
2259
2260 ;; Now check the result of the move to memory.
2261 cmp.b @byte_src, @byte_dst
2262 beq .Lnext135
2263 fail
2264 .Lnext135:
2265 ;; Now clear the destination location, and verify that.
2266 mov.b #0, @byte_dst
2267 cmp.b @byte_src, @byte_dst
2268 bne .Lnext136
2269 fail
2270 .Lnext136: ; OK, pass on.
2271
2272 mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
2273 set_grs_a5a5 ; Fill all general regs with a fixed pattern
2274 set_ccr_zero
2275
2276 ;; mov.b @aa:32, @aa:32
2277
2278 mov.b @byte_src:32, @byte_dst:32
2279 ;;; .word 0x0178
2280 ;;; .word 0x4848
2281 ;;; .long @byte_src
2282 ;;; .long @byte_dst
2283
2284 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
2285 test_neg_clear
2286 test_zero_clear
2287 test_ovf_clear
2288 test_carry_clear
2289
2290 test_gr_a5a5 0 ; Make sure *NO* general registers are changed
2291 test_gr_a5a5 1
2292 test_gr_a5a5 2
2293 test_gr_a5a5 3
2294 test_gr_a5a5 4
2295 test_gr_a5a5 5
2296 test_gr_a5a5 6
2297 test_gr_a5a5 7
2298
2299 ;; Now check the result of the move to memory.
2300 cmp.b @byte_src, @byte_dst
2301 beq .Lnext145
2302 fail
2303 .Lnext145:
2304 ;; Now clear the destination location, and verify that.
2305 mov.b #0, @byte_dst
2306 cmp.b @byte_src, @byte_dst
2307 bne .Lnext146
2308 fail
2309 .Lnext146: ; OK, pass on.
2310
2311
2312 .endif
2313
2314 pass
2315
2316 exit 0
2317
2318 fail1:
2319 fail