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[binutils-gdb.git] / sim / testsuite / h8300 / movw.s
1 # Hitachi H8 testcase 'mov.w'
2 # mach(): h8300h h8300s h8sx
3 # as(h8300h): --defsym sim_cpu=1
4 # as(h8300s): --defsym sim_cpu=2
5 # as(h8sx): --defsym sim_cpu=3
6 # ld(h8300h): -m h8300helf
7 # ld(h8300s): -m h8300self
8 # ld(h8sx): -m h8300sxelf
9
10 .include "testutils.inc"
11
12 start
13
14 .data
15 .align 2
16 word_dst_dec:
17 .word 0
18 word_src:
19 .word 0x7777
20 word_dst:
21 .word 0
22
23 .text
24
25 ;;
26 ;; Move word from immediate source
27 ;;
28
29 .if (sim_cpu == h8sx)
30 mov_w_imm3_to_reg16:
31 set_grs_a5a5 ; Fill all general regs with a fixed pattern
32 set_ccr_zero
33
34 ;; mov.w #xx:3, rd
35 mov.w #0x3:3, r0 ; Immediate 3-bit operand
36 ;;; .word 0x0f30
37
38 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
39 test_neg_clear
40 test_zero_clear
41 test_ovf_clear
42 test_carry_clear
43
44 test_h_gr32 0xa5a50003 er0
45
46 test_gr_a5a5 1 ; Make sure other general regs not disturbed
47 test_gr_a5a5 2
48 test_gr_a5a5 3
49 test_gr_a5a5 4
50 test_gr_a5a5 5
51 test_gr_a5a5 6
52 test_gr_a5a5 7
53 .endif
54
55 mov_w_imm16_to_reg16:
56 set_grs_a5a5 ; Fill all general regs with a fixed pattern
57 set_ccr_zero
58
59 ;; mov.w #xx:16, rd
60 mov.w #0x1234, r0 ; Immediate 16-bit operand
61 ;;; .word 0x7900
62 ;;; .word 0x1234
63
64 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
65 test_neg_clear
66 test_zero_clear
67 test_ovf_clear
68 test_carry_clear
69
70 test_h_gr32 0xa5a51234 er0
71
72 test_gr_a5a5 1 ; Make sure other general regs not disturbed
73 test_gr_a5a5 2
74 test_gr_a5a5 3
75 test_gr_a5a5 4
76 test_gr_a5a5 5
77 test_gr_a5a5 6
78 test_gr_a5a5 7
79
80 .if (sim_cpu == h8sx)
81 mov_w_imm4_to_abs16:
82 set_grs_a5a5 ; Fill all general regs with a fixed pattern
83 set_ccr_zero
84
85 ;; mov.w #xx:4, @aa:16
86 mov.w #0xf:4, @word_dst:16 ; 4-bit imm to 16-bit address-direct
87 ;;; .word 0x6bdf
88 ;;; .word @word_dst
89
90 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
91 test_neg_clear
92 test_zero_clear
93 test_ovf_clear
94 test_carry_clear
95
96 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
97 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
98 test_gr_a5a5 2 ; to examine the destination memory).
99 test_gr_a5a5 3
100 test_gr_a5a5 4
101 test_gr_a5a5 5
102 test_gr_a5a5 6
103 test_gr_a5a5 7
104
105 ;; Now check the result of the move to memory.
106 cmp.w #0xf, @word_dst
107 beq .Lnext21
108 fail
109 .Lnext21:
110 mov.w #0, @word_dst ; zero it again for the next use.
111
112 mov_w_imm4_to_abs32:
113 set_grs_a5a5 ; Fill all general regs with a fixed pattern
114 set_ccr_zero
115
116 ;; mov.w #xx:4, @aa:32
117 mov.w #0xf:4, @word_dst:32 ; 4-bit imm to 32-bit address-direct
118 ;;; .word 0x6bff
119 ;;; .long @word_dst
120
121 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
122 test_neg_clear
123 test_zero_clear
124 test_ovf_clear
125 test_carry_clear
126
127 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
128 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
129 test_gr_a5a5 2 ; to examine the destination memory).
130 test_gr_a5a5 3
131 test_gr_a5a5 4
132 test_gr_a5a5 5
133 test_gr_a5a5 6
134 test_gr_a5a5 7
135
136 ;; Now check the result of the move to memory.
137 cmp.w #0xf, @word_dst
138 beq .Lnext22
139 fail
140 .Lnext22:
141 mov.w #0, @word_dst ; zero it again for the next use.
142
143 mov_w_imm8_to_indirect:
144 set_grs_a5a5 ; Fill all general regs with a fixed pattern
145 set_ccr_zero
146
147 ;; mov.w #xx:8, @erd
148 mov.l #word_dst, er1
149 mov.w #0xa5:8, @er1 ; Register indirect operand
150 ;;; .word 0x015d
151 ;;; .word 0x01a5
152
153 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
154 test_neg_clear
155 test_zero_clear
156 test_ovf_clear
157 test_carry_clear
158
159 test_gr_a5a5 0 ; Make sure other general regs not disturbed
160 test_h_gr32 word_dst, er1
161 test_gr_a5a5 2
162 test_gr_a5a5 3
163 test_gr_a5a5 4
164 test_gr_a5a5 5
165 test_gr_a5a5 6
166 test_gr_a5a5 7
167
168 ;; Now check the result of the move to memory.
169 cmp.w #0xa5, @word_dst
170 beq .Lnext1
171 fail
172 .Lnext1:
173 mov.w #0, @word_dst ; zero it again for the next use.
174
175 mov_w_imm8_to_postinc: ; post-increment from imm8 to mem
176 set_grs_a5a5 ; Fill all general regs with a fixed pattern
177 set_ccr_zero
178
179 ;; mov.w #xx:8, @erd+
180 mov.l #word_dst, er1
181 mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands.
182 ;;; .word 0x015d
183 ;;; .word 0x81a5
184
185 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
186 test_neg_clear
187 test_zero_clear
188 test_ovf_clear
189 test_carry_clear
190
191 test_gr_a5a5 0 ; Make sure other general regs not disturbed
192 test_h_gr32 word_dst+2, er1
193 test_gr_a5a5 2
194 test_gr_a5a5 3
195 test_gr_a5a5 4
196 test_gr_a5a5 5
197 test_gr_a5a5 6
198 test_gr_a5a5 7
199
200 ;; Now check the result of the move to memory.
201 cmp.w #0xa5, @word_dst
202 beq .Lnext2
203 fail
204 .Lnext2:
205 mov.w #0, @word_dst ; zero it again for the next use.
206
207 mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem
208 set_grs_a5a5 ; Fill all general regs with a fixed pattern
209 set_ccr_zero
210
211 ;; mov.w #xx:8, @erd-
212 mov.l #word_dst, er1
213 mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands.
214 ;;; .word 0x015d
215 ;;; .word 0xa1a5
216
217 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
218 test_neg_clear
219 test_zero_clear
220 test_ovf_clear
221 test_carry_clear
222
223 test_gr_a5a5 0 ; Make sure other general regs not disturbed
224 test_h_gr32 word_dst-2, er1
225 test_gr_a5a5 2
226 test_gr_a5a5 3
227 test_gr_a5a5 4
228 test_gr_a5a5 5
229 test_gr_a5a5 6
230 test_gr_a5a5 7
231
232 ;; Now check the result of the move to memory.
233 cmp.w #0xa5, @word_dst
234 beq .Lnext3
235 fail
236 .Lnext3:
237 mov.w #0, @word_dst ; zero it again for the next use.
238
239 mov_w_imm8_to_preinc: ; pre-increment from register to mem
240 set_grs_a5a5 ; Fill all general regs with a fixed pattern
241 set_ccr_zero
242
243 ;; mov.w #xx:8, @+erd
244 mov.l #word_dst-2, er1
245 mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands
246 ;;; .word 0x015d
247 ;;; .word 0x91a5
248
249 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
250 test_neg_clear
251 test_zero_clear
252 test_ovf_clear
253 test_carry_clear
254
255 test_gr_a5a5 0 ; Make sure other general regs not disturbed
256 test_h_gr32 word_dst, er1
257 test_gr_a5a5 2
258 test_gr_a5a5 3
259 test_gr_a5a5 4
260 test_gr_a5a5 5
261 test_gr_a5a5 6
262 test_gr_a5a5 7
263
264 ;; Now check the result of the move to memory.
265 cmp.w #0xa5, @word_dst
266 beq .Lnext4
267 fail
268 .Lnext4:
269 mov.w #0, @word_dst ; zero it again for the next use.
270
271 mov_w_imm8_to_predec: ; pre-decrement from register to mem
272 set_grs_a5a5 ; Fill all general regs with a fixed pattern
273 set_ccr_zero
274
275 ;; mov.w #xx:8, @-erd
276 mov.l #word_dst+2, er1
277 mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands
278 ;;; .word 0x015d
279 ;;; .word 0xb1a5
280
281 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
282 test_neg_clear
283 test_zero_clear
284 test_ovf_clear
285 test_carry_clear
286
287 test_gr_a5a5 0 ; Make sure other general regs not disturbed
288 test_h_gr32 word_dst, er1
289 test_gr_a5a5 2
290 test_gr_a5a5 3
291 test_gr_a5a5 4
292 test_gr_a5a5 5
293 test_gr_a5a5 6
294 test_gr_a5a5 7
295
296 ;; Now check the result of the move to memory.
297 cmp.w #0xa5, @word_dst
298 beq .Lnext5
299 fail
300 .Lnext5:
301 mov.w #0, @word_dst ; zero it again for the next use.
302
303 mov_w_imm8_to_disp2:
304 set_grs_a5a5 ; Fill all general regs with a fixed pattern
305 set_ccr_zero
306
307 ;; mov.w #xx:8, @(dd:2, erd)
308 mov.l #word_dst-6, er1
309 mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand
310 ;;; .word 0x015d
311 ;;; .word 0x31a5
312
313 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
314 test_neg_clear
315 test_zero_clear
316 test_ovf_clear
317 test_carry_clear
318
319 test_gr_a5a5 0 ; Make sure other general regs not disturbed
320 test_h_gr32 word_dst-6, er1
321 test_gr_a5a5 2
322 test_gr_a5a5 3
323 test_gr_a5a5 4
324 test_gr_a5a5 5
325 test_gr_a5a5 6
326 test_gr_a5a5 7
327
328 ;; Now check the result of the move to memory.
329 cmp.w #0xa5, @word_dst
330 beq .Lnext6
331 fail
332 .Lnext6:
333 mov.w #0, @word_dst ; zero it again for the next use.
334
335 mov_w_imm8_to_disp16:
336 set_grs_a5a5 ; Fill all general regs with a fixed pattern
337 set_ccr_zero
338
339 ;; mov.w #xx:8, @(dd:16, erd)
340 mov.l #word_dst-4, er1
341 mov.w #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand
342 ;;; .word 0x015d
343 ;;; .word 0x6f90
344 ;;; .word 0x0004
345
346 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
347 test_neg_clear
348 test_zero_clear
349 test_ovf_clear
350 test_carry_clear
351
352 test_gr_a5a5 0 ; Make sure other general regs not disturbed
353 test_h_gr32 word_dst-4, er1
354 test_gr_a5a5 2
355 test_gr_a5a5 3
356 test_gr_a5a5 4
357 test_gr_a5a5 5
358 test_gr_a5a5 6
359 test_gr_a5a5 7
360
361 ;; Now check the result of the move to memory.
362 cmp.w #0xa5, @word_dst
363 beq .Lnext7
364 fail
365 .Lnext7:
366 mov.w #0, @word_dst ; zero it again for the next use.
367
368 mov_w_imm8_to_disp32:
369 set_grs_a5a5 ; Fill all general regs with a fixed pattern
370 set_ccr_zero
371
372 ;; mov.w #xx:8, @(dd:32, erd)
373 mov.l #word_dst-8, er1
374 mov.w #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand
375 ;;; .word 0x015d
376 ;;; .word 0xc9a5
377 ;;; .long 8
378
379 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
380 test_neg_clear
381 test_zero_clear
382 test_ovf_clear
383 test_carry_clear
384
385 test_gr_a5a5 0 ; Make sure other general regs not disturbed
386 test_h_gr32 word_dst-8, er1
387 test_gr_a5a5 2
388 test_gr_a5a5 3
389 test_gr_a5a5 4
390 test_gr_a5a5 5
391 test_gr_a5a5 6
392 test_gr_a5a5 7
393
394 ;; Now check the result of the move to memory.
395 cmp.w #0xa5, @word_dst
396 beq .Lnext8
397 fail
398 .Lnext8:
399 mov.w #0, @word_dst ; zero it again for the next use.
400
401 mov_w_imm8_to_abs16:
402 set_grs_a5a5 ; Fill all general regs with a fixed pattern
403 set_ccr_zero
404
405 ;; mov.w #xx:8, @aa:16
406 mov.w #0xa5:8, @word_dst:16 ; 16-bit address-direct operand
407 ;;; .word 0x015d
408 ;;; .word 0x40a5
409 ;;; .word @word_dst
410
411 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
412 test_neg_clear
413 test_zero_clear
414 test_ovf_clear
415 test_carry_clear
416
417 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
418 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
419 test_gr_a5a5 2 ; to examine the destination memory).
420 test_gr_a5a5 3
421 test_gr_a5a5 4
422 test_gr_a5a5 5
423 test_gr_a5a5 6
424 test_gr_a5a5 7
425
426 ;; Now check the result of the move to memory.
427 cmp.w #0xa5, @word_dst
428 beq .Lnext9
429 fail
430 .Lnext9:
431 mov.w #0, @word_dst ; zero it again for the next use.
432
433 mov_w_imm8_to_abs32:
434 set_grs_a5a5 ; Fill all general regs with a fixed pattern
435 set_ccr_zero
436
437 ;; mov.w #xx:8, @aa:32
438 mov.w #0xa5:8, @word_dst:32 ; 32-bit address-direct operand
439 ;;; .word 0x015d
440 ;;; .word 0x48a5
441 ;;; .long @word_dst
442
443 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
444 test_neg_clear
445 test_zero_clear
446 test_ovf_clear
447 test_carry_clear
448
449 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
450 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
451 test_gr_a5a5 2 ; to examine the destination memory).
452 test_gr_a5a5 3
453 test_gr_a5a5 4
454 test_gr_a5a5 5
455 test_gr_a5a5 6
456 test_gr_a5a5 7
457
458 ;; Now check the result of the move to memory.
459 cmp.w #0xa5, @word_dst
460 beq .Lnext10
461 fail
462 .Lnext10:
463 mov.w #0, @word_dst ; zero it again for the next use.
464
465 mov_w_imm16_to_indirect:
466 set_grs_a5a5 ; Fill all general regs with a fixed pattern
467 set_ccr_zero
468
469 ;; mov.w #xx:16, @erd
470 mov.l #word_dst, er1
471 mov.w #0xdead:16, @er1 ; Register indirect operand
472 ;;; .word 0x7974
473 ;;; .word 0xdead
474 ;;; .word 0x0100
475
476 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
477 test_neg_set
478 test_zero_clear
479 test_ovf_clear
480 test_carry_clear
481
482 test_gr_a5a5 0 ; Make sure other general regs not disturbed
483 test_h_gr32 word_dst, er1
484 test_gr_a5a5 2
485 test_gr_a5a5 3
486 test_gr_a5a5 4
487 test_gr_a5a5 5
488 test_gr_a5a5 6
489 test_gr_a5a5 7
490
491 ;; Now check the result of the move to memory.
492 cmp.w #0xdead, @word_dst
493 beq .Lnext11
494 fail
495 .Lnext11:
496 mov.w #0, @word_dst ; zero it again for the next use.
497
498 mov_w_imm16_to_postinc: ; post-increment from imm16 to mem
499 set_grs_a5a5 ; Fill all general regs with a fixed pattern
500 set_ccr_zero
501
502 ;; mov.w #xx:16, @erd+
503 mov.l #word_dst, er1
504 mov.w #0xdead:16, @er1+ ; Imm16, register post-incr operands.
505 ;;; .word 0x7974
506 ;;; .word 0xdead
507 ;;; .word 0x8100
508
509 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
510 test_neg_set
511 test_zero_clear
512 test_ovf_clear
513 test_carry_clear
514
515 test_gr_a5a5 0 ; Make sure other general regs not disturbed
516 test_h_gr32 word_dst+2, er1
517 test_gr_a5a5 2
518 test_gr_a5a5 3
519 test_gr_a5a5 4
520 test_gr_a5a5 5
521 test_gr_a5a5 6
522 test_gr_a5a5 7
523
524 ;; Now check the result of the move to memory.
525 cmp.w #0xdead, @word_dst
526 beq .Lnext12
527 fail
528 .Lnext12:
529 mov.w #0, @word_dst ; zero it again for the next use.
530
531 mov_w_imm16_to_postdec: ; post-decrement from imm16 to mem
532 set_grs_a5a5 ; Fill all general regs with a fixed pattern
533 set_ccr_zero
534
535 ;; mov.w #xx:16, @erd-
536 mov.l #word_dst, er1
537 mov.w #0xdead:16, @er1- ; Imm16, register post-decr operands.
538 ;;; .word 0x7974
539 ;;; .word 0xdead
540 ;;; .word 0xa100
541
542 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
543 test_neg_set
544 test_zero_clear
545 test_ovf_clear
546 test_carry_clear
547
548 test_gr_a5a5 0 ; Make sure other general regs not disturbed
549 test_h_gr32 word_dst-2, er1
550 test_gr_a5a5 2
551 test_gr_a5a5 3
552 test_gr_a5a5 4
553 test_gr_a5a5 5
554 test_gr_a5a5 6
555 test_gr_a5a5 7
556
557 ;; Now check the result of the move to memory.
558 cmp.w #0xdead, @word_dst
559 beq .Lnext13
560 fail
561 .Lnext13:
562 mov.w #0, @word_dst ; zero it again for the next use.
563
564 mov_w_imm16_to_preinc: ; pre-increment from register to mem
565 set_grs_a5a5 ; Fill all general regs with a fixed pattern
566 set_ccr_zero
567
568 ;; mov.w #xx:16, @+erd
569 mov.l #word_dst-2, er1
570 mov.w #0xdead:16, @+er1 ; Imm16, register pre-incr operands
571 ;;; .word 0x7974
572 ;;; .word 0xdead
573 ;;; .word 0x9100
574
575 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
576 test_neg_set
577 test_zero_clear
578 test_ovf_clear
579 test_carry_clear
580
581 test_gr_a5a5 0 ; Make sure other general regs not disturbed
582 test_h_gr32 word_dst, er1
583 test_gr_a5a5 2
584 test_gr_a5a5 3
585 test_gr_a5a5 4
586 test_gr_a5a5 5
587 test_gr_a5a5 6
588 test_gr_a5a5 7
589
590 ;; Now check the result of the move to memory.
591 cmp.w #0xdead, @word_dst
592 beq .Lnext14
593 fail
594 .Lnext14:
595 mov.w #0, @word_dst ; zero it again for the next use.
596
597 mov_w_imm16_to_predec: ; pre-decrement from register to mem
598 set_grs_a5a5 ; Fill all general regs with a fixed pattern
599 set_ccr_zero
600
601 ;; mov.w #xx:16, @-erd
602 mov.l #word_dst+2, er1
603 mov.w #0xdead:16, @-er1 ; Imm16, register pre-decr operands
604 ;;; .word 0x7974
605 ;;; .word 0xdead
606 ;;; .word 0xb100
607
608 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
609 test_neg_set
610 test_zero_clear
611 test_ovf_clear
612 test_carry_clear
613
614 test_gr_a5a5 0 ; Make sure other general regs not disturbed
615 test_h_gr32 word_dst, er1
616 test_gr_a5a5 2
617 test_gr_a5a5 3
618 test_gr_a5a5 4
619 test_gr_a5a5 5
620 test_gr_a5a5 6
621 test_gr_a5a5 7
622
623 ;; Now check the result of the move to memory.
624 cmp.w #0xdead, @word_dst
625 beq .Lnext15
626 fail
627 .Lnext15:
628 mov.w #0, @word_dst ; zero it again for the next use.
629
630 mov_w_imm16_to_disp2:
631 set_grs_a5a5 ; Fill all general regs with a fixed pattern
632 set_ccr_zero
633
634 ;; mov.w #xx:16, @(dd:2, erd)
635 mov.l #word_dst-6, er1
636 mov.w #0xdead:16, @(6:2, er1) ; Imm16, reg plus 2-bit disp. operand
637 ;;; .word 0x7974
638 ;;; .word 0xdead
639 ;;; .word 0x3100
640
641 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
642 test_neg_set
643 test_zero_clear
644 test_ovf_clear
645 test_carry_clear
646
647 test_gr_a5a5 0 ; Make sure other general regs not disturbed
648 test_h_gr32 word_dst-6, er1
649 test_gr_a5a5 2
650 test_gr_a5a5 3
651 test_gr_a5a5 4
652 test_gr_a5a5 5
653 test_gr_a5a5 6
654 test_gr_a5a5 7
655
656 ;; Now check the result of the move to memory.
657 cmp.w #0xdead, @word_dst
658 beq .Lnext16
659 fail
660 .Lnext16:
661 mov.w #0, @word_dst ; zero it again for the next use.
662
663 mov_w_imm16_to_disp16:
664 set_grs_a5a5 ; Fill all general regs with a fixed pattern
665 set_ccr_zero
666
667 ;; mov.w #xx:16, @(dd:16, erd)
668 mov.l #word_dst-4, er1
669 mov.w #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand
670 ;;; .word 0x7974
671 ;;; .word 0xdead
672 ;;; .word 0xc100
673 ;;; .word 0x0004
674
675 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
676 test_neg_set
677 test_zero_clear
678 test_ovf_clear
679 test_carry_clear
680
681 test_gr_a5a5 0 ; Make sure other general regs not disturbed
682 test_h_gr32 word_dst-4, er1
683 test_gr_a5a5 2
684 test_gr_a5a5 3
685 test_gr_a5a5 4
686 test_gr_a5a5 5
687 test_gr_a5a5 6
688 test_gr_a5a5 7
689
690 ;; Now check the result of the move to memory.
691 cmp.w #0xdead, @word_dst
692 beq .Lnext17
693 fail
694 .Lnext17:
695 mov.w #0, @word_dst ; zero it again for the next use.
696
697 mov_w_imm16_to_disp32:
698 set_grs_a5a5 ; Fill all general regs with a fixed pattern
699 set_ccr_zero
700
701 ;; mov.w #xx:16, @(dd:32, erd)
702 mov.l #word_dst-8, er1
703 mov.w #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand
704 ;;; .word 0x7974
705 ;;; .word 0xdead
706 ;;; .word 0xc900
707 ;;; .long 8
708
709 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
710 test_neg_set
711 test_zero_clear
712 test_ovf_clear
713 test_carry_clear
714
715 test_gr_a5a5 0 ; Make sure other general regs not disturbed
716 test_h_gr32 word_dst-8, er1
717 test_gr_a5a5 2
718 test_gr_a5a5 3
719 test_gr_a5a5 4
720 test_gr_a5a5 5
721 test_gr_a5a5 6
722 test_gr_a5a5 7
723
724 ;; Now check the result of the move to memory.
725 cmp.w #0xdead, @word_dst
726 beq .Lnext18
727 fail
728 .Lnext18:
729 mov.w #0, @word_dst ; zero it again for the next use.
730
731 mov_w_imm16_to_abs16:
732 set_grs_a5a5 ; Fill all general regs with a fixed pattern
733 set_ccr_zero
734
735 ;; mov.w #xx:16, @aa:16
736 mov.w #0xdead:16, @word_dst:16 ; 16-bit address-direct operand
737 ;;; .word 0x7974
738 ;;; .word 0xdead
739 ;;; .word 0x4000
740 ;;; .word @word_dst
741
742 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
743 test_neg_set
744 test_zero_clear
745 test_ovf_clear
746 test_carry_clear
747
748 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
749 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
750 test_gr_a5a5 2 ; to examine the destination memory).
751 test_gr_a5a5 3
752 test_gr_a5a5 4
753 test_gr_a5a5 5
754 test_gr_a5a5 6
755 test_gr_a5a5 7
756
757 ;; Now check the result of the move to memory.
758 cmp.w #0xdead, @word_dst
759 beq .Lnext19
760 fail
761 .Lnext19:
762 mov.w #0, @word_dst ; zero it again for the next use.
763
764 mov_w_imm16_to_abs32:
765 set_grs_a5a5 ; Fill all general regs with a fixed pattern
766 set_ccr_zero
767
768 ;; mov.w #xx:16, @aa:32
769 mov.w #0xdead:16, @word_dst:32 ; 32-bit address-direct operand
770 ;;; .word 0x7974
771 ;;; .word 0xdead
772 ;;; .word 0x4800
773 ;;; .long @word_dst
774
775 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
776 test_neg_set
777 test_zero_clear
778 test_ovf_clear
779 test_carry_clear
780
781 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
782 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
783 test_gr_a5a5 2 ; to examine the destination memory).
784 test_gr_a5a5 3
785 test_gr_a5a5 4
786 test_gr_a5a5 5
787 test_gr_a5a5 6
788 test_gr_a5a5 7
789
790 ;; Now check the result of the move to memory.
791 cmp.w #0xdead, @word_dst
792 beq .Lnext20
793 fail
794 .Lnext20:
795 mov.w #0, @word_dst ; zero it again for the next use.
796 .endif
797
798 ;;
799 ;; Move word from register source
800 ;;
801
802 mov_w_reg16_to_reg16:
803 set_grs_a5a5 ; Fill all general regs with a fixed pattern
804 set_ccr_zero
805
806 ;; mov.w ers, erd
807 mov.w #0x1234, r1
808 mov.w r1, r0 ; Register 16-bit operand
809 ;;; .word 0x0d10
810
811 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
812 test_neg_clear
813 test_zero_clear
814 test_ovf_clear
815 test_carry_clear
816 test_h_gr16 0x1234 r0
817 test_h_gr16 0x1234 r1 ; mov src unchanged
818 .if (sim_cpu)
819 test_h_gr32 0xa5a51234 er0
820 test_h_gr32 0xa5a51234 er1 ; mov src unchanged
821 .endif
822 test_gr_a5a5 2 ; Make sure other general regs not disturbed
823 test_gr_a5a5 3
824 test_gr_a5a5 4
825 test_gr_a5a5 5
826 test_gr_a5a5 6
827 test_gr_a5a5 7
828
829
830 mov_w_reg16_to_indirect:
831 set_grs_a5a5 ; Fill all general regs with a fixed pattern
832 set_ccr_zero
833
834 ;; mov.w ers, @erd
835 mov.l #word_dst, er1
836 mov.w r0, @er1 ; Register indirect operand
837 ;;; .word 0x6990
838
839 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
840 test_neg_set
841 test_zero_clear
842 test_ovf_clear
843 test_carry_clear
844
845 test_gr_a5a5 0 ; Make sure other general regs not disturbed
846 test_h_gr32 word_dst, er1
847 test_gr_a5a5 2
848 test_gr_a5a5 3
849 test_gr_a5a5 4
850 test_gr_a5a5 5
851 test_gr_a5a5 6
852 test_gr_a5a5 7
853
854 ;; Now check the result of the move to memory.
855 mov.w #0, r0
856 mov.w @word_dst, r0
857 cmp.w r2, r0
858 beq .Lnext44
859 fail
860 .Lnext44:
861 mov.w #0, r0
862 mov.w r0, @word_dst ; zero it again for the next use.
863
864 .if (sim_cpu == h8sx)
865 mov_w_reg16_to_postinc: ; post-increment from register to mem
866 set_grs_a5a5 ; Fill all general regs with a fixed pattern
867 set_ccr_zero
868
869 ;; mov.w ers, @erd+
870 mov.l #word_dst, er1
871 mov.w r0, @er1+ ; Register post-incr operand
872 ;;; .word 0x0153
873 ;;; .word 0x6d90
874
875 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
876 test_neg_set
877 test_zero_clear
878 test_ovf_clear
879 test_carry_clear
880
881 test_gr_a5a5 0 ; Make sure other general regs not disturbed
882 test_h_gr32 word_dst+2, er1
883 test_gr_a5a5 2
884 test_gr_a5a5 3
885 test_gr_a5a5 4
886 test_gr_a5a5 5
887 test_gr_a5a5 6
888 test_gr_a5a5 7
889
890 ;; Now check the result of the move to memory.
891 cmp.w r2, @word_dst
892 beq .Lnext49
893 fail
894 .Lnext49:
895 ;; special case same register
896 mov.l #word_dst, er0
897 mov.w r0, r1
898 inc.w #2,r1
899 mov.w r0, @er0+
900 mov.w @word_dst, r0
901 cmp.w r0, r1
902 beq .Lnext53
903 fail
904 .Lnext53:
905 mov.w #0, @word_dst ; zero it again for the next use.
906
907 mov_w_reg16_to_postdec: ; post-decrement from register to mem
908 set_grs_a5a5 ; Fill all general regs with a fixed pattern
909 set_ccr_zero
910
911 ;; mov.w ers, @erd-
912 mov.l #word_dst, er1
913 mov.w r0, @er1- ; Register post-decr operand
914 ;;; .word 0x0151
915 ;;; .word 0x6d90
916
917 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
918 test_neg_set
919 test_zero_clear
920 test_ovf_clear
921 test_carry_clear
922
923 test_gr_a5a5 0 ; Make sure other general regs not disturbed
924 test_h_gr32 word_dst-2, er1
925 test_gr_a5a5 2
926 test_gr_a5a5 3
927 test_gr_a5a5 4
928 test_gr_a5a5 5
929 test_gr_a5a5 6
930 test_gr_a5a5 7
931
932 ;; Now check the result of the move to memory.
933 cmp.w r2, @word_dst
934 beq .Lnext50
935 fail
936 .Lnext50:
937 ;; special case same register
938 mov.l #word_dst, er0
939 mov.w r0, r1
940 dec.w #2, r1
941 mov.w r0, @er0-
942 mov.w @word_dst, r0
943 cmp.w r0, r1
944 beq .Lnext54
945 fail
946 .Lnext54:
947 mov.w #0, @word_dst ; zero it again for the next use.
948
949 mov_w_reg16_to_preinc: ; pre-increment from register to mem
950 set_grs_a5a5 ; Fill all general regs with a fixed pattern
951 set_ccr_zero
952
953 ;; mov.w ers, @+erd
954 mov.l #word_dst-2, er1
955 mov.w r0, @+er1 ; Register pre-incr operand
956 ;;; .word 0x0152
957 ;;; .word 0x6d90
958
959 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
960 test_neg_set
961 test_zero_clear
962 test_ovf_clear
963 test_carry_clear
964
965 test_gr_a5a5 0 ; Make sure other general regs not disturbed
966 test_h_gr32 word_dst, er1
967 test_gr_a5a5 2
968 test_gr_a5a5 3
969 test_gr_a5a5 4
970 test_gr_a5a5 5
971 test_gr_a5a5 6
972 test_gr_a5a5 7
973
974 ;; Now check the result of the move to memory.
975 cmp.w r2, @word_dst
976 beq .Lnext51
977 fail
978 .Lnext51:
979 ;; special case same register
980 mov.l #word_dst-2, er0
981 mov.w r0, r1
982 inc.w #2, r1
983 mov.w r0, @+er0
984 mov.w @word_dst, r0
985 cmp.w r0, r1
986 beq .Lnext55
987 fail
988 .Lnext55:
989 mov.w #0, @word_dst ; zero it again for the next use.
990 .endif
991
992 mov_w_reg16_to_predec: ; pre-decrement from register to mem
993 set_grs_a5a5 ; Fill all general regs with a fixed pattern
994 set_ccr_zero
995
996 ;; mov.w ers, @-erd
997 mov.l #word_dst+2, er1
998 mov.w r0, @-er1 ; Register pre-decr operand
999 ;;; .word 0x6d90
1000
1001 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1002 test_neg_set
1003 test_zero_clear
1004 test_ovf_clear
1005 test_carry_clear
1006
1007 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1008 test_h_gr32 word_dst, er1
1009 test_gr_a5a5 2
1010 test_gr_a5a5 3
1011 test_gr_a5a5 4
1012 test_gr_a5a5 5
1013 test_gr_a5a5 6
1014 test_gr_a5a5 7
1015
1016 ;; Now check the result of the move to memory.
1017 mov.w #0, r0
1018 mov.w @word_dst, r0
1019 cmp.w r2, r0
1020 beq .Lnext48
1021 fail
1022 .Lnext48:
1023 ;; Special case in same register
1024 ;; CCR confirmation omitted
1025 mov.l #word_dst+2, er1
1026 mov.l er1, er0
1027 dec.w #2, r1
1028 mov.w r0, @-er0
1029 mov.w @word_dst, r0
1030 cmp.w r1, r0
1031 beq .Lnext47
1032 fail
1033 .Lnext47:
1034 mov.w #0, r0
1035 mov.w r0, @word_dst ; zero it again for the next use.
1036
1037 .if (sim_cpu == h8sx)
1038 mov_w_reg16_to_disp2:
1039 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1040 set_ccr_zero
1041
1042 ;; mov.w ers, @(dd:2, erd)
1043 mov.l #word_dst-6, er1
1044 mov.w r0, @(6:2, er1) ; Register plus 2-bit disp. operand
1045 ;;; .word 0x0153
1046 ;;; .word 0x6990
1047
1048 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1049 test_neg_set
1050 test_zero_clear
1051 test_ovf_clear
1052 test_carry_clear
1053
1054 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1055 test_h_gr32 word_dst-6, er1
1056 test_gr_a5a5 2
1057 test_gr_a5a5 3
1058 test_gr_a5a5 4
1059 test_gr_a5a5 5
1060 test_gr_a5a5 6
1061 test_gr_a5a5 7
1062
1063 ;; Now check the result of the move to memory.
1064 cmp.w r2, @word_dst
1065 beq .Lnext52
1066 fail
1067 .Lnext52:
1068 mov.w #0, @word_dst ; zero it again for the next use.
1069 .endif
1070
1071 mov_w_reg16_to_disp16:
1072 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1073 set_ccr_zero
1074
1075 ;; mov.w ers, @(dd:16, erd)
1076 mov.l #word_dst-4, er1
1077 mov.w r0, @(4:16, er1) ; Register plus 16-bit disp. operand
1078 ;;; .word 0x6f90
1079 ;;; .word 0x0004
1080
1081 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1082 test_neg_set
1083 test_zero_clear
1084 test_ovf_clear
1085 test_carry_clear
1086
1087 test_h_gr32 word_dst-4, er1
1088 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1089 test_gr_a5a5 2
1090 test_gr_a5a5 3
1091 test_gr_a5a5 4
1092 test_gr_a5a5 5
1093 test_gr_a5a5 6
1094 test_gr_a5a5 7
1095
1096 ;; Now check the result of the move to memory.
1097 mov.w #0, r0
1098 mov.w @word_dst, r0
1099 cmp.w r2, r0
1100 beq .Lnext45
1101 fail
1102 .Lnext45:
1103 mov.w #0, r0
1104 mov.w r0, @word_dst ; zero it again for the next use.
1105
1106 mov_w_reg16_to_disp32:
1107 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1108 set_ccr_zero
1109
1110 ;; mov.w ers, @(dd:32, erd)
1111 mov.l #word_dst-8, er1
1112 mov.w r0, @(8:32, er1) ; Register plus 32-bit disp. operand
1113 ;;; .word 0x7810
1114 ;;; .word 0x6ba0
1115 ;;; .long 8
1116
1117 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1118 test_neg_set
1119 test_zero_clear
1120 test_ovf_clear
1121 test_carry_clear
1122
1123 test_h_gr32 word_dst-8, er1
1124 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1125 test_gr_a5a5 2
1126 test_gr_a5a5 3
1127 test_gr_a5a5 4
1128 test_gr_a5a5 5
1129 test_gr_a5a5 6
1130 test_gr_a5a5 7
1131
1132 ;; Now check the result of the move to memory.
1133 mov.w #0, r0
1134 mov.w @word_dst, r0
1135 cmp.w r2, r0
1136 beq .Lnext46
1137 fail
1138 .Lnext46:
1139 mov.w #0, r0
1140 mov.w r0, @word_dst ; zero it again for the next use.
1141
1142 mov_w_reg16_to_abs16:
1143 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1144 set_ccr_zero
1145
1146 ;; mov.w ers, @aa:16
1147 mov.w r0, @word_dst:16 ; 16-bit address-direct operand
1148 ;;; .word 0x6b80
1149 ;;; .word @word_dst
1150
1151 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1152 test_neg_set
1153 test_zero_clear
1154 test_ovf_clear
1155 test_carry_clear
1156
1157 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
1158 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
1159 test_gr_a5a5 2 ; to examine the destination memory).
1160 test_gr_a5a5 3
1161 test_gr_a5a5 4
1162 test_gr_a5a5 5
1163 test_gr_a5a5 6
1164 test_gr_a5a5 7
1165
1166 ;; Now check the result of the move to memory.
1167 mov.w #0, r0
1168 mov.w @word_dst, r0
1169 cmp.w r0, r1
1170 beq .Lnext41
1171 fail
1172 .Lnext41:
1173 mov.w #0, r0
1174 mov.w r0, @word_dst ; zero it again for the next use.
1175
1176 mov_w_reg16_to_abs32:
1177 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1178 set_ccr_zero
1179
1180 ;; mov.w ers, @aa:32
1181 mov.w r0, @word_dst:32 ; 32-bit address-direct operand
1182 ;;; .word 0x6ba0
1183 ;;; .long @word_dst
1184
1185 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0
1186 test_neg_set
1187 test_zero_clear
1188 test_ovf_clear
1189 test_carry_clear
1190
1191 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed
1192 test_gr_a5a5 1 ; (first, because on h8/300 we must use one
1193 test_gr_a5a5 2 ; to examine the destination memory).
1194 test_gr_a5a5 3
1195 test_gr_a5a5 4
1196 test_gr_a5a5 5
1197 test_gr_a5a5 6
1198 test_gr_a5a5 7
1199
1200 ;; Now check the result of the move to memory.
1201 mov.w #0, r0
1202 mov.w @word_dst, r0
1203 cmp.w r0, r1
1204 beq .Lnext42
1205 fail
1206 .Lnext42:
1207 mov.w #0, r0
1208 mov.w r0, @word_dst ; zero it again for the next use.
1209
1210 ;;
1211 ;; Move word to register destination.
1212 ;;
1213
1214 mov_w_indirect_to_reg16:
1215 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1216 set_ccr_zero
1217
1218 ;; mov.w @ers, rd
1219 mov.l #word_src, er1
1220 mov.w @er1, r0 ; Register indirect operand
1221 ;;; .word 0x6910
1222
1223 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1224 test_neg_clear
1225 test_zero_clear
1226 test_ovf_clear
1227 test_carry_clear
1228
1229 test_h_gr32 0xa5a57777 er0
1230
1231 test_h_gr32 word_src, er1
1232 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1233 test_gr_a5a5 3
1234 test_gr_a5a5 4
1235 test_gr_a5a5 5
1236 test_gr_a5a5 6
1237 test_gr_a5a5 7
1238
1239 mov_w_postinc_to_reg16: ; post-increment from mem to register
1240 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1241 set_ccr_zero
1242
1243 ;; mov.w @ers+, rd
1244
1245 mov.l #word_src, er1
1246 mov.w @er1+, r0 ; Register post-incr operand
1247 ;;; .word 0x6d10
1248
1249 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1250 test_neg_clear
1251 test_zero_clear
1252 test_ovf_clear
1253 test_carry_clear
1254
1255 test_h_gr32 0xa5a57777 er0
1256
1257 test_h_gr32 word_src+2, er1
1258 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1259 test_gr_a5a5 3
1260 test_gr_a5a5 4
1261 test_gr_a5a5 5
1262 test_gr_a5a5 6
1263 test_gr_a5a5 7
1264
1265 .if (sim_cpu == h8sx)
1266 mov_w_postdec_to_reg16: ; post-decrement from mem to register
1267 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1268 set_ccr_zero
1269
1270 ;; mov.w @ers-, rd
1271
1272 mov.l #word_src, er1
1273 mov.w @er1-, r0 ; Register post-decr operand
1274 ;;; .word 0x0152
1275 ;;; .word 0x6d10
1276
1277 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1278 test_neg_clear
1279 test_zero_clear
1280 test_ovf_clear
1281 test_carry_clear
1282
1283 test_h_gr32 0xa5a57777 er0
1284
1285 test_h_gr32 word_src-2, er1
1286 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1287 test_gr_a5a5 3
1288 test_gr_a5a5 4
1289 test_gr_a5a5 5
1290 test_gr_a5a5 6
1291 test_gr_a5a5 7
1292
1293 mov_w_preinc_to_reg16: ; pre-increment from mem to register
1294 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1295 set_ccr_zero
1296
1297 ;; mov.w @+ers, rd
1298
1299 mov.l #word_src-2, er1
1300 mov.w @+er1, r0 ; Register pre-incr operand
1301 ;;; .word 0x0151
1302 ;;; .word 0x6d10
1303
1304 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1305 test_neg_clear
1306 test_zero_clear
1307 test_ovf_clear
1308 test_carry_clear
1309
1310 test_h_gr32 0xa5a57777 er0
1311
1312 test_h_gr32 word_src, er1
1313 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1314 test_gr_a5a5 3
1315 test_gr_a5a5 4
1316 test_gr_a5a5 5
1317 test_gr_a5a5 6
1318 test_gr_a5a5 7
1319
1320 mov_w_predec_to_reg16: ; pre-decrement from mem to register
1321 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1322 set_ccr_zero
1323
1324 ;; mov.w @-ers, rd
1325
1326 mov.l #word_src+2, er1
1327 mov.w @-er1, r0 ; Register pre-decr operand
1328 ;;; .word 0x0153
1329 ;;; .word 0x6d10
1330
1331 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1332 test_neg_clear
1333 test_zero_clear
1334 test_ovf_clear
1335 test_carry_clear
1336
1337 test_h_gr32 0xa5a57777 er0
1338
1339 test_h_gr32 word_src, er1
1340 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1341 test_gr_a5a5 3
1342 test_gr_a5a5 4
1343 test_gr_a5a5 5
1344 test_gr_a5a5 6
1345 test_gr_a5a5 7
1346
1347
1348 mov_w_disp2_to_reg16:
1349 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1350 set_ccr_zero
1351
1352 ;; mov.w @(dd:2, ers), rd
1353 mov.l #word_src-2, er1
1354 mov.w @(2:2, er1), r0 ; Register plus 2-bit disp. operand
1355 ;;; .word 0x0151
1356 ;;; .word 0x6910
1357
1358 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1359 test_neg_clear
1360 test_zero_clear
1361 test_ovf_clear
1362 test_carry_clear
1363
1364 test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
1365
1366 test_h_gr32 word_src-2, er1
1367 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1368 test_gr_a5a5 3
1369 test_gr_a5a5 4
1370 test_gr_a5a5 5
1371 test_gr_a5a5 6
1372 test_gr_a5a5 7
1373 .endif
1374
1375 mov_w_disp16_to_reg16:
1376 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1377 set_ccr_zero
1378
1379 ;; mov.w @(dd:16, ers), rd
1380 mov.l #word_src+0x1234, er1
1381 mov.w @(-0x1234:16, er1), r0 ; Register plus 16-bit disp. operand
1382 ;;; .word 0x6f10
1383 ;;; .word -0x1234
1384
1385 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1386 test_neg_clear
1387 test_zero_clear
1388 test_ovf_clear
1389 test_carry_clear
1390
1391 test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
1392
1393 test_h_gr32 word_src+0x1234, er1
1394 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1395 test_gr_a5a5 3
1396 test_gr_a5a5 4
1397 test_gr_a5a5 5
1398 test_gr_a5a5 6
1399 test_gr_a5a5 7
1400
1401 mov_w_disp32_to_reg16:
1402 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1403 set_ccr_zero
1404
1405 ;; mov.w @(dd:32, ers), rd
1406 mov.l #word_src+65536, er1
1407 mov.w @(-65536:32, er1), r0 ; Register plus 32-bit disp. operand
1408 ;;; .word 0x7810
1409 ;;; .word 0x6b20
1410 ;;; .long -65536
1411
1412 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1413 test_neg_clear
1414 test_zero_clear
1415 test_ovf_clear
1416 test_carry_clear
1417
1418 test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777
1419
1420 test_h_gr32 word_src+65536, er1
1421 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1422 test_gr_a5a5 3
1423 test_gr_a5a5 4
1424 test_gr_a5a5 5
1425 test_gr_a5a5 6
1426 test_gr_a5a5 7
1427
1428 mov_w_abs16_to_reg16:
1429 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1430 set_ccr_zero
1431
1432 ;; mov.w @aa:16, rd
1433 mov.w @word_src:16, r0 ; 16-bit address-direct operand
1434 ;;; .word 0x6b00
1435 ;;; .word @word_src
1436
1437 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1438 test_neg_clear
1439 test_zero_clear
1440 test_ovf_clear
1441 test_carry_clear
1442
1443 test_h_gr32 0xa5a57777 er0
1444
1445 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1446 test_gr_a5a5 2
1447 test_gr_a5a5 3
1448 test_gr_a5a5 4
1449 test_gr_a5a5 5
1450 test_gr_a5a5 6
1451 test_gr_a5a5 7
1452
1453 mov_w_abs32_to_reg16:
1454 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1455 set_ccr_zero
1456
1457 ;; mov.w @aa:32, rd
1458 mov.w @word_src:32, r0 ; 32-bit address-direct operand
1459 ;;; .word 0x6b20
1460 ;;; .long @word_src
1461
1462 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1463 test_neg_clear
1464 test_zero_clear
1465 test_ovf_clear
1466 test_carry_clear
1467
1468 test_h_gr32 0xa5a57777 er0
1469
1470 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1471 test_gr_a5a5 2
1472 test_gr_a5a5 3
1473 test_gr_a5a5 4
1474 test_gr_a5a5 5
1475 test_gr_a5a5 6
1476 test_gr_a5a5 7
1477
1478 .if (sim_cpu == h8sx)
1479
1480 ;;
1481 ;; Move word from memory to memory
1482 ;;
1483
1484 mov_w_indirect_to_indirect: ; reg indirect, memory to memory
1485 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1486 set_ccr_zero
1487
1488 ;; mov.w @ers, @erd
1489
1490 mov.l #word_src, er1
1491 mov.l #word_dst, er0
1492 mov.w @er1, @er0
1493 ;;; .word 0x0158
1494 ;;; .word 0x0100
1495
1496 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1497 test_neg_clear
1498 test_zero_clear
1499 test_ovf_clear
1500 test_carry_clear
1501
1502 ;; Verify the affected registers.
1503
1504 test_h_gr32 word_dst er0
1505 test_h_gr32 word_src er1
1506 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1507 test_gr_a5a5 3
1508 test_gr_a5a5 4
1509 test_gr_a5a5 5
1510 test_gr_a5a5 6
1511 test_gr_a5a5 7
1512
1513 ;; Now check the result of the move to memory.
1514 cmp.w @word_src, @word_dst
1515 beq .Lnext56
1516 fail
1517 .Lnext56:
1518 ;; Now clear the destination location, and verify that.
1519 mov.w #0, @word_dst
1520 cmp.w @word_src, @word_dst
1521 bne .Lnext57
1522 fail
1523 .Lnext57: ; OK, pass on.
1524
1525 mov_w_postinc_to_postinc: ; reg post-increment, memory to memory
1526 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1527 set_ccr_zero
1528
1529 ;; mov.w @ers+, @erd+
1530
1531 mov.l #word_src, er1
1532 mov.l #word_dst, er0
1533 mov.w @er1+, @er0+
1534 ;;; .word 0x0158
1535 ;;; .word 0x8180
1536
1537 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1538 test_neg_clear
1539 test_zero_clear
1540 test_ovf_clear
1541 test_carry_clear
1542
1543 ;; Verify the affected registers.
1544
1545 test_h_gr32 word_dst+2 er0
1546 test_h_gr32 word_src+2 er1
1547 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1548 test_gr_a5a5 3
1549 test_gr_a5a5 4
1550 test_gr_a5a5 5
1551 test_gr_a5a5 6
1552 test_gr_a5a5 7
1553
1554 ;; Now check the result of the move to memory.
1555 cmp.w @word_src, @word_dst
1556 beq .Lnext65
1557 fail
1558 .Lnext65:
1559 ;; Now clear the destination location, and verify that.
1560 mov.w #0, @word_dst
1561 cmp.w @word_src, @word_dst
1562 bne .Lnext66
1563 fail
1564 .Lnext66: ; OK, pass on.
1565 ;; special case same register
1566 mov.l #word_src, er0
1567 mov.w @er0+, @er0+ ; copying word_src to word_dst
1568 test_h_gr32 word_src+4 er0
1569 cmp.w @word_src, @word_dst
1570 beq .Lnext67
1571 fail
1572 .Lnext67:
1573 ;; Now clear the destination location, and verify that.
1574 mov.w #0, @word_dst
1575 cmp.b @word_src, @word_dst
1576 bne .Lnext68
1577 fail
1578 .Lnext68:
1579
1580 mov_w_postdec_to_postdec: ; reg post-decrement, memory to memory
1581 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1582 set_ccr_zero
1583
1584 ;; mov.w @ers-, @erd-
1585
1586 mov.l #word_src, er1
1587 mov.l #word_dst, er0
1588 mov.w @er1-, @er0-
1589 ;;; .word 0x0158
1590 ;;; .word 0xa1a0
1591
1592 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1593 test_neg_clear
1594 test_zero_clear
1595 test_ovf_clear
1596 test_carry_clear
1597
1598 ;; Verify the affected registers.
1599
1600 test_h_gr32 word_dst-2 er0
1601 test_h_gr32 word_src-2 er1
1602 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1603 test_gr_a5a5 3
1604 test_gr_a5a5 4
1605 test_gr_a5a5 5
1606 test_gr_a5a5 6
1607 test_gr_a5a5 7
1608
1609 ;; Now check the result of the move to memory.
1610 cmp.w @word_src, @word_dst
1611 beq .Lnext75
1612 fail
1613 .Lnext75:
1614 ;; Now clear the destination location, and verify that.
1615 mov.w #0, @word_dst
1616 cmp.w @word_src, @word_dst
1617 bne .Lnext76
1618 fail
1619 .Lnext76: ; OK, pass on.
1620 ;; special case same register
1621 mov.l #word_src, er0
1622 mov.w @er0-, @er0- ; copying word_src to word_dst_dec
1623 test_h_gr32 word_src-4 er0
1624 cmp.w @word_src, @word_dst_dec
1625 beq .Lnext77
1626 fail
1627 .Lnext77:
1628 ;; Now clear the destination location, and verify that.
1629 mov.w #0, @word_dst_dec
1630 cmp.w @word_src, @word_dst_dec
1631 bne .Lnext78
1632 fail
1633 .Lnext78:
1634
1635 mov_w_preinc_to_preinc: ; reg pre-increment, memory to memory
1636 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1637 set_ccr_zero
1638
1639 ;; mov.w @+ers, @+erd
1640
1641 mov.l #word_src-2, er1
1642 mov.l #word_dst-2, er0
1643 mov.w @+er1, @+er0
1644 ;;; .word 0x0158
1645 ;;; .word 0x9190
1646
1647 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1648 test_neg_clear
1649 test_zero_clear
1650 test_ovf_clear
1651 test_carry_clear
1652
1653 ;; Verify the affected registers.
1654
1655 test_h_gr32 word_dst er0
1656 test_h_gr32 word_src er1
1657 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1658 test_gr_a5a5 3
1659 test_gr_a5a5 4
1660 test_gr_a5a5 5
1661 test_gr_a5a5 6
1662 test_gr_a5a5 7
1663
1664 ;; Now check the result of the move to memory.
1665 cmp.w @word_src, @word_dst
1666 beq .Lnext85
1667 fail
1668 .Lnext85:
1669 ;; Now clear the destination location, and verify that.
1670 mov.w #0, @word_dst
1671 cmp.w @word_src, @word_dst
1672 bne .Lnext86
1673 fail
1674 .Lnext86: ; OK, pass on.
1675 ;; special case same register
1676 mov.l #word_src-2, er0
1677 mov.w @+er0, @+er0 ; copying word_src to word_dst
1678 test_h_gr32 word_src+2 er0
1679 cmp.w @word_src, @word_dst
1680 beq .Lnext87
1681 fail
1682 .Lnext87:
1683 ;; Now clear the destination location, and verify that.
1684 mov.w #0, @word_dst
1685 cmp.w @word_src, @word_dst
1686 bne .Lnext88
1687 fail
1688 .Lnext88:
1689
1690 mov_w_predec_to_predec: ; reg pre-decrement, memory to memory
1691 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1692 set_ccr_zero
1693
1694 ;; mov.w @-ers, @-erd
1695
1696 mov.l #word_src+2, er1
1697 mov.l #word_dst+2, er0
1698 mov.w @-er1, @-er0
1699 ;;; .word 0x0158
1700 ;;; .word 0xb1b0
1701
1702 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1703 test_neg_clear
1704 test_zero_clear
1705 test_ovf_clear
1706 test_carry_clear
1707
1708 ;; Verify the affected registers.
1709
1710 test_h_gr32 word_dst er0
1711 test_h_gr32 word_src er1
1712 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1713 test_gr_a5a5 3
1714 test_gr_a5a5 4
1715 test_gr_a5a5 5
1716 test_gr_a5a5 6
1717 test_gr_a5a5 7
1718
1719 ;; Now check the result of the move to memory.
1720 cmp.w @word_src, @word_dst
1721 beq .Lnext95
1722 fail
1723 .Lnext95:
1724 ;; Now clear the destination location, and verify that.
1725 mov.w #0, @word_dst
1726 cmp.w @word_src, @word_dst
1727 bne .Lnext96
1728 fail
1729 .Lnext96: ; OK, pass on.
1730 ;; special case same register
1731 mov.l #word_src+2, er0
1732 mov.w @-er0, @-er0 ; copying word_src to word_dst_dec
1733 test_h_gr32 word_src-2 er0
1734 cmp.w @word_src, @word_dst_dec
1735 beq .Lnext97
1736 fail
1737 .Lnext97:
1738 ;; Now clear the destination location, and verify that.
1739 mov.w #0, @word_dst_dec
1740 cmp.w @word_src, @word_dst_dec
1741 bne .Lnext98
1742 fail
1743 .Lnext98:
1744
1745 mov_w_disp2_to_disp2: ; reg 2-bit disp, memory to memory
1746 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1747 set_ccr_zero
1748
1749 ;; mov.w @(dd:2, ers), @(dd:2, erd)
1750
1751 mov.l #word_src-2, er1
1752 mov.l #word_dst-4, er0
1753 mov.w @(2:2, er1), @(4:2, er0)
1754 ;;; .word 0x0158
1755 ;;; .word 0x1120
1756
1757 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1758 test_neg_clear
1759 test_zero_clear
1760 test_ovf_clear
1761 test_carry_clear
1762
1763 ;; Verify the affected registers.
1764
1765 test_h_gr32 word_dst-4 er0
1766 test_h_gr32 word_src-2 er1
1767 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1768 test_gr_a5a5 3
1769 test_gr_a5a5 4
1770 test_gr_a5a5 5
1771 test_gr_a5a5 6
1772 test_gr_a5a5 7
1773
1774 ;; Now check the result of the move to memory.
1775 cmp.w @word_src, @word_dst
1776 beq .Lnext105
1777 fail
1778 .Lnext105:
1779 ;; Now clear the destination location, and verify that.
1780 mov.w #0, @word_dst
1781 cmp.w @word_src, @word_dst
1782 bne .Lnext106
1783 fail
1784 .Lnext106: ; OK, pass on.
1785
1786 mov_w_disp16_to_disp16: ; reg 16-bit disp, memory to memory
1787 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1788 set_ccr_zero
1789
1790 ;; mov.w @(dd:16, ers), @(dd:16, erd)
1791
1792 mov.l #word_src-1, er1
1793 mov.l #word_dst-2, er0
1794 mov.w @(1:16, er1), @(2:16, er0)
1795 ;;; .word 0x0158
1796 ;;; .word 0xc1c0
1797 ;;; .word 0x0001
1798 ;;; .word 0x0002
1799
1800 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1801 test_neg_clear
1802 test_zero_clear
1803 test_ovf_clear
1804 test_carry_clear
1805
1806 ;; Verify the affected registers.
1807
1808 test_h_gr32 word_dst-2 er0
1809 test_h_gr32 word_src-1 er1
1810 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1811 test_gr_a5a5 3
1812 test_gr_a5a5 4
1813 test_gr_a5a5 5
1814 test_gr_a5a5 6
1815 test_gr_a5a5 7
1816
1817 ;; Now check the result of the move to memory.
1818 cmp.w @word_src, @word_dst
1819 beq .Lnext115
1820 fail
1821 .Lnext115:
1822 ;; Now clear the destination location, and verify that.
1823 mov.w #0, @word_dst
1824 cmp.w @word_src, @word_dst
1825 bne .Lnext116
1826 fail
1827 .Lnext116: ; OK, pass on.
1828
1829 mov_w_disp32_to_disp32: ; reg 32-bit disp, memory to memory
1830 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1831 set_ccr_zero
1832
1833 ;; mov.w @(dd:32, ers), @(dd:32, erd)
1834
1835 mov.l #word_src-1, er1
1836 mov.l #word_dst-2, er0
1837 mov.w @(1:32, er1), @(2:32, er0)
1838 ;;; .word 0x0158
1839 ;;; .word 0xc9c8
1840 ;;; .long 1
1841 ;;; .long 2
1842
1843 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1844 test_neg_clear
1845 test_zero_clear
1846 test_ovf_clear
1847 test_carry_clear
1848
1849 ;; Verify the affected registers.
1850
1851 test_h_gr32 word_dst-2 er0
1852 test_h_gr32 word_src-1 er1
1853 test_gr_a5a5 2 ; Make sure other general regs not disturbed
1854 test_gr_a5a5 3
1855 test_gr_a5a5 4
1856 test_gr_a5a5 5
1857 test_gr_a5a5 6
1858 test_gr_a5a5 7
1859
1860 ;; Now check the result of the move to memory.
1861 cmp.w @word_src, @word_dst
1862 beq .Lnext125
1863 fail
1864 .Lnext125:
1865 ;; Now clear the destination location, and verify that.
1866 mov.w #0, @word_dst
1867 cmp.w @word_src, @word_dst
1868 bne .Lnext126
1869 fail
1870 .Lnext126: ; OK, pass on.
1871
1872 mov_w_abs16_to_abs16: ; 16-bit absolute addr, memory to memory
1873 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1874 set_ccr_zero
1875
1876 ;; mov.w @aa:16, @aa:16
1877
1878 mov.w @word_src:16, @word_dst:16
1879 ;;; .word 0x0158
1880 ;;; .word 0x4040
1881 ;;; .word @word_src
1882 ;;; .word @word_dst
1883
1884 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1885 test_neg_clear
1886 test_zero_clear
1887 test_ovf_clear
1888 test_carry_clear
1889
1890
1891 test_gr_a5a5 0 ; Make sure *NO* general registers are changed
1892 test_gr_a5a5 1
1893 test_gr_a5a5 2
1894 test_gr_a5a5 3
1895 test_gr_a5a5 4
1896 test_gr_a5a5 5
1897 test_gr_a5a5 6
1898 test_gr_a5a5 7
1899
1900 ;; Now check the result of the move to memory.
1901 cmp.w @word_src, @word_dst
1902 beq .Lnext135
1903 fail
1904 .Lnext135:
1905 ;; Now clear the destination location, and verify that.
1906 mov.w #0, @word_dst
1907 cmp.w @word_src, @word_dst
1908 bne .Lnext136
1909 fail
1910 .Lnext136: ; OK, pass on.
1911
1912 mov_w_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
1913 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1914 set_ccr_zero
1915
1916 ;; mov.w @aa:32, @aa:32
1917
1918 mov.w @word_src:32, @word_dst:32
1919 ;;; .word 0x0158
1920 ;;; .word 0x4848
1921 ;;; .long @word_src
1922 ;;; .long @word_dst
1923
1924 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0
1925 test_neg_clear
1926 test_zero_clear
1927 test_ovf_clear
1928 test_carry_clear
1929
1930 test_gr_a5a5 0 ; Make sure *NO* general registers are changed
1931 test_gr_a5a5 1
1932 test_gr_a5a5 2
1933 test_gr_a5a5 3
1934 test_gr_a5a5 4
1935 test_gr_a5a5 5
1936 test_gr_a5a5 6
1937 test_gr_a5a5 7
1938
1939 ;; Now check the result of the move to memory.
1940 cmp.w @word_src, @word_dst
1941 beq .Lnext145
1942 fail
1943 .Lnext145:
1944 ;; Now clear the destination location, and verify that.
1945 mov.w #0, @word_dst
1946 cmp.w @word_src, @word_dst
1947 bne .Lnext146
1948 fail
1949 .Lnext146: ; OK, pass on.
1950
1951
1952 .endif
1953
1954 pass
1955
1956 exit 0