sim/testsuite/h8300/rotl.s

   1 # Hitachi H8 testcase 'rotl'
   2 # mach(): h8300s h8sx
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12
  13         start
  14
  15         .data
  16 byte_dest:      .byte   0xa5
  17         .align 2
  18 word_dest:      .word   0xa5a5
  19         .align 4
  20 long_dest:      .long   0xa5a5a5a5
  21
  22         .text
  23
  24 rotl_b_reg8_1:
  25         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  26         set_ccr_zero
  27
  28         rotl.b  r0l             ; shift left arithmetic by one
  29
  30         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
  31         test_zero_clear
  32         test_ovf_clear
  33         test_neg_clear
  34         test_h_gr16 0xa54b r0   ; 1010 0101 -> 0100 1011
  35 .if (sim_cpu)
  36         test_h_gr32 0xa5a5a54b er0
  37 .endif
  38         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  39         test_gr_a5a5 2
  40         test_gr_a5a5 3
  41         test_gr_a5a5 4
  42         test_gr_a5a5 5
  43         test_gr_a5a5 6
  44         test_gr_a5a5 7
  45
  46 .if (sim_cpu == h8sx)
  47 rotl_b_ind_1:
  48         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  49         set_ccr_zero
  50
  51         mov     #byte_dest, er0
  52         rotl.b  @er0    ; shift right arithmetic by one, indirect
  53
  54         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
  55         test_zero_clear
  56         test_ovf_clear
  57         test_neg_clear
  58
  59         test_h_gr32  byte_dest er0
  60         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  61         test_gr_a5a5 2
  62         test_gr_a5a5 3
  63         test_gr_a5a5 4
  64         test_gr_a5a5 5
  65         test_gr_a5a5 6
  66         test_gr_a5a5 7
  67         ; 1010 0101 -> 0100 1011
  68         cmp.b   #0x4b, @byte_dest
  69         beq     .Lbind1
  70         fail
  71 .Lbind1:
  72         mov.b   #0xa5, @byte_dest
  73
  74 rotl_b_indexb16_1:
  75         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  76         set_ccr_zero
  77
  78         mov.b   #5, r0l
  79         rotl.b  @(byte_dest-5:16, r0.b) ; indexed byte/byte
  80
  81         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
  82         test_zero_clear
  83         test_ovf_clear
  84         test_neg_clear
  85
  86         test_h_gr32  0xa5a5a505 er0
  87         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  88         test_gr_a5a5 2
  89         test_gr_a5a5 3
  90         test_gr_a5a5 4
  91         test_gr_a5a5 5
  92         test_gr_a5a5 6
  93         test_gr_a5a5 7
  94         ; 1010 0101 -> 0100 1011
  95         cmp.b   #0x4b, @byte_dest
  96         beq     .Lbindexb161
  97         fail
  98 .Lbindexb161:
  99         mov.b   #0xa5, @byte_dest
 100
 101 rotl_b_indexw16_1:
 102         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 103         set_ccr_zero
 104
 105         mov.w   #256, r0
 106         rotl.b  @(byte_dest-256:16, r0.w)       ; indexed byte/word
 107
 108         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 109         test_zero_clear
 110         test_ovf_clear
 111         test_neg_clear
 112
 113         test_h_gr32  0xa5a50100 er0
 114         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 115         test_gr_a5a5 2
 116         test_gr_a5a5 3
 117         test_gr_a5a5 4
 118         test_gr_a5a5 5
 119         test_gr_a5a5 6
 120         test_gr_a5a5 7
 121         ; 1010 0101 -> 0100 1011
 122         cmp.b   #0x4b, @byte_dest
 123         beq     .Lbindexw161
 124         fail
 125 .Lbindexw161:
 126         mov.b   #0xa5, @byte_dest
 127
 128 rotl_b_indexl16_1:
 129         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 130         set_ccr_zero
 131
 132         mov.l   #0xffffffff, er0
 133         rotl.b  @(byte_dest+1:16, er0.l)        ; indexed byte/long
 134
 135         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 136         test_zero_clear
 137         test_ovf_clear
 138         test_neg_clear
 139
 140         test_h_gr32  0xffffffff er0
 141         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 142         test_gr_a5a5 2
 143         test_gr_a5a5 3
 144         test_gr_a5a5 4
 145         test_gr_a5a5 5
 146         test_gr_a5a5 6
 147         test_gr_a5a5 7
 148         ; 1010 0101 -> 0100 1011
 149         cmp.b   #0x4b, @byte_dest
 150         beq     .Lbindexl161
 151         fail
 152 .Lbindexl161:
 153         mov.b   #0xa5, @byte_dest
 154
 155 rotl_b_indexb32_1:
 156         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 157         set_ccr_zero
 158
 159         mov.b   #5, r1l
 160         rotl.b  @(byte_dest-5:32, r1.b) ; indexed byte/byte
 161
 162         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 163         test_zero_clear
 164         test_ovf_clear
 165         test_neg_clear
 166
 167         test_h_gr32  0xa5a5a505 er1
 168         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 169         test_gr_a5a5 2
 170         test_gr_a5a5 3
 171         test_gr_a5a5 4
 172         test_gr_a5a5 5
 173         test_gr_a5a5 6
 174         test_gr_a5a5 7
 175         ; 1010 0101 -> 0100 1011
 176         cmp.b   #0x4b, @byte_dest
 177         beq     .Lbindexb321
 178         fail
 179 .Lbindexb321:
 180         mov.b   #0xa5, @byte_dest
 181
 182 rotl_b_indexw32_1:
 183         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 184         set_ccr_zero
 185
 186         mov.w   #256, r1
 187         rotl.b  @(byte_dest-256:32, r1.w)       ; indexed byte/word
 188
 189         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 190         test_zero_clear
 191         test_ovf_clear
 192         test_neg_clear
 193
 194         test_h_gr32  0xa5a50100 er1
 195         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 196         test_gr_a5a5 2
 197         test_gr_a5a5 3
 198         test_gr_a5a5 4
 199         test_gr_a5a5 5
 200         test_gr_a5a5 6
 201         test_gr_a5a5 7
 202         ; 1010 0101 -> 0100 1011
 203         cmp.b   #0x4b, @byte_dest
 204         beq     .Lbindexw321
 205         fail
 206 .Lbindexw321:
 207         mov.b   #0xa5, @byte_dest
 208
 209 rotl_b_indexl32_1:
 210         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 211         set_ccr_zero
 212
 213         mov.l   #0xffffffff, er1
 214         rotl.b  @(byte_dest+1:32, er1.l)        ; indexed byte/long
 215
 216         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 217         test_zero_clear
 218         test_ovf_clear
 219         test_neg_clear
 220
 221         test_h_gr32  0xffffffff er1
 222         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 223         test_gr_a5a5 2
 224         test_gr_a5a5 3
 225         test_gr_a5a5 4
 226         test_gr_a5a5 5
 227         test_gr_a5a5 6
 228         test_gr_a5a5 7
 229         ; 1010 0101 -> 0100 1011
 230         cmp.b   #0x4b, @byte_dest
 231         beq     .Lbindexl321
 232         fail
 233 .Lbindexl321:
 234         mov.b   #0xa5, @byte_dest
 235
 236 .endif
 237
 238 rotl_b_reg8_2:
 239         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 240         set_ccr_zero
 241
 242         rotl.b  #2, r0l         ; shift left arithmetic by two
 243
 244         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 245         test_zero_clear
 246         test_ovf_clear
 247         test_neg_set
 248
 249         test_h_gr16 0xa596 r0   ; 1010 0101 -> 1001 0110
 250 .if (sim_cpu)
 251         test_h_gr32 0xa5a5a596 er0
 252 .endif
 253         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 254         test_gr_a5a5 2
 255         test_gr_a5a5 3
 256         test_gr_a5a5 4
 257         test_gr_a5a5 5
 258         test_gr_a5a5 6
 259         test_gr_a5a5 7
 260
 261 .if (sim_cpu == h8sx)
 262 rotl_b_ind_2:
 263         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 264         set_ccr_zero
 265
 266         mov     #byte_dest, er0
 267         rotl.b  #2, @er0        ; shift right arithmetic by one, indirect
 268
 269         test_carry_clear        ; H=0 N=1 Z=0 C=0
 270         test_zero_clear
 271         test_ovf_clear
 272         test_neg_set
 273
 274         test_h_gr32  byte_dest er0
 275         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 276         test_gr_a5a5 2
 277         test_gr_a5a5 3
 278         test_gr_a5a5 4
 279         test_gr_a5a5 5
 280         test_gr_a5a5 6
 281         test_gr_a5a5 7
 282         ; 1010 0101 -> 1001 0110
 283         cmp.b   #0x96, @byte_dest
 284         beq     .Lbind2
 285         fail
 286 .Lbind2:
 287         mov.b   #0xa5, @byte_dest
 288
 289 rotl_b_indexb16_2:
 290         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 291         set_ccr_zero
 292
 293         mov.b   #5, r0l
 294         rotl.b  #2, @(byte_dest-5:16, r0.b)     ; indexed byte/byte
 295
 296         test_carry_clear        ; H=0 N=1 Z=0 C=0
 297         test_zero_clear
 298         test_ovf_clear
 299         test_neg_set
 300
 301         test_h_gr32  0xa5a5a505 er0
 302         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 303         test_gr_a5a5 2
 304         test_gr_a5a5 3
 305         test_gr_a5a5 4
 306         test_gr_a5a5 5
 307         test_gr_a5a5 6
 308         test_gr_a5a5 7
 309         ; 1010 0101 -> 1001 0110
 310         cmp.b   #0x96, @byte_dest
 311         beq     .Lbindexb162
 312         fail
 313 .Lbindexb162:
 314         mov.b   #0xa5, @byte_dest
 315
 316 rotl_b_indexw16_2:
 317         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 318         set_ccr_zero
 319
 320         mov.w   #256, r0
 321         rotl.b  #2, @(byte_dest-256:16, r0.w)   ; indexed byte/word
 322
 323         test_carry_clear        ; H=0 N=1 Z=0 C=0
 324         test_zero_clear
 325         test_ovf_clear
 326         test_neg_set
 327
 328         test_h_gr32  0xa5a50100 er0
 329         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 330         test_gr_a5a5 2
 331         test_gr_a5a5 3
 332         test_gr_a5a5 4
 333         test_gr_a5a5 5
 334         test_gr_a5a5 6
 335         test_gr_a5a5 7
 336         ; 1010 0101 -> 1001 0110
 337         cmp.b   #0x96, @byte_dest
 338         beq     .Lbindexw162
 339         fail
 340 .Lbindexw162:
 341         mov.b   #0xa5, @byte_dest
 342
 343 rotl_b_indexl16_2:
 344         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 345         set_ccr_zero
 346
 347         mov.l   #0xffffffff, er0
 348         rotl.b  #2, @(byte_dest+1:16, er0.l)    ; indexed byte/long
 349
 350         test_carry_clear        ; H=0 N=1 Z=0 C=0
 351         test_zero_clear
 352         test_ovf_clear
 353         test_neg_set
 354
 355         test_h_gr32  0xffffffff er0
 356         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 357         test_gr_a5a5 2
 358         test_gr_a5a5 3
 359         test_gr_a5a5 4
 360         test_gr_a5a5 5
 361         test_gr_a5a5 6
 362         test_gr_a5a5 7
 363         ; 1010 0101 -> 1001 0110
 364         cmp.b   #0x96, @byte_dest
 365         beq     .Lbindexl162
 366         fail
 367 .Lbindexl162:
 368         mov.b   #0xa5, @byte_dest
 369
 370 rotl_b_indexb32_2:
 371         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 372         set_ccr_zero
 373
 374         mov.b   #5, r1l
 375         rotl.b  #2, @(byte_dest-5:32, r1.b)     ; indexed byte/byte
 376
 377         test_carry_clear        ; H=0 N=1 Z=0 C=0
 378         test_zero_clear
 379         test_ovf_clear
 380         test_neg_set
 381
 382         test_h_gr32  0xa5a5a505 er1
 383         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 384         test_gr_a5a5 2
 385         test_gr_a5a5 3
 386         test_gr_a5a5 4
 387         test_gr_a5a5 5
 388         test_gr_a5a5 6
 389         test_gr_a5a5 7
 390         ; 1010 0101 -> 1001 0110
 391         cmp.b   #0x96, @byte_dest
 392         beq     .Lbindexb322
 393         fail
 394 .Lbindexb322:
 395         mov.b   #0xa5, @byte_dest
 396
 397 rotl_b_indexw32_2:
 398         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 399         set_ccr_zero
 400
 401         mov.w   #256, r1
 402         rotl.b  #2, @(byte_dest-256:32, r1.w)   ; indexed byte/word
 403
 404         test_carry_clear        ; H=0 N=1 Z=0 C=0
 405         test_zero_clear
 406         test_ovf_clear
 407         test_neg_set
 408
 409         test_h_gr32  0xa5a50100 er1
 410         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 411         test_gr_a5a5 2
 412         test_gr_a5a5 3
 413         test_gr_a5a5 4
 414         test_gr_a5a5 5
 415         test_gr_a5a5 6
 416         test_gr_a5a5 7
 417         ; 1010 0101 -> 1001 0110
 418         cmp.b   #0x96, @byte_dest
 419         beq     .Lbindexw322
 420         fail
 421 .Lbindexw322:
 422         mov.b   #0xa5, @byte_dest
 423
 424 rotl_b_indexl32_2:
 425         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 426         set_ccr_zero
 427
 428         mov.l   #0xffffffff, er1
 429         rotl.b  #2, @(byte_dest+1:32, er1.l)    ; indexed byte/long
 430
 431         test_carry_clear        ; H=0 N=1 Z=0 C=0
 432         test_zero_clear
 433         test_ovf_clear
 434         test_neg_set
 435
 436         test_h_gr32  0xffffffff er1
 437         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 438         test_gr_a5a5 2
 439         test_gr_a5a5 3
 440         test_gr_a5a5 4
 441         test_gr_a5a5 5
 442         test_gr_a5a5 6
 443         test_gr_a5a5 7
 444         ; 1010 0101 -> 1001 0110
 445         cmp.b   #0x96, @byte_dest
 446         beq     .Lbindexl322
 447         fail
 448 .Lbindexl322:
 449         mov.b   #0xa5, @byte_dest
 450
 451 .endif
 452
 453 .if (sim_cpu)                   ; Not available in h8300 mode
 454 rotl_w_reg16_1:
 455         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 456         set_ccr_zero
 457
 458         rotl.w  r0              ; shift left arithmetic by one
 459
 460         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 461         test_zero_clear
 462         test_ovf_clear
 463         test_neg_clear
 464         test_h_gr16 0x4b4b r0   ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
 465         test_h_gr32 0xa5a54b4b er0
 466
 467         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 468         test_gr_a5a5 2
 469         test_gr_a5a5 3
 470         test_gr_a5a5 4
 471         test_gr_a5a5 5
 472         test_gr_a5a5 6
 473         test_gr_a5a5 7
 474
 475 .if (sim_cpu == h8sx)
 476 rotl_w_indexb16_1:
 477         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 478         set_ccr_zero
 479
 480         mov.b   #5, r0l
 481         rotl.w  @(word_dest-10:16, r0.b)        ; indexed word/byte
 482
 483         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 484         test_zero_clear
 485         test_ovf_clear
 486         test_neg_clear
 487
 488         test_h_gr32  0xa5a5a505 er0
 489         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 490         test_gr_a5a5 2
 491         test_gr_a5a5 3
 492         test_gr_a5a5 4
 493         test_gr_a5a5 5
 494         test_gr_a5a5 6
 495         test_gr_a5a5 7
 496         ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
 497         cmp.w   #0x4b4b, @word_dest
 498         beq     .Lwindexb161
 499         fail
 500 .Lwindexb161:
 501         mov.w   #0xa5a5, @word_dest
 502
 503 rotl_w_indexw16_1:
 504         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 505         set_ccr_zero
 506
 507         mov.w   #256, r0
 508         rotl.w  @(word_dest-512:16, r0.w)       ; indexed word/word
 509
 510         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 511         test_zero_clear
 512         test_ovf_clear
 513         test_neg_clear
 514
 515         test_h_gr32  0xa5a50100 er0
 516         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 517         test_gr_a5a5 2
 518         test_gr_a5a5 3
 519         test_gr_a5a5 4
 520         test_gr_a5a5 5
 521         test_gr_a5a5 6
 522         test_gr_a5a5 7
 523         ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
 524         cmp.w   #0x4b4b, @word_dest
 525         beq     .Lwindexw161
 526         fail
 527 .Lwindexw161:
 528         mov.w   #0xa5a5, @word_dest
 529
 530 rotl_w_indexl16_1:
 531         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 532         set_ccr_zero
 533
 534         mov.l   #0xffffffff, er0
 535         rotl.w  @(word_dest+2:16, er0.l)        ; indexed word/long
 536
 537         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 538         test_zero_clear
 539         test_ovf_clear
 540         test_neg_clear
 541
 542         test_h_gr32  0xffffffff er0
 543         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 544         test_gr_a5a5 2
 545         test_gr_a5a5 3
 546         test_gr_a5a5 4
 547         test_gr_a5a5 5
 548         test_gr_a5a5 6
 549         test_gr_a5a5 7
 550         ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
 551         cmp.w   #0x4b4b, @word_dest
 552         beq     .Lwindexl161
 553         fail
 554 .Lwindexl161:
 555         mov.w   #0xa5a5, @word_dest
 556
 557 rotl_w_indexb32_1:
 558         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 559         set_ccr_zero
 560
 561         mov.b   #5, r1l
 562         rotl.w  @(word_dest-10:32, r1.b)        ; indexed word/byte
 563
 564         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 565         test_zero_clear
 566         test_ovf_clear
 567         test_neg_clear
 568
 569         test_h_gr32  0xa5a5a505 er1
 570         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 571         test_gr_a5a5 2
 572         test_gr_a5a5 3
 573         test_gr_a5a5 4
 574         test_gr_a5a5 5
 575         test_gr_a5a5 6
 576         test_gr_a5a5 7
 577         ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
 578         cmp.w   #0x4b4b, @word_dest
 579         beq     .Lwindexb321
 580         fail
 581 .Lwindexb321:
 582         mov.w   #0xa5a5, @word_dest
 583
 584 rotl_w_indexw32_1:
 585         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 586         set_ccr_zero
 587
 588         mov.w   #256, r1
 589         rotl.w  @(word_dest-512:32, r1.w)       ; indexed word/byte
 590
 591         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 592         test_zero_clear
 593         test_ovf_clear
 594         test_neg_clear
 595
 596         test_h_gr32  0xa5a50100 er1
 597         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 598         test_gr_a5a5 2
 599         test_gr_a5a5 3
 600         test_gr_a5a5 4
 601         test_gr_a5a5 5
 602         test_gr_a5a5 6
 603         test_gr_a5a5 7
 604         ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
 605         cmp.w   #0x4b4b, @word_dest
 606         beq     .Lwindexw321
 607         fail
 608 .Lwindexw321:
 609         mov.w   #0xa5a5, @word_dest
 610
 611 rotl_w_indexl32_1:
 612         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 613         set_ccr_zero
 614
 615         mov.l   #0xffffffff, er1
 616         rotl.w  @(word_dest+2:32, er1.l)        ; indexed word/byte
 617
 618         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 619         test_zero_clear
 620         test_ovf_clear
 621         test_neg_clear
 622
 623         test_h_gr32  0xffffffff er1
 624         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 625         test_gr_a5a5 2
 626         test_gr_a5a5 3
 627         test_gr_a5a5 4
 628         test_gr_a5a5 5
 629         test_gr_a5a5 6
 630         test_gr_a5a5 7
 631         ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
 632         cmp.w   #0x4b4b, @word_dest
 633         beq     .Lwindexl321
 634         fail
 635 .Lwindexl321:
 636         mov.w   #0xa5a5, @word_dest
 637 .endif
 638
 639 rotl_w_reg16_2:
 640         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 641         set_ccr_zero
 642
 643         rotl.w  #2, r0          ; shift left arithmetic by two
 644
 645         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 646         test_zero_clear
 647         test_ovf_clear
 648         test_neg_set
 649         test_h_gr16 0x9696 r0   ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
 650         test_h_gr32 0xa5a59696 er0
 651
 652         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 653         test_gr_a5a5 2
 654         test_gr_a5a5 3
 655         test_gr_a5a5 4
 656         test_gr_a5a5 5
 657         test_gr_a5a5 6
 658         test_gr_a5a5 7
 659
 660 .if (sim_cpu == h8sx)
 661 rotl_w_indexb16_2:
 662         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 663         set_ccr_zero
 664
 665         mov.b   #5, r0l
 666         rotl.w  #2, @(word_dest-10:16, r0.b)    ; indexed word/byte
 667
 668         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
 669         test_zero_clear
 670         test_ovf_clear
 671         test_neg_set
 672
 673         test_h_gr32  0xa5a5a505 er0
 674         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 675         test_gr_a5a5 2
 676         test_gr_a5a5 3
 677         test_gr_a5a5 4
 678         test_gr_a5a5 5
 679         test_gr_a5a5 6
 680         test_gr_a5a5 7
 681         ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
 682         cmp.w   #0x9696, @word_dest
 683         beq     .Lwindexb162
 684         fail
 685 .Lwindexb162:
 686         mov.w   #0xa5a5, @word_dest
 687
 688 rotl_w_indexw16_2:
 689         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 690         set_ccr_zero
 691
 692         mov.w   #256, r0
 693         rotl.w  #2, @(word_dest-512:16, r0.w)   ; indexed word/word
 694
 695         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
 696         test_zero_clear
 697         test_ovf_clear
 698         test_neg_set
 699
 700         test_h_gr32  0xa5a50100 er0
 701         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 702         test_gr_a5a5 2
 703         test_gr_a5a5 3
 704         test_gr_a5a5 4
 705         test_gr_a5a5 5
 706         test_gr_a5a5 6
 707         test_gr_a5a5 7
 708         ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
 709         cmp.w   #0x9696, @word_dest
 710         beq     .Lwindexw162
 711         fail
 712 .Lwindexw162:
 713         mov.w   #0xa5a5, @word_dest
 714
 715 rotl_w_indexl16_2:
 716         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 717         set_ccr_zero
 718
 719         mov.l   #0xffffffff, er0
 720         rotl.w  #2, @(word_dest+2:16, er0.l)    ; indexed word/long
 721
 722         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
 723         test_zero_clear
 724         test_ovf_clear
 725         test_neg_set
 726
 727         test_h_gr32  0xffffffff er0
 728         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 729         test_gr_a5a5 2
 730         test_gr_a5a5 3
 731         test_gr_a5a5 4
 732         test_gr_a5a5 5
 733         test_gr_a5a5 6
 734         test_gr_a5a5 7
 735         ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
 736         cmp.w   #0x9696, @word_dest
 737         beq     .Lwindexl162
 738         fail
 739 .Lwindexl162:
 740         mov.w   #0xa5a5, @word_dest
 741
 742 rotl_w_indexb32_2:
 743         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 744         set_ccr_zero
 745
 746         mov.b   #5, r1l
 747         rotl.w  #2, @(word_dest-10:32, r1.b)    ; indexed word/byte
 748
 749         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
 750         test_zero_clear
 751         test_ovf_clear
 752         test_neg_set
 753
 754         test_h_gr32  0xa5a5a505 er1
 755         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 756         test_gr_a5a5 2
 757         test_gr_a5a5 3
 758         test_gr_a5a5 4
 759         test_gr_a5a5 5
 760         test_gr_a5a5 6
 761         test_gr_a5a5 7
 762         ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
 763         cmp.w   #0x9696, @word_dest
 764         beq     .Lwindexb322
 765         fail
 766 .Lwindexb322:
 767         mov.w   #0xa5a5, @word_dest
 768
 769 rotl_w_indexw32_2:
 770         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 771         set_ccr_zero
 772
 773         mov.w   #256, r1
 774         rotl.w  #2, @(word_dest-512:32, r1.w)   ; indexed word/byte
 775
 776         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
 777         test_zero_clear
 778         test_ovf_clear
 779         test_neg_set
 780
 781         test_h_gr32  0xa5a50100 er1
 782         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 783         test_gr_a5a5 2
 784         test_gr_a5a5 3
 785         test_gr_a5a5 4
 786         test_gr_a5a5 5
 787         test_gr_a5a5 6
 788         test_gr_a5a5 7
 789         ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
 790         cmp.w   #0x9696, @word_dest
 791         beq     .Lwindexw322
 792         fail
 793 .Lwindexw322:
 794         mov.w   #0xa5a5, @word_dest
 795
 796 rotl_w_indexl32_2:
 797         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 798         set_ccr_zero
 799
 800         mov.l   #0xffffffff, er1
 801         rotl.w  #2, @(word_dest+2:32, er1.l)    ; indexed word/byte
 802
 803         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
 804         test_zero_clear
 805         test_ovf_clear
 806         test_neg_set
 807
 808         test_h_gr32  0xffffffff er1
 809         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 810         test_gr_a5a5 2
 811         test_gr_a5a5 3
 812         test_gr_a5a5 4
 813         test_gr_a5a5 5
 814         test_gr_a5a5 6
 815         test_gr_a5a5 7
 816         ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
 817         cmp.w   #0x9696, @word_dest
 818         beq     .Lwindexl322
 819         fail
 820 .Lwindexl322:
 821         mov.w   #0xa5a5, @word_dest
 822 .endif
 823
 824 rotl_l_reg32_1:
 825         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 826         set_ccr_zero
 827
 828         rotl.l  er0             ; shift left arithmetic by one
 829
 830         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 831         test_zero_clear
 832         test_ovf_clear
 833         test_neg_clear
 834         ; 1010 0101 1010 0101 1010 0101 1010 0101
 835         ; -> 0100 1011 0100 1011 0100 1011 0100 1011
 836         test_h_gr32 0x4b4b4b4b er0
 837
 838         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 839         test_gr_a5a5 2
 840         test_gr_a5a5 3
 841         test_gr_a5a5 4
 842         test_gr_a5a5 5
 843         test_gr_a5a5 6
 844         test_gr_a5a5 7
 845
 846 .if (sim_cpu == h8sx)
 847 rotl_l_indexb16_1:
 848         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 849         set_ccr_zero
 850
 851         mov.b   #5, r0l
 852         rotl.l  @(long_dest-20:16, er0.b)       ; indexed long/byte
 853
 854         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 855         test_zero_clear
 856         test_ovf_clear
 857         test_neg_clear
 858
 859         test_h_gr32  0xa5a5a505 er0
 860         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 861         test_gr_a5a5 2
 862         test_gr_a5a5 3
 863         test_gr_a5a5 4
 864         test_gr_a5a5 5
 865         test_gr_a5a5 6
 866         test_gr_a5a5 7
 867         ; 1010 0101 1010 0101 1010 0101 1010 0101
 868         ; -> 0100 1011 0100 1011 0100 1011 0100 1011
 869         cmp.l   #0x4b4b4b4b, @long_dest
 870         beq     .Llindexb161
 871         fail
 872 .Llindexb161:
 873         mov.l   #0xa5a5a5a5, @long_dest
 874
 875 rotl_l_indexw16_1:
 876         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 877         set_ccr_zero
 878
 879         mov.w   #256, r0
 880         rotl.l  @(long_dest-1024:16, er0.w)     ; indexed long/word
 881
 882         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 883         test_zero_clear
 884         test_ovf_clear
 885         test_neg_clear
 886
 887         test_h_gr32  0xa5a50100 er0
 888         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 889         test_gr_a5a5 2
 890         test_gr_a5a5 3
 891         test_gr_a5a5 4
 892         test_gr_a5a5 5
 893         test_gr_a5a5 6
 894         test_gr_a5a5 7
 895         ; 1010 0101 1010 0101 1010 0101 1010 0101
 896         ; -> 0100 1011 0100 1011 0100 1011 0100 1011
 897         cmp.l   #0x4b4b4b4b, @long_dest
 898         beq     .Llindexw161
 899         fail
 900 .Llindexw161:
 901         mov.l   #0xa5a5a5a5, @long_dest
 902
 903 rotl_l_indexl16_1:
 904         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 905         set_ccr_zero
 906
 907         mov.l   #0xffffffff, er0
 908         rotl.l  @(long_dest+4:16, er0.l)        ; indexed long/long
 909
 910         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 911         test_zero_clear
 912         test_ovf_clear
 913         test_neg_clear
 914
 915         test_h_gr32  0xffffffff er0
 916         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 917         test_gr_a5a5 2
 918         test_gr_a5a5 3
 919         test_gr_a5a5 4
 920         test_gr_a5a5 5
 921         test_gr_a5a5 6
 922         test_gr_a5a5 7
 923         ; 1010 0101 1010 0101 1010 0101 1010 0101
 924         ; -> 0100 1011 0100 1011 0100 1011 0100 1011
 925         cmp.l   #0x4b4b4b4b, @long_dest
 926         beq     .Llindexl161
 927         fail
 928 .Llindexl161:
 929         mov.l   #0xa5a5a5a5, @long_dest
 930
 931 rotl_l_indexb32_1:
 932         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 933         set_ccr_zero
 934
 935         mov.b   #5, r1l
 936         rotl.l  @(long_dest-20:32, er1.b)       ; indexed long/byte
 937
 938         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 939         test_zero_clear
 940         test_ovf_clear
 941         test_neg_clear
 942
 943         test_h_gr32  0xa5a5a505 er1
 944         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 945         test_gr_a5a5 2
 946         test_gr_a5a5 3
 947         test_gr_a5a5 4
 948         test_gr_a5a5 5
 949         test_gr_a5a5 6
 950         test_gr_a5a5 7
 951         ; 1010 0101 1010 0101 1010 0101 1010 0101
 952         ; -> 0100 1011 0100 1011 0100 1011 0100 1011
 953         cmp.l   #0x4b4b4b4b, @long_dest
 954         beq     .Llindexb321
 955         fail
 956 .Llindexb321:
 957         mov.l   #0xa5a5a5a5, @long_dest
 958
 959 rotl_l_indexw32_1:
 960         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 961         set_ccr_zero
 962
 963         mov.w   #256, r1
 964         rotl.l  @(long_dest-1024:32, er1.w)     ; indexed long/byte
 965
 966         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 967         test_zero_clear
 968         test_ovf_clear
 969         test_neg_clear
 970
 971         test_h_gr32  0xa5a50100 er1
 972         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 973         test_gr_a5a5 2
 974         test_gr_a5a5 3
 975         test_gr_a5a5 4
 976         test_gr_a5a5 5
 977         test_gr_a5a5 6
 978         test_gr_a5a5 7
 979         ; 1010 0101 1010 0101 1010 0101 1010 0101
 980         ; -> 0100 1011 0100 1011 0100 1011 0100 1011
 981         cmp.l   #0x4b4b4b4b, @long_dest
 982         beq     .Llindexw321
 983         fail
 984 .Llindexw321:
 985         mov.l   #0xa5a5a5a5, @long_dest
 986
 987 rotl_l_indexl32_1:
 988         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 989         set_ccr_zero
 990
 991         mov.l   #0xffffffff, er1
 992         rotl.l  @(long_dest+4:32, er1.l)        ; indexed long/byte
 993
 994         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 995         test_zero_clear
 996         test_ovf_clear
 997         test_neg_clear
 998
 999         test_h_gr32  0xffffffff er1
1000         test_gr_a5a5 0          ; Make sure other general regs not disturbed
1001         test_gr_a5a5 2
1002         test_gr_a5a5 3
1003         test_gr_a5a5 4
1004         test_gr_a5a5 5
1005         test_gr_a5a5 6
1006         test_gr_a5a5 7
1007         ; 1010 0101 1010 0101 1010 0101 1010 0101
1008         ; -> 0100 1011 0100 1011 0100 1011 0100 1011
1009         cmp.l   #0x4b4b4b4b, @long_dest
1010         beq     .Llindexl321
1011         fail
1012 .Llindexl321:
1013         mov.l   #0xa5a5a5a5, @long_dest
1014 .endif
1015
1016 rotl_l_reg32_2:
1017         set_grs_a5a5            ; Fill all general regs with a fixed pattern
1018         set_ccr_zero
1019
1020         rotl.l  #2, er0         ; shift left arithmetic by two
1021
1022         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
1023         test_zero_clear
1024         test_ovf_clear
1025         test_neg_set
1026         ; 1010 0101 1010 0101 1010 0101 1010 0101
1027         ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1028         test_h_gr32 0x96969696 er0
1029
1030         test_gr_a5a5 1          ; Make sure other general regs not disturbed
1031         test_gr_a5a5 2
1032         test_gr_a5a5 3
1033         test_gr_a5a5 4
1034         test_gr_a5a5 5
1035         test_gr_a5a5 6
1036         test_gr_a5a5 7
1037
1038 .if (sim_cpu == h8sx)
1039 rotl_l_indexb16_2:
1040         set_grs_a5a5            ; Fill all general regs with a fixed pattern
1041         set_ccr_zero
1042
1043         mov.b   #5, r0l
1044         rotl.l  #2, @(long_dest-20:16, er0.b)   ; indexed long/byte
1045
1046         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
1047         test_zero_clear
1048         test_ovf_clear
1049         test_neg_set
1050
1051         test_h_gr32  0xa5a5a505 er0
1052         test_gr_a5a5 1          ; Make sure other general regs not disturbed
1053         test_gr_a5a5 2
1054         test_gr_a5a5 3
1055         test_gr_a5a5 4
1056         test_gr_a5a5 5
1057         test_gr_a5a5 6
1058         test_gr_a5a5 7
1059         ; 1010 0101 1010 0101 1010 0101 1010 0101
1060         ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1061         cmp.l   #0x96969696, @long_dest
1062         beq     .Llindexb162
1063         fail
1064 .Llindexb162:
1065         mov.l   #0xa5a5a5a5, @long_dest
1066
1067 rotl_l_indexw16_2:
1068         set_grs_a5a5            ; Fill all general regs with a fixed pattern
1069         set_ccr_zero
1070
1071         mov.w   #256, r0
1072         rotl.l  #2, @(long_dest-1024:16, er0.w) ; indexed long/word
1073
1074         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
1075         test_zero_clear
1076         test_ovf_clear
1077         test_neg_set
1078
1079         test_h_gr32  0xa5a50100 er0
1080         test_gr_a5a5 1          ; Make sure other general regs not disturbed
1081         test_gr_a5a5 2
1082         test_gr_a5a5 3
1083         test_gr_a5a5 4
1084         test_gr_a5a5 5
1085         test_gr_a5a5 6
1086         test_gr_a5a5 7
1087         ; 1010 0101 1010 0101 1010 0101 1010 0101
1088         ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1089         cmp.l   #0x96969696, @long_dest
1090         beq     .Llindexw162
1091         fail
1092 .Llindexw162:
1093         mov.l   #0xa5a5a5a5, @long_dest
1094
1095 rotl_l_indexl16_2:
1096         set_grs_a5a5            ; Fill all general regs with a fixed pattern
1097         set_ccr_zero
1098
1099         mov.l   #0xffffffff, er0
1100         rotl.l  #2, @(long_dest+4:16, er0.l)    ; indexed long/long
1101
1102         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
1103         test_zero_clear
1104         test_ovf_clear
1105         test_neg_set
1106
1107         test_h_gr32  0xffffffff er0
1108         test_gr_a5a5 1          ; Make sure other general regs not disturbed
1109         test_gr_a5a5 2
1110         test_gr_a5a5 3
1111         test_gr_a5a5 4
1112         test_gr_a5a5 5
1113         test_gr_a5a5 6
1114         test_gr_a5a5 7
1115         ; 1010 0101 1010 0101 1010 0101 1010 0101
1116         ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1117         cmp.l   #0x96969696, @long_dest
1118         beq     .Llindexl162
1119         fail
1120 .Llindexl162:
1121         mov.l   #0xa5a5a5a5, @long_dest
1122
1123 rotl_l_indexb32_2:
1124         set_grs_a5a5            ; Fill all general regs with a fixed pattern
1125         set_ccr_zero
1126
1127         mov.b   #5, r1l
1128         rotl.l  #2, @(long_dest-20:32, er1.b)   ; indexed long/byte
1129
1130         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
1131         test_zero_clear
1132         test_ovf_clear
1133         test_neg_set
1134
1135         test_h_gr32  0xa5a5a505 er1
1136         test_gr_a5a5 0          ; Make sure other general regs not disturbed
1137         test_gr_a5a5 2
1138         test_gr_a5a5 3
1139         test_gr_a5a5 4
1140         test_gr_a5a5 5
1141         test_gr_a5a5 6
1142         test_gr_a5a5 7
1143         ; 1010 0101 1010 0101 1010 0101 1010 0101
1144         ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1145         cmp.l   #0x96969696, @long_dest
1146         beq     .Llindexb322
1147         fail
1148 .Llindexb322:
1149         mov.l   #0xa5a5a5a5, @long_dest
1150
1151 rotl_l_indexw32_2:
1152         set_grs_a5a5            ; Fill all general regs with a fixed pattern
1153         set_ccr_zero
1154
1155         mov.w   #256, r1
1156         rotl.l  #2, @(long_dest-1024:32, er1.w) ; indexed long/byte
1157
1158         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
1159         test_zero_clear
1160         test_ovf_clear
1161         test_neg_set
1162
1163         test_h_gr32  0xa5a50100 er1
1164         test_gr_a5a5 0          ; Make sure other general regs not disturbed
1165         test_gr_a5a5 2
1166         test_gr_a5a5 3
1167         test_gr_a5a5 4
1168         test_gr_a5a5 5
1169         test_gr_a5a5 6
1170         test_gr_a5a5 7
1171         ; 1010 0101 1010 0101 1010 0101 1010 0101
1172         ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1173         cmp.l   #0x96969696, @long_dest
1174         beq     .Llindexw322
1175         fail
1176 .Llindexw322:
1177         mov.l   #0xa5a5a5a5, @long_dest
1178
1179 rotl_l_indexl32_2:
1180         set_grs_a5a5            ; Fill all general regs with a fixed pattern
1181         set_ccr_zero
1182
1183         mov.l   #0xffffffff, er1
1184         rotl.l  #2, @(long_dest+4:32, er1.l)    ; indexed long/byte
1185
1186         test_carry_clear                ; H=0 N=1 Z=0 V=0 C=0
1187         test_zero_clear
1188         test_ovf_clear
1189         test_neg_set
1190
1191         test_h_gr32  0xffffffff er1
1192         test_gr_a5a5 0          ; Make sure other general regs not disturbed
1193         test_gr_a5a5 2
1194         test_gr_a5a5 3
1195         test_gr_a5a5 4
1196         test_gr_a5a5 5
1197         test_gr_a5a5 6
1198         test_gr_a5a5 7
1199         ; 1010 0101 1010 0101 1010 0101 1010 0101
1200         ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1201         cmp.l   #0x96969696, @long_dest
1202         beq     .Llindexl322
1203         fail
1204 .Llindexl322:
1205         mov.l   #0xa5a5a5a5, @long_dest
1206 .endif
1207 .endif
1208
1209         pass
1210
1211         exit 0
1212