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[binutils-gdb.git] / sim / testsuite / h8300 / shar.s
1 # Hitachi H8 testcase 'shar'
2 # mach(): h8300s h8sx
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
10
11 .include "testutils.inc"
12
13 start
14
15 .data
16 byte_dest: .byte 0xa5
17 .align 2
18 word_dest: .word 0xa5a5
19 .align 4
20 long_dest: .long 0xa5a5a5a5
21
22 .text
23
24 shar_b_reg8_1:
25 set_grs_a5a5 ; Fill all general regs with a fixed pattern
26 set_ccr_zero
27
28 shar.b r0l ; shift right arithmetic by one
29 ;;; .word 0x1188
30
31 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
32 test_zero_clear
33 test_ovf_clear
34 test_neg_set
35
36 test_h_gr16 0xa5d2 r0 ; 1010 0101 -> 1101 0010
37 .if (sim_cpu)
38 test_h_gr32 0xa5a5a5d2 er0
39 .endif
40 test_gr_a5a5 1 ; Make sure other general regs not disturbed
41 test_gr_a5a5 2
42 test_gr_a5a5 3
43 test_gr_a5a5 4
44 test_gr_a5a5 5
45 test_gr_a5a5 6
46 test_gr_a5a5 7
47
48 .if (sim_cpu == h8sx)
49 shar_b_ind_1:
50 set_grs_a5a5 ; Fill all general regs with a fixed pattern
51 set_ccr_zero
52
53 mov #byte_dest, er0
54 shar.b @er0 ; shift right arithmetic by one, indirect
55 ;;; .word 0x7d00
56 ;;; .word 0x1180
57
58 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
59 test_zero_clear
60 test_ovf_clear
61 test_neg_set
62
63 test_h_gr32 byte_dest er0
64 test_gr_a5a5 1 ; Make sure other general regs not disturbed
65 test_gr_a5a5 2
66 test_gr_a5a5 3
67 test_gr_a5a5 4
68 test_gr_a5a5 5
69 test_gr_a5a5 6
70 test_gr_a5a5 7
71 ; 1010 0101 -> 1101 0010
72 cmp.b #0xd2, @byte_dest
73 beq .Lbind1
74 fail
75 .Lbind1:
76 mov.b #0xa5, @byte_dest
77
78 shar_b_postinc_1:
79 set_grs_a5a5 ; Fill all general regs with a fixed pattern
80 set_ccr_zero
81
82 mov #byte_dest, er0
83 shar.b @er0+ ; shift right arithmetic by one, postinc
84 ;;; .word 0x0174
85 ;;; .word 0x6c08
86 ;;; .word 0x1180
87
88 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
89 test_zero_clear
90 test_ovf_clear
91 test_neg_set
92
93 test_h_gr32 byte_dest+1 er0
94 test_gr_a5a5 1 ; Make sure other general regs not disturbed
95 test_gr_a5a5 2
96 test_gr_a5a5 3
97 test_gr_a5a5 4
98 test_gr_a5a5 5
99 test_gr_a5a5 6
100 test_gr_a5a5 7
101 ; 1010 0101 -> 1101 0010
102 cmp.b #0xd2, @byte_dest
103 beq .Lbpostinc1
104 fail
105 .Lbpostinc1:
106 mov.b #0xa5, @byte_dest
107
108 shar_b_postdec_1:
109 set_grs_a5a5 ; Fill all general regs with a fixed pattern
110 set_ccr_zero
111
112 mov #byte_dest, er0
113 shar.b @er0- ; shift right arithmetic by one, postdec
114 ;;; .word 0x0176
115 ;;; .word 0x6c08
116 ;;; .word 0x1180
117
118 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
119 test_zero_clear
120 test_ovf_clear
121 test_neg_set
122
123 test_h_gr32 byte_dest-1 er0
124 test_gr_a5a5 1 ; Make sure other general regs not disturbed
125 test_gr_a5a5 2
126 test_gr_a5a5 3
127 test_gr_a5a5 4
128 test_gr_a5a5 5
129 test_gr_a5a5 6
130 test_gr_a5a5 7
131 ; 1010 0101 -> 1101 0010
132 cmp.b #0xd2, @byte_dest
133 beq .Lbpostdec1
134 fail
135 .Lbpostdec1:
136 mov.b #0xa5, @byte_dest
137
138 shar_b_preinc_1:
139 set_grs_a5a5 ; Fill all general regs with a fixed pattern
140 set_ccr_zero
141
142 mov #byte_dest-1, er0
143 shar.b @+er0 ; shift right arithmetic by one, preinc
144 ;;; .word 0x0175
145 ;;; .word 0x6c08
146 ;;; .word 0x1180
147
148 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
149 test_zero_clear
150 test_ovf_clear
151 test_neg_set
152
153 test_h_gr32 byte_dest er0
154 test_gr_a5a5 1 ; Make sure other general regs not disturbed
155 test_gr_a5a5 2
156 test_gr_a5a5 3
157 test_gr_a5a5 4
158 test_gr_a5a5 5
159 test_gr_a5a5 6
160 test_gr_a5a5 7
161 ; 1010 0101 -> 1101 0010
162 cmp.b #0xd2, @byte_dest
163 beq .Lbpreinc1
164 fail
165 .Lbpreinc1:
166 mov.b #0xa5, @byte_dest
167
168 shar_b_predec_1:
169 set_grs_a5a5 ; Fill all general regs with a fixed pattern
170 set_ccr_zero
171
172 mov #byte_dest+1, er0
173 shar.b @-er0 ; shift right arithmetic by one, predec
174 ;;; .word 0x0177
175 ;;; .word 0x6c08
176 ;;; .word 0x1180
177
178 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
179 test_zero_clear
180 test_ovf_clear
181 test_neg_set
182
183 test_h_gr32 byte_dest er0
184 test_gr_a5a5 1 ; Make sure other general regs not disturbed
185 test_gr_a5a5 2
186 test_gr_a5a5 3
187 test_gr_a5a5 4
188 test_gr_a5a5 5
189 test_gr_a5a5 6
190 test_gr_a5a5 7
191 ; 1010 0101 -> 1101 0010
192 cmp.b #0xd2, @byte_dest
193 beq .Lbpredec1
194 fail
195 .Lbpredec1:
196 mov.b #0xa5, @byte_dest
197
198 shar_b_disp2_1:
199 set_grs_a5a5 ; Fill all general regs with a fixed pattern
200 set_ccr_zero
201
202 mov #byte_dest-2, er0
203 shar.b @(2:2, er0) ; shift right arithmetic by one, disp2
204 ;;; .word 0x0176
205 ;;; .word 0x6808
206 ;;; .word 0x1180
207
208 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
209 test_zero_clear
210 test_ovf_clear
211 test_neg_set
212
213 test_h_gr32 byte_dest-2 er0
214 test_gr_a5a5 1 ; Make sure other general regs not disturbed
215 test_gr_a5a5 2
216 test_gr_a5a5 3
217 test_gr_a5a5 4
218 test_gr_a5a5 5
219 test_gr_a5a5 6
220 test_gr_a5a5 7
221 ; 1010 0101 -> 1101 0010
222 cmp.b #0xd2, @byte_dest
223 beq .Lbdisp21
224 fail
225 .Lbdisp21:
226 mov.b #0xa5, @byte_dest
227
228 shar_b_disp16_1:
229 set_grs_a5a5 ; Fill all general regs with a fixed pattern
230 set_ccr_zero
231
232 mov #byte_dest-44, er0
233 shar.b @(44:16, er0) ; shift right arithmetic by one, disp16
234 ;;; .word 0x0174
235 ;;; .word 0x6e08
236 ;;; .word 44
237 ;;; .word 0x1180
238
239 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
240 test_zero_clear
241 test_ovf_clear
242 test_neg_set
243
244 test_h_gr32 byte_dest-44 er0
245 test_gr_a5a5 1 ; Make sure other general regs not disturbed
246 test_gr_a5a5 2
247 test_gr_a5a5 3
248 test_gr_a5a5 4
249 test_gr_a5a5 5
250 test_gr_a5a5 6
251 test_gr_a5a5 7
252 ; 1010 0101 -> 1101 0010
253 cmp.b #0xd2, @byte_dest
254 beq .Lbdisp161
255 fail
256 .Lbdisp161:
257 mov.b #0xa5, @byte_dest
258
259 shar_b_disp32_1:
260 set_grs_a5a5 ; Fill all general regs with a fixed pattern
261 set_ccr_zero
262
263 mov #byte_dest-666, er0
264 shar.b @(666:32, er0) ; shift right arithmetic by one, disp32
265 ;;; .word 0x7884
266 ;;; .word 0x6a28
267 ;;; .long 666
268 ;;; .word 0x1180
269
270 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
271 test_zero_clear
272 test_ovf_clear
273 test_neg_set
274
275 test_h_gr32 byte_dest-666 er0
276 test_gr_a5a5 1 ; Make sure other general regs not disturbed
277 test_gr_a5a5 2
278 test_gr_a5a5 3
279 test_gr_a5a5 4
280 test_gr_a5a5 5
281 test_gr_a5a5 6
282 test_gr_a5a5 7
283 ; 1010 0101 -> 1101 0010
284 cmp.b #0xd2, @byte_dest
285 beq .Lbdisp321
286 fail
287 .Lbdisp321:
288 mov.b #0xa5, @byte_dest
289
290 shar_b_abs16_1:
291 set_grs_a5a5 ; Fill all general regs with a fixed pattern
292 set_ccr_zero
293
294 shar.b @byte_dest:16 ; shift right arithmetic by one, abs16
295 ;;; .word 0x6a18
296 ;;; .word byte_dest
297 ;;; .word 0x1180
298
299 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
300 test_zero_clear
301 test_ovf_clear
302 test_neg_set
303
304 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
305 test_gr_a5a5 2
306 test_gr_a5a5 2
307 test_gr_a5a5 3
308 test_gr_a5a5 4
309 test_gr_a5a5 5
310 test_gr_a5a5 6
311 test_gr_a5a5 7
312 ; 1010 0101 -> 1101 0010
313 cmp.b #0xd2, @byte_dest
314 beq .Lbabs161
315 fail
316 .Lbabs161:
317 mov.b #0xa5, @byte_dest
318
319 shar_b_abs32_1:
320 set_grs_a5a5 ; Fill all general regs with a fixed pattern
321 set_ccr_zero
322
323 shar.b @byte_dest:32 ; shift right arithmetic by one, abs32
324 ;;; .word 0x6a38
325 ;;; .long byte_dest
326 ;;; .word 0x1180
327
328 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
329 test_zero_clear
330 test_ovf_clear
331 test_neg_set
332
333 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
334 test_gr_a5a5 2
335 test_gr_a5a5 2
336 test_gr_a5a5 3
337 test_gr_a5a5 4
338 test_gr_a5a5 5
339 test_gr_a5a5 6
340 test_gr_a5a5 7
341 ; 1010 0101 -> 1101 0010
342 cmp.b #0xd2, @byte_dest
343 beq .Lbabs321
344 fail
345 .Lbabs321:
346 mov.b #0xa5, @byte_dest
347 .endif
348
349 shar_b_reg8_2:
350 set_grs_a5a5 ; Fill all general regs with a fixed pattern
351 set_ccr_zero
352
353 shar.b #2, r0l ; shift right arithmetic by two
354 ;;; .word 0x11c8
355
356 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
357 test_zero_clear
358 test_ovf_clear
359 test_neg_set
360 test_h_gr16 0xa5e9 r0 ; 1010 0101 -> 1110 1001
361 .if (sim_cpu)
362 test_h_gr32 0xa5a5a5e9 er0
363 .endif
364 test_gr_a5a5 1 ; Make sure other general regs not disturbed
365 test_gr_a5a5 2
366 test_gr_a5a5 3
367 test_gr_a5a5 4
368 test_gr_a5a5 5
369 test_gr_a5a5 6
370 test_gr_a5a5 7
371
372 .if (sim_cpu == h8sx)
373 shar_b_ind_2:
374 set_grs_a5a5 ; Fill all general regs with a fixed pattern
375 set_ccr_zero
376
377 mov #byte_dest, er0
378 shar.b #2, @er0 ; shift right arithmetic by two, indirect
379 ;;; .word 0x7d00
380 ;;; .word 0x11c0
381
382 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
383 test_zero_clear
384 test_ovf_clear
385 test_neg_set
386
387 test_h_gr32 byte_dest er0
388 test_gr_a5a5 1 ; Make sure other general regs not disturbed
389 test_gr_a5a5 2
390 test_gr_a5a5 3
391 test_gr_a5a5 4
392 test_gr_a5a5 5
393 test_gr_a5a5 6
394 test_gr_a5a5 7
395 ; 1010 0101 -> 1110 1001
396 cmp.b #0xe9, @byte_dest
397 beq .Lbind2
398 fail
399 .Lbind2:
400 mov.b #0xa5, @byte_dest
401
402 shar_b_postinc_2:
403 set_grs_a5a5 ; Fill all general regs with a fixed pattern
404 set_ccr_zero
405
406 mov #byte_dest, er0
407 shar.b #2, @er0+ ; shift right arithmetic by two, postinc
408 ;;; .word 0x0174
409 ;;; .word 0x6c08
410 ;;; .word 0x11c0
411
412 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
413 test_zero_clear
414 test_ovf_clear
415 test_neg_set
416
417 test_h_gr32 byte_dest+1 er0
418 test_gr_a5a5 1 ; Make sure other general regs not disturbed
419 test_gr_a5a5 2
420 test_gr_a5a5 3
421 test_gr_a5a5 4
422 test_gr_a5a5 5
423 test_gr_a5a5 6
424 test_gr_a5a5 7
425 ; 1010 0101 -> 1110 1001
426 cmp.b #0xe9, @byte_dest
427 beq .Lbpostinc2
428 fail
429 .Lbpostinc2:
430 mov.b #0xa5, @byte_dest
431
432 shar_b_postdec_2:
433 set_grs_a5a5 ; Fill all general regs with a fixed pattern
434 set_ccr_zero
435
436 mov #byte_dest, er0
437 shar.b #2, @er0- ; shift right arithmetic by two, postdec
438 ;;; .word 0x0176
439 ;;; .word 0x6c08
440 ;;; .word 0x11c0
441
442 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
443 test_zero_clear
444 test_ovf_clear
445 test_neg_set
446
447 test_h_gr32 byte_dest-1 er0
448 test_gr_a5a5 1 ; Make sure other general regs not disturbed
449 test_gr_a5a5 2
450 test_gr_a5a5 3
451 test_gr_a5a5 4
452 test_gr_a5a5 5
453 test_gr_a5a5 6
454 test_gr_a5a5 7
455 ; 1010 0101 -> 1110 1001
456 cmp.b #0xe9, @byte_dest
457 beq .Lbpostdec2
458 fail
459 .Lbpostdec2:
460 mov.b #0xa5, @byte_dest
461
462 shar_b_preinc_2:
463 set_grs_a5a5 ; Fill all general regs with a fixed pattern
464 set_ccr_zero
465
466 mov #byte_dest-1, er0
467 shar.b #2, @+er0 ; shift right arithmetic by two, preinc
468 ;;; .word 0x0175
469 ;;; .word 0x6c08
470 ;;; .word 0x11c0
471
472 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
473 test_zero_clear
474 test_ovf_clear
475 test_neg_set
476
477 test_h_gr32 byte_dest er0
478 test_gr_a5a5 1 ; Make sure other general regs not disturbed
479 test_gr_a5a5 2
480 test_gr_a5a5 3
481 test_gr_a5a5 4
482 test_gr_a5a5 5
483 test_gr_a5a5 6
484 test_gr_a5a5 7
485 ; 1010 0101 -> 1110 1001
486 cmp.b #0xe9, @byte_dest
487 beq .Lbpreinc2
488 fail
489 .Lbpreinc2:
490 mov.b #0xa5, @byte_dest
491
492 shar_b_predec_2:
493 set_grs_a5a5 ; Fill all general regs with a fixed pattern
494 set_ccr_zero
495
496 mov #byte_dest+1, er0
497 shar.b #2, @-er0 ; shift right arithmetic by two, predec
498 ;;; .word 0x0177
499 ;;; .word 0x6c08
500 ;;; .word 0x11c0
501
502 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
503 test_zero_clear
504 test_ovf_clear
505 test_neg_set
506
507 test_h_gr32 byte_dest er0
508 test_gr_a5a5 1 ; Make sure other general regs not disturbed
509 test_gr_a5a5 2
510 test_gr_a5a5 3
511 test_gr_a5a5 4
512 test_gr_a5a5 5
513 test_gr_a5a5 6
514 test_gr_a5a5 7
515 ; 1010 0101 -> 1110 1001
516 cmp.b #0xe9, @byte_dest
517 beq .Lbpredec2
518 fail
519 .Lbpredec2:
520 mov.b #0xa5, @byte_dest
521
522 shar_b_disp2_2:
523 set_grs_a5a5 ; Fill all general regs with a fixed pattern
524 set_ccr_zero
525
526 mov #byte_dest-2, er0
527 shar.b #2, @(2:2, er0) ; shift right arithmetic by two, disp2
528 ;;; .word 0x0176
529 ;;; .word 0x6808
530 ;;; .word 0x11c0
531
532 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
533 test_zero_clear
534 test_ovf_clear
535 test_neg_set
536
537 test_h_gr32 byte_dest-2 er0
538 test_gr_a5a5 1 ; Make sure other general regs not disturbed
539 test_gr_a5a5 2
540 test_gr_a5a5 3
541 test_gr_a5a5 4
542 test_gr_a5a5 5
543 test_gr_a5a5 6
544 test_gr_a5a5 7
545 ; 1010 0101 -> 1110 1001
546 cmp.b #0xe9, @byte_dest
547 beq .Lbdisp22
548 fail
549 .Lbdisp22:
550 mov.b #0xa5, @byte_dest
551
552 shar_b_disp16_2:
553 set_grs_a5a5 ; Fill all general regs with a fixed pattern
554 set_ccr_zero
555
556 mov #byte_dest-44, er0
557 shar.b #2, @(44:16, er0) ; shift right arithmetic by two, disp16
558 ;;; .word 0x0174
559 ;;; .word 0x6e08
560 ;;; .word 44
561 ;;; .word 0x11c0
562
563 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
564 test_zero_clear
565 test_ovf_clear
566 test_neg_set
567
568 test_h_gr32 byte_dest-44 er0
569 test_gr_a5a5 1 ; Make sure other general regs not disturbed
570 test_gr_a5a5 2
571 test_gr_a5a5 3
572 test_gr_a5a5 4
573 test_gr_a5a5 5
574 test_gr_a5a5 6
575 test_gr_a5a5 7
576 ; 1010 0101 -> 1110 1001
577 cmp.b #0xe9, @byte_dest
578 beq .Lbdisp162
579 fail
580 .Lbdisp162:
581 mov.b #0xa5, @byte_dest
582
583 shar_b_disp32_2:
584 set_grs_a5a5 ; Fill all general regs with a fixed pattern
585 set_ccr_zero
586
587 mov #byte_dest-666, er0
588 shar.b #2, @(666:32, er0) ; shift right arithmetic by two, disp32
589 ;;; .word 0x7884
590 ;;; .word 0x6a28
591 ;;; .long 666
592 ;;; .word 0x11c0
593
594 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
595 test_zero_clear
596 test_ovf_clear
597 test_neg_set
598
599 test_h_gr32 byte_dest-666 er0
600 test_gr_a5a5 1 ; Make sure other general regs not disturbed
601 test_gr_a5a5 2
602 test_gr_a5a5 3
603 test_gr_a5a5 4
604 test_gr_a5a5 5
605 test_gr_a5a5 6
606 test_gr_a5a5 7
607 ; 1010 0101 -> 1110 1001
608 cmp.b #0xe9, @byte_dest
609 beq .Lbdisp322
610 fail
611 .Lbdisp322:
612 mov.b #0xa5, @byte_dest
613
614 shar_b_abs16_2:
615 set_grs_a5a5 ; Fill all general regs with a fixed pattern
616 set_ccr_zero
617
618 shar.b #2, @byte_dest:16 ; shift right arithmetic by two, abs16
619 ;;; .word 0x6a18
620 ;;; .word byte_dest
621 ;;; .word 0x11c0
622
623 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
624 test_zero_clear
625 test_ovf_clear
626 test_neg_set
627
628 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
629 test_gr_a5a5 2
630 test_gr_a5a5 2
631 test_gr_a5a5 3
632 test_gr_a5a5 4
633 test_gr_a5a5 5
634 test_gr_a5a5 6
635 test_gr_a5a5 7
636 ; 1010 0101 -> 1110 1001
637 cmp.b #0xe9, @byte_dest
638 beq .Lbabs162
639 fail
640 .Lbabs162:
641 mov.b #0xa5, @byte_dest
642
643 shar_b_abs32_2:
644 set_grs_a5a5 ; Fill all general regs with a fixed pattern
645 set_ccr_zero
646
647 shar.b #2, @byte_dest:32 ; shift right arithmetic by two, abs32
648 ;;; .word 0x6a38
649 ;;; .long byte_dest
650 ;;; .word 0x11c0
651
652 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
653 test_zero_clear
654 test_ovf_clear
655 test_neg_set
656
657 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
658 test_gr_a5a5 2
659 test_gr_a5a5 2
660 test_gr_a5a5 3
661 test_gr_a5a5 4
662 test_gr_a5a5 5
663 test_gr_a5a5 6
664 test_gr_a5a5 7
665 ; 1010 0101 -> 1110 1001
666 cmp.b #0xe9, @byte_dest
667 beq .Lbabs322
668 fail
669 .Lbabs322:
670 mov.b #0xa5, @byte_dest
671 .endif
672
673 .if (sim_cpu) ; Not available in h8300 mode
674 shar_w_reg16_1:
675 set_grs_a5a5 ; Fill all general regs with a fixed pattern
676 set_ccr_zero
677
678 shar.w r0 ; shift right arithmetic by one
679 ;;; .word 0x1190
680
681 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
682 test_zero_clear
683 test_ovf_clear
684 test_neg_set
685 test_h_gr16 0xd2d2 r0 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
686 test_h_gr32 0xa5a5d2d2 er0
687
688 test_gr_a5a5 1 ; Make sure other general regs not disturbed
689 test_gr_a5a5 2
690 test_gr_a5a5 3
691 test_gr_a5a5 4
692 test_gr_a5a5 5
693 test_gr_a5a5 6
694 test_gr_a5a5 7
695
696 .if (sim_cpu == h8sx)
697 shar_w_ind_1:
698 set_grs_a5a5 ; Fill all general regs with a fixed pattern
699 set_ccr_zero
700
701 mov #word_dest, er0
702 shar.w @er0 ; shift right arithmetic by one, indirect
703 ;;; .word 0x7d80
704 ;;; .word 0x1190
705
706 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
707 test_zero_clear
708 test_ovf_clear
709 test_neg_set
710
711 test_h_gr32 word_dest er0
712 test_gr_a5a5 1 ; Make sure other general regs not disturbed
713 test_gr_a5a5 2
714 test_gr_a5a5 3
715 test_gr_a5a5 4
716 test_gr_a5a5 5
717 test_gr_a5a5 6
718 test_gr_a5a5 7
719 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
720 cmp.w #0xd2d2, @word_dest
721 beq .Lwind1
722 fail
723 .Lwind1:
724 mov.w #0xa5a5, @word_dest
725
726 shar_w_postinc_1:
727 set_grs_a5a5 ; Fill all general regs with a fixed pattern
728 set_ccr_zero
729
730 mov #word_dest, er0
731 shar.w @er0+ ; shift right arithmetic by one, postinc
732 ;;; .word 0x0154
733 ;;; .word 0x6d08
734 ;;; .word 0x1190
735
736 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
737 test_zero_clear
738 test_ovf_clear
739 test_neg_set
740
741 test_h_gr32 word_dest+2 er0
742 test_gr_a5a5 1 ; Make sure other general regs not disturbed
743 test_gr_a5a5 2
744 test_gr_a5a5 3
745 test_gr_a5a5 4
746 test_gr_a5a5 5
747 test_gr_a5a5 6
748 test_gr_a5a5 7
749 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
750 cmp.w #0xd2d2, @word_dest
751 beq .Lwpostinc1
752 fail
753 .Lwpostinc1:
754 mov.w #0xa5a5, @word_dest
755
756 shar_w_postdec_1:
757 set_grs_a5a5 ; Fill all general regs with a fixed pattern
758 set_ccr_zero
759
760 mov #word_dest, er0
761 shar.w @er0- ; shift right arithmetic by one, postdec
762 ;;; .word 0x0156
763 ;;; .word 0x6d08
764 ;;; .word 0x1190
765
766 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
767 test_zero_clear
768 test_ovf_clear
769 test_neg_set
770
771 test_h_gr32 word_dest-2 er0
772 test_gr_a5a5 1 ; Make sure other general regs not disturbed
773 test_gr_a5a5 2
774 test_gr_a5a5 3
775 test_gr_a5a5 4
776 test_gr_a5a5 5
777 test_gr_a5a5 6
778 test_gr_a5a5 7
779 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
780 cmp.w #0xd2d2, @word_dest
781 beq .Lwpostdec1
782 fail
783 .Lwpostdec1:
784 mov.w #0xa5a5, @word_dest
785
786 shar_w_preinc_1:
787 set_grs_a5a5 ; Fill all general regs with a fixed pattern
788 set_ccr_zero
789
790 mov #word_dest-2, er0
791 shar.w @+er0 ; shift right arithmetic by one, preinc
792 ;;; .word 0x0155
793 ;;; .word 0x6d08
794 ;;; .word 0x1190
795
796 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
797 test_zero_clear
798 test_ovf_clear
799 test_neg_set
800
801 test_h_gr32 word_dest er0
802 test_gr_a5a5 1 ; Make sure other general regs not disturbed
803 test_gr_a5a5 2
804 test_gr_a5a5 3
805 test_gr_a5a5 4
806 test_gr_a5a5 5
807 test_gr_a5a5 6
808 test_gr_a5a5 7
809 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
810 cmp.w #0xd2d2, @word_dest
811 beq .Lwpreinc1
812 fail
813 .Lwpreinc1:
814 mov.w #0xa5a5, @word_dest
815
816 shar_w_predec_1:
817 set_grs_a5a5 ; Fill all general regs with a fixed pattern
818 set_ccr_zero
819
820 mov #word_dest+2, er0
821 shar.w @-er0 ; shift right arithmetic by one, predec
822 ;;; .word 0x0157
823 ;;; .word 0x6d08
824 ;;; .word 0x1190
825
826 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
827 test_zero_clear
828 test_ovf_clear
829 test_neg_set
830
831 test_h_gr32 word_dest er0
832 test_gr_a5a5 1 ; Make sure other general regs not disturbed
833 test_gr_a5a5 2
834 test_gr_a5a5 3
835 test_gr_a5a5 4
836 test_gr_a5a5 5
837 test_gr_a5a5 6
838 test_gr_a5a5 7
839 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
840 cmp.w #0xd2d2, @word_dest
841 beq .Lwpredec1
842 fail
843 .Lwpredec1:
844 mov.w #0xa5a5, @word_dest
845
846 shar_w_disp2_1:
847 set_grs_a5a5 ; Fill all general regs with a fixed pattern
848 set_ccr_zero
849
850 mov #word_dest-4, er0
851 shar.w @(4:2, er0) ; shift right arithmetic by one, disp2
852 ;;; .word 0x0156
853 ;;; .word 0x6908
854 ;;; .word 0x1190
855
856 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
857 test_zero_clear
858 test_ovf_clear
859 test_neg_set
860
861 test_h_gr32 word_dest-4 er0
862 test_gr_a5a5 1 ; Make sure other general regs not disturbed
863 test_gr_a5a5 2
864 test_gr_a5a5 3
865 test_gr_a5a5 4
866 test_gr_a5a5 5
867 test_gr_a5a5 6
868 test_gr_a5a5 7
869 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
870 cmp.w #0xd2d2, @word_dest
871 beq .Lwdisp21
872 fail
873 .Lwdisp21:
874 mov.w #0xa5a5, @word_dest
875
876 shar_w_disp16_1:
877 set_grs_a5a5 ; Fill all general regs with a fixed pattern
878 set_ccr_zero
879
880 mov #word_dest-44, er0
881 shar.w @(44:16, er0) ; shift right arithmetic by one, disp16
882 ;;; .word 0x0154
883 ;;; .word 0x6f08
884 ;;; .word 44
885 ;;; .word 0x1190
886
887 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
888 test_zero_clear
889 test_ovf_clear
890 test_neg_set
891
892 test_h_gr32 word_dest-44 er0
893 test_gr_a5a5 1 ; Make sure other general regs not disturbed
894 test_gr_a5a5 2
895 test_gr_a5a5 3
896 test_gr_a5a5 4
897 test_gr_a5a5 5
898 test_gr_a5a5 6
899 test_gr_a5a5 7
900 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
901 cmp.w #0xd2d2, @word_dest
902 beq .Lwdisp161
903 fail
904 .Lwdisp161:
905 mov.w #0xa5a5, @word_dest
906
907 shar_w_disp32_1:
908 set_grs_a5a5 ; Fill all general regs with a fixed pattern
909 set_ccr_zero
910
911 mov #word_dest-666, er0
912 shar.w @(666:32, er0) ; shift right arithmetic by one, disp32
913 ;;; .word 0x7884
914 ;;; .word 0x6b28
915 ;;; .long 666
916 ;;; .word 0x1190
917
918 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
919 test_zero_clear
920 test_ovf_clear
921 test_neg_set
922
923 test_h_gr32 word_dest-666 er0
924 test_gr_a5a5 1 ; Make sure other general regs not disturbed
925 test_gr_a5a5 2
926 test_gr_a5a5 3
927 test_gr_a5a5 4
928 test_gr_a5a5 5
929 test_gr_a5a5 6
930 test_gr_a5a5 7
931 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
932 cmp.w #0xd2d2, @word_dest
933 beq .Lwdisp321
934 fail
935 .Lwdisp321:
936 mov.w #0xa5a5, @word_dest
937
938 shar_w_abs16_1:
939 set_grs_a5a5 ; Fill all general regs with a fixed pattern
940 set_ccr_zero
941
942 shar.w @word_dest:16 ; shift right arithmetic by one, abs16
943 ;;; .word 0x6b18
944 ;;; .word word_dest
945 ;;; .word 0x1190
946
947 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
948 test_zero_clear
949 test_ovf_clear
950 test_neg_set
951
952 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
953 test_gr_a5a5 1
954 test_gr_a5a5 2
955 test_gr_a5a5 3
956 test_gr_a5a5 4
957 test_gr_a5a5 5
958 test_gr_a5a5 6
959 test_gr_a5a5 7
960 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
961 cmp.w #0xd2d2, @word_dest
962 beq .Lwabs161
963 fail
964 .Lwabs161:
965 mov.w #0xa5a5, @word_dest
966
967 shar_w_abs32_1:
968 set_grs_a5a5 ; Fill all general regs with a fixed pattern
969 set_ccr_zero
970
971 shar.w @word_dest:32 ; shift right arithmetic by one, abs32
972 ;;; .word 0x6b38
973 ;;; .long word_dest
974 ;;; .word 0x1190
975
976 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
977 test_zero_clear
978 test_ovf_clear
979 test_neg_set
980
981 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
982 test_gr_a5a5 1
983 test_gr_a5a5 2
984 test_gr_a5a5 3
985 test_gr_a5a5 4
986 test_gr_a5a5 5
987 test_gr_a5a5 6
988 test_gr_a5a5 7
989 ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
990 cmp.w #0xd2d2, @word_dest
991 beq .Lwabs321
992 fail
993 .Lwabs321:
994 mov.w #0xa5a5, @word_dest
995 .endif
996
997 shar_w_reg16_2:
998 set_grs_a5a5 ; Fill all general regs with a fixed pattern
999 set_ccr_zero
1000
1001 shar.w #2, r0 ; shift right arithmetic by two
1002 ;;; .word 0x11d0
1003
1004 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1005 test_zero_clear
1006 test_ovf_clear
1007 test_neg_set
1008
1009 test_h_gr16 0xe969 r0 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1010 test_h_gr32 0xa5a5e969 er0
1011 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1012 test_gr_a5a5 2
1013 test_gr_a5a5 3
1014 test_gr_a5a5 4
1015 test_gr_a5a5 5
1016 test_gr_a5a5 6
1017 test_gr_a5a5 7
1018
1019 .if (sim_cpu == h8sx)
1020 shar_w_ind_2:
1021 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1022 set_ccr_zero
1023
1024 mov #word_dest, er0
1025 shar.w #2, @er0 ; shift right arithmetic by two, indirect
1026 ;;; .word 0x7d80
1027 ;;; .word 0x11d0
1028
1029 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1030 test_zero_clear
1031 test_ovf_clear
1032 test_neg_set
1033
1034 test_h_gr32 word_dest er0
1035 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1036 test_gr_a5a5 2
1037 test_gr_a5a5 3
1038 test_gr_a5a5 4
1039 test_gr_a5a5 5
1040 test_gr_a5a5 6
1041 test_gr_a5a5 7
1042 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1043 cmp.w #0xe969, @word_dest
1044 beq .Lwind2
1045 fail
1046 .Lwind2:
1047 mov.w #0xa5a5, @word_dest
1048
1049 shar_w_postinc_2:
1050 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1051 set_ccr_zero
1052
1053 mov #word_dest, er0
1054 shar.w #2, @er0+ ; shift right arithmetic by two, postinc
1055 ;;; .word 0x0154
1056 ;;; .word 0x6d08
1057 ;;; .word 0x11d0
1058
1059 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1060 test_zero_clear
1061 test_ovf_clear
1062 test_neg_set
1063
1064 test_h_gr32 word_dest+2 er0
1065 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1066 test_gr_a5a5 2
1067 test_gr_a5a5 3
1068 test_gr_a5a5 4
1069 test_gr_a5a5 5
1070 test_gr_a5a5 6
1071 test_gr_a5a5 7
1072 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1073 cmp.w #0xe969, @word_dest
1074 beq .Lwpostinc2
1075 fail
1076 .Lwpostinc2:
1077 mov.w #0xa5a5, @word_dest
1078
1079 shar_w_postdec_2:
1080 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1081 set_ccr_zero
1082
1083 mov #word_dest, er0
1084 shar.w #2, @er0- ; shift right arithmetic by two, postdec
1085 ;;; .word 0x0156
1086 ;;; .word 0x6d08
1087 ;;; .word 0x11d0
1088
1089 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1090 test_zero_clear
1091 test_ovf_clear
1092 test_neg_set
1093
1094 test_h_gr32 word_dest-2 er0
1095 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1096 test_gr_a5a5 2
1097 test_gr_a5a5 3
1098 test_gr_a5a5 4
1099 test_gr_a5a5 5
1100 test_gr_a5a5 6
1101 test_gr_a5a5 7
1102 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1103 cmp.w #0xe969, @word_dest
1104 beq .Lwpostdec2
1105 fail
1106 .Lwpostdec2:
1107 mov.w #0xa5a5, @word_dest
1108
1109 shar_w_preinc_2:
1110 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1111 set_ccr_zero
1112
1113 mov #word_dest-2, er0
1114 shar.w #2, @+er0 ; shift right arithmetic by two, preinc
1115 ;;; .word 0x0155
1116 ;;; .word 0x6d08
1117 ;;; .word 0x11d0
1118
1119 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1120 test_zero_clear
1121 test_ovf_clear
1122 test_neg_set
1123
1124 test_h_gr32 word_dest er0
1125 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1126 test_gr_a5a5 2
1127 test_gr_a5a5 3
1128 test_gr_a5a5 4
1129 test_gr_a5a5 5
1130 test_gr_a5a5 6
1131 test_gr_a5a5 7
1132 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1133 cmp.w #0xe969, @word_dest
1134 beq .Lwpreinc2
1135 fail
1136 .Lwpreinc2:
1137 mov.w #0xa5a5, @word_dest
1138
1139 shar_w_predec_2:
1140 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1141 set_ccr_zero
1142
1143 mov #word_dest+2, er0
1144 shar.w #2, @-er0 ; shift right arithmetic by two, predec
1145 ;;; .word 0x0157
1146 ;;; .word 0x6d08
1147 ;;; .word 0x11d0
1148
1149 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1150 test_zero_clear
1151 test_ovf_clear
1152 test_neg_set
1153
1154 test_h_gr32 word_dest er0
1155 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1156 test_gr_a5a5 2
1157 test_gr_a5a5 3
1158 test_gr_a5a5 4
1159 test_gr_a5a5 5
1160 test_gr_a5a5 6
1161 test_gr_a5a5 7
1162 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1163 cmp.w #0xe969, @word_dest
1164 beq .Lwpredec2
1165 fail
1166 .Lwpredec2:
1167 mov.w #0xa5a5, @word_dest
1168
1169 shar_w_disp2_2:
1170 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1171 set_ccr_zero
1172
1173 mov #word_dest-4, er0
1174 shar.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2
1175 ;;; .word 0x0156
1176 ;;; .word 0x6908
1177 ;;; .word 0x11d0
1178
1179 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1180 test_zero_clear
1181 test_ovf_clear
1182 test_neg_set
1183
1184 test_h_gr32 word_dest-4 er0
1185 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1186 test_gr_a5a5 2
1187 test_gr_a5a5 3
1188 test_gr_a5a5 4
1189 test_gr_a5a5 5
1190 test_gr_a5a5 6
1191 test_gr_a5a5 7
1192 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1193 cmp.w #0xe969, @word_dest
1194 beq .Lwdisp22
1195 fail
1196 .Lwdisp22:
1197 mov.w #0xa5a5, @word_dest
1198
1199 shar_w_disp16_2:
1200 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1201 set_ccr_zero
1202
1203 mov #word_dest-44, er0
1204 shar.w #2, @(44:16, er0) ; shift right arithmetic by two, disp16
1205 ;;; .word 0x0154
1206 ;;; .word 0x6f08
1207 ;;; .word 44
1208 ;;; .word 0x11d0
1209
1210 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1211 test_zero_clear
1212 test_ovf_clear
1213 test_neg_set
1214
1215 test_h_gr32 word_dest-44 er0
1216 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1217 test_gr_a5a5 2
1218 test_gr_a5a5 3
1219 test_gr_a5a5 4
1220 test_gr_a5a5 5
1221 test_gr_a5a5 6
1222 test_gr_a5a5 7
1223 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1224 cmp.w #0xe969, @word_dest
1225 beq .Lwdisp162
1226 fail
1227 .Lwdisp162:
1228 mov.w #0xa5a5, @word_dest
1229
1230 shar_w_disp32_2:
1231 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1232 set_ccr_zero
1233
1234 mov #word_dest-666, er0
1235 shar.w #2, @(666:32, er0) ; shift right arithmetic by two, disp32
1236 ;;; .word 0x7884
1237 ;;; .word 0x6b28
1238 ;;; .long 666
1239 ;;; .word 0x11d0
1240
1241 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1242 test_zero_clear
1243 test_ovf_clear
1244 test_neg_set
1245
1246 test_h_gr32 word_dest-666 er0
1247 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1248 test_gr_a5a5 2
1249 test_gr_a5a5 3
1250 test_gr_a5a5 4
1251 test_gr_a5a5 5
1252 test_gr_a5a5 6
1253 test_gr_a5a5 7
1254 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1255 cmp.w #0xe969, @word_dest
1256 beq .Lwdisp322
1257 fail
1258 .Lwdisp322:
1259 mov.w #0xa5a5, @word_dest
1260
1261 shar_w_abs16_2:
1262 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1263 set_ccr_zero
1264
1265 shar.w #2, @word_dest:16 ; shift right arithmetic by two, abs16
1266 ;;; .word 0x6b18
1267 ;;; .word word_dest
1268 ;;; .word 0x11d0
1269
1270 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1271 test_zero_clear
1272 test_ovf_clear
1273 test_neg_set
1274
1275 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1276 test_gr_a5a5 2
1277 test_gr_a5a5 2
1278 test_gr_a5a5 3
1279 test_gr_a5a5 4
1280 test_gr_a5a5 5
1281 test_gr_a5a5 6
1282 test_gr_a5a5 7
1283 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1284 cmp.w #0xe969, @word_dest
1285 beq .Lwabs162
1286 fail
1287 .Lwabs162:
1288 mov.w #0xa5a5, @word_dest
1289
1290 shar_w_abs32_2:
1291 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1292 set_ccr_zero
1293
1294 shar.w #2, @word_dest:32 ; shift right arithmetic by two, abs32
1295 ;;; .word 0x6b38
1296 ;;; .long word_dest
1297 ;;; .word 0x11d0
1298
1299 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1300 test_zero_clear
1301 test_ovf_clear
1302 test_neg_set
1303
1304 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1305 test_gr_a5a5 2
1306 test_gr_a5a5 2
1307 test_gr_a5a5 3
1308 test_gr_a5a5 4
1309 test_gr_a5a5 5
1310 test_gr_a5a5 6
1311 test_gr_a5a5 7
1312 ; 1010 0101 1010 0101 -> 1110 1001 0110 1001
1313 cmp.w #0xe969, @word_dest
1314 beq .Lwabs322
1315 fail
1316 .Lwabs322:
1317 mov.w #0xa5a5, @word_dest
1318 .endif
1319
1320 shar_l_reg32_1:
1321 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1322 set_ccr_zero
1323
1324 shar.l er0 ; shift right arithmetic by one, register
1325 ;;; .word 0x11b0
1326
1327 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1328 test_zero_clear
1329 test_ovf_clear
1330 test_neg_set
1331
1332 ; 1010 0101 1010 0101 1010 0101 1010 0101
1333 ; -> 1101 0010 1101 0010 1101 0010 1101 0010
1334 test_h_gr32 0xd2d2d2d2 er0
1335
1336 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1337 test_gr_a5a5 2
1338 test_gr_a5a5 3
1339 test_gr_a5a5 4
1340 test_gr_a5a5 5
1341 test_gr_a5a5 6
1342 test_gr_a5a5 7
1343
1344 .if (sim_cpu == h8sx)
1345 shar_l_ind_1:
1346 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1347 set_ccr_zero
1348
1349 mov #long_dest, er0
1350 shar.l @er0 ; shift right arithmetic by one, indirect
1351 ;;; .word 0x0104
1352 ;;; .word 0x6908
1353 ;;; .word 0x11b0
1354
1355 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1356 test_zero_clear
1357 test_ovf_clear
1358 test_neg_set
1359
1360 test_h_gr32 long_dest er0
1361 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1362 test_gr_a5a5 2
1363 test_gr_a5a5 3
1364 test_gr_a5a5 4
1365 test_gr_a5a5 5
1366 test_gr_a5a5 6
1367 test_gr_a5a5 7
1368 ; 1010 0101 1010 0101 1010 0101 1010 0101
1369 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1370 cmp.l #0xd2d2d2d2, @long_dest
1371 beq .Llind1
1372 fail
1373 .Llind1:
1374 mov #0xa5a5a5a5, @long_dest
1375
1376 shar_l_postinc_1:
1377 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1378 set_ccr_zero
1379
1380 mov #long_dest, er0
1381 shar.l @er0+ ; shift right arithmetic by one, postinc
1382 ;;; .word 0x0104
1383 ;;; .word 0x6d08
1384 ;;; .word 0x11b0
1385
1386 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1387 test_zero_clear
1388 test_ovf_clear
1389 test_neg_set
1390
1391 test_h_gr32 long_dest+4 er0
1392 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1393 test_gr_a5a5 2
1394 test_gr_a5a5 3
1395 test_gr_a5a5 4
1396 test_gr_a5a5 5
1397 test_gr_a5a5 6
1398 test_gr_a5a5 7
1399 ; 1010 0101 1010 0101 1010 0101 1010 0101
1400 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1401 cmp.l #0xd2d2d2d2, @long_dest
1402 beq .Llpostinc1
1403 fail
1404 .Llpostinc1:
1405 mov #0xa5a5a5a5, @long_dest
1406
1407 shar_l_postdec_1:
1408 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1409 set_ccr_zero
1410
1411 mov #long_dest, er0
1412 shar.l @er0- ; shift right arithmetic by one, postdec
1413 ;;; .word 0x0106
1414 ;;; .word 0x6d08
1415 ;;; .word 0x11b0
1416
1417 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1418 test_zero_clear
1419 test_ovf_clear
1420 test_neg_set
1421
1422 test_h_gr32 long_dest-4 er0
1423 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1424 test_gr_a5a5 2
1425 test_gr_a5a5 3
1426 test_gr_a5a5 4
1427 test_gr_a5a5 5
1428 test_gr_a5a5 6
1429 test_gr_a5a5 7
1430 ; 1010 0101 1010 0101 1010 0101 1010 0101
1431 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1432 cmp.l #0xd2d2d2d2, @long_dest
1433 beq .Llpostdec1
1434 fail
1435 .Llpostdec1:
1436 mov #0xa5a5a5a5, @long_dest
1437
1438 shar_l_preinc_1:
1439 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1440 set_ccr_zero
1441
1442 mov #long_dest-4, er0
1443 shar.l @+er0 ; shift right arithmetic by one, preinc
1444 ;;; .word 0x0105
1445 ;;; .word 0x6d08
1446 ;;; .word 0x11b0
1447
1448 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1449 test_zero_clear
1450 test_ovf_clear
1451 test_neg_set
1452
1453 test_h_gr32 long_dest er0
1454 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1455 test_gr_a5a5 2
1456 test_gr_a5a5 3
1457 test_gr_a5a5 4
1458 test_gr_a5a5 5
1459 test_gr_a5a5 6
1460 test_gr_a5a5 7
1461 ; 1010 0101 1010 0101 1010 0101 1010 0101
1462 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1463 cmp.l #0xd2d2d2d2, @long_dest
1464 beq .Llpreinc1
1465 fail
1466 .Llpreinc1:
1467 mov #0xa5a5a5a5, @long_dest
1468
1469 shar_l_predec_1:
1470 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1471 set_ccr_zero
1472
1473 mov #long_dest+4, er0
1474 shar.l @-er0 ; shift right arithmetic by one, predec
1475 ;;; .word 0x0107
1476 ;;; .word 0x6d08
1477 ;;; .word 0x11b0
1478
1479 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1480 test_zero_clear
1481 test_ovf_clear
1482 test_neg_set
1483
1484 test_h_gr32 long_dest er0
1485 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1486 test_gr_a5a5 2
1487 test_gr_a5a5 3
1488 test_gr_a5a5 4
1489 test_gr_a5a5 5
1490 test_gr_a5a5 6
1491 test_gr_a5a5 7
1492 ; 1010 0101 1010 0101 1010 0101 1010 0101
1493 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1494 cmp.l #0xd2d2d2d2, @long_dest
1495 beq .Llpredec1
1496 fail
1497 .Llpredec1:
1498 mov #0xa5a5a5a5, @long_dest
1499
1500 shar_l_disp2_1:
1501 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1502 set_ccr_zero
1503
1504 mov #long_dest-8, er0
1505 shar.l @(8:2, er0) ; shift right arithmetic by one, disp2
1506 ;;; .word 0x0106
1507 ;;; .word 0x6908
1508 ;;; .word 0x11b0
1509
1510 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1511 test_zero_clear
1512 test_ovf_clear
1513 test_neg_set
1514
1515 test_h_gr32 long_dest-8 er0
1516 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1517 test_gr_a5a5 2
1518 test_gr_a5a5 3
1519 test_gr_a5a5 4
1520 test_gr_a5a5 5
1521 test_gr_a5a5 6
1522 test_gr_a5a5 7
1523 ; 1010 0101 1010 0101 1010 0101 1010 0101
1524 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1525 cmp.l #0xd2d2d2d2, @long_dest
1526 beq .Lldisp21
1527 fail
1528 .Lldisp21:
1529 mov #0xa5a5a5a5, @long_dest
1530
1531 shar_l_disp16_1:
1532 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1533 set_ccr_zero
1534
1535 mov #long_dest-44, er0
1536 shar.l @(44:16, er0) ; shift right arithmetic by one, disp16
1537 ;;; .word 0x0104
1538 ;;; .word 0x6f08
1539 ;;; .word 44
1540 ;;; .word 0x11b0
1541
1542 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1543 test_zero_clear
1544 test_ovf_clear
1545 test_neg_set
1546
1547 test_h_gr32 long_dest-44 er0
1548 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1549 test_gr_a5a5 2
1550 test_gr_a5a5 3
1551 test_gr_a5a5 4
1552 test_gr_a5a5 5
1553 test_gr_a5a5 6
1554 test_gr_a5a5 7
1555 ; 1010 0101 1010 0101 1010 0101 1010 0101
1556 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1557 cmp.l #0xd2d2d2d2, @long_dest
1558 beq .Lldisp161
1559 fail
1560 .Lldisp161:
1561 mov #0xa5a5a5a5, @long_dest
1562
1563 shar_l_disp32_1:
1564 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1565 set_ccr_zero
1566
1567 mov #long_dest-666, er0
1568 shar.l @(666:32, er0) ; shift right arithmetic by one, disp32
1569 ;;; .word 0x7884
1570 ;;; .word 0x6b28
1571 ;;; .long 666
1572 ;;; .word 0x11b0
1573
1574 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1575 test_zero_clear
1576 test_ovf_clear
1577 test_neg_set
1578
1579 test_h_gr32 long_dest-666 er0
1580 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1581 test_gr_a5a5 2
1582 test_gr_a5a5 3
1583 test_gr_a5a5 4
1584 test_gr_a5a5 5
1585 test_gr_a5a5 6
1586 test_gr_a5a5 7
1587 ; 1010 0101 1010 0101 1010 0101 1010 0101
1588 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1589 cmp.l #0xd2d2d2d2, @long_dest
1590 beq .Lldisp321
1591 fail
1592 .Lldisp321:
1593 mov #0xa5a5a5a5, @long_dest
1594
1595 shar_l_abs16_1:
1596 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1597 set_ccr_zero
1598
1599 shar.l @long_dest:16 ; shift right arithmetic by one, abs16
1600 ;;; .word 0x0104
1601 ;;; .word 0x6b08
1602 ;;; .word long_dest
1603 ;;; .word 0x11b0
1604
1605 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1606 test_zero_clear
1607 test_ovf_clear
1608 test_neg_set
1609
1610 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1611 test_gr_a5a5 1
1612 test_gr_a5a5 2
1613 test_gr_a5a5 3
1614 test_gr_a5a5 4
1615 test_gr_a5a5 5
1616 test_gr_a5a5 6
1617 test_gr_a5a5 7
1618 ; 1010 0101 1010 0101 1010 0101 1010 0101
1619 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1620 cmp.l #0xd2d2d2d2, @long_dest
1621 beq .Llabs161
1622 fail
1623 .Llabs161:
1624 mov #0xa5a5a5a5, @long_dest
1625
1626 shar_l_abs32_1:
1627 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1628 set_ccr_zero
1629
1630 shar.l @long_dest:32 ; shift right arithmetic by one, abs32
1631 ;;; .word 0x0104
1632 ;;; .word 0x6b28
1633 ;;; .long long_dest
1634 ;;; .word 0x11b0
1635
1636 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1637 test_zero_clear
1638 test_ovf_clear
1639 test_neg_set
1640
1641 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1642 test_gr_a5a5 1
1643 test_gr_a5a5 2
1644 test_gr_a5a5 3
1645 test_gr_a5a5 4
1646 test_gr_a5a5 5
1647 test_gr_a5a5 6
1648 test_gr_a5a5 7
1649 ; 1010 0101 1010 0101 1010 0101 1010 0101
1650 ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1651 cmp.l #0xd2d2d2d2, @long_dest
1652 beq .Llabs321
1653 fail
1654 .Llabs321:
1655 mov #0xa5a5a5a5, @long_dest
1656 .endif
1657
1658 shar_l_reg32_2:
1659 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1660 set_ccr_zero
1661
1662 shar.l #2, er0 ; shift right arithmetic by two, register
1663 ;;; .word 0x11f0
1664
1665 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1666 test_zero_clear
1667 test_ovf_clear
1668 test_neg_set
1669 ; 1010 0101 1010 0101 1010 0101 1010 0101
1670 ; -> 1110 1001 0110 1001 0110 1001 0110 1001
1671 test_h_gr32 0xe9696969 er0
1672
1673 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1674 test_gr_a5a5 2
1675 test_gr_a5a5 3
1676 test_gr_a5a5 4
1677 test_gr_a5a5 5
1678 test_gr_a5a5 6
1679 test_gr_a5a5 7
1680
1681 .if (sim_cpu == h8sx)
1682
1683 shar_l_ind_2:
1684 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1685 set_ccr_zero
1686
1687 mov #long_dest, er0
1688 shar.l #2, @er0 ; shift right arithmetic by two, indirect
1689 ;;; .word 0x0104
1690 ;;; .word 0x6908
1691 ;;; .word 0x11f0
1692
1693 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1694 test_zero_clear
1695 test_ovf_clear
1696 test_neg_set
1697
1698 test_h_gr32 long_dest er0
1699 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1700 test_gr_a5a5 2
1701 test_gr_a5a5 3
1702 test_gr_a5a5 4
1703 test_gr_a5a5 5
1704 test_gr_a5a5 6
1705 test_gr_a5a5 7
1706 ; 1010 0101 1010 0101 1010 0101 1010 0101
1707 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1708 cmp.l #0xe9696969, @long_dest
1709 beq .Llind2
1710 fail
1711 .Llind2:
1712 mov #0xa5a5a5a5, @long_dest
1713
1714 shar_l_postinc_2:
1715 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1716 set_ccr_zero
1717
1718 mov #long_dest, er0
1719 shar.l #2, @er0+ ; shift right arithmetic by two, postinc
1720 ;;; .word 0x0104
1721 ;;; .word 0x6d08
1722 ;;; .word 0x11f0
1723
1724 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1725 test_zero_clear
1726 test_ovf_clear
1727 test_neg_set
1728
1729 test_h_gr32 long_dest+4 er0
1730 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1731 test_gr_a5a5 2
1732 test_gr_a5a5 3
1733 test_gr_a5a5 4
1734 test_gr_a5a5 5
1735 test_gr_a5a5 6
1736 test_gr_a5a5 7
1737 ; 1010 0101 1010 0101 1010 0101 1010 0101
1738 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1739 cmp.l #0xe9696969, @long_dest
1740 beq .Llpostinc2
1741 fail
1742 .Llpostinc2:
1743 mov #0xa5a5a5a5, @long_dest
1744
1745 shar_l_postdec_2:
1746 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1747 set_ccr_zero
1748
1749 mov #long_dest, er0
1750 shar.l #2, @er0- ; shift right arithmetic by two, postdec
1751 ;;; .word 0x0106
1752 ;;; .word 0x6d08
1753 ;;; .word 0x11f0
1754
1755 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1756 test_zero_clear
1757 test_ovf_clear
1758 test_neg_set
1759
1760 test_h_gr32 long_dest-4 er0
1761 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1762 test_gr_a5a5 2
1763 test_gr_a5a5 3
1764 test_gr_a5a5 4
1765 test_gr_a5a5 5
1766 test_gr_a5a5 6
1767 test_gr_a5a5 7
1768 ; 1010 0101 1010 0101 1010 0101 1010 0101
1769 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1770 cmp.l #0xe9696969, @long_dest
1771 beq .Llpostdec2
1772 fail
1773 .Llpostdec2:
1774 mov #0xa5a5a5a5, @long_dest
1775
1776 shar_l_preinc_2:
1777 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1778 set_ccr_zero
1779
1780 mov #long_dest-4, er0
1781 shar.l #2, @+er0 ; shift right arithmetic by two, preinc
1782 ;;; .word 0x0105
1783 ;;; .word 0x6d08
1784 ;;; .word 0x11f0
1785
1786 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1787 test_zero_clear
1788 test_ovf_clear
1789 test_neg_set
1790
1791 test_h_gr32 long_dest er0
1792 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1793 test_gr_a5a5 2
1794 test_gr_a5a5 3
1795 test_gr_a5a5 4
1796 test_gr_a5a5 5
1797 test_gr_a5a5 6
1798 test_gr_a5a5 7
1799 ; 1010 0101 1010 0101 1010 0101 1010 0101
1800 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1801 cmp.l #0xe9696969, @long_dest
1802 beq .Llpreinc2
1803 fail
1804 .Llpreinc2:
1805 mov #0xa5a5a5a5, @long_dest
1806
1807 shar_l_predec_2:
1808 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1809 set_ccr_zero
1810
1811 mov #long_dest+4, er0
1812 shar.l #2, @-er0 ; shift right arithmetic by two, predec
1813 ;;; .word 0x0107
1814 ;;; .word 0x6d08
1815 ;;; .word 0x11f0
1816
1817 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1818 test_zero_clear
1819 test_ovf_clear
1820 test_neg_set
1821
1822 test_h_gr32 long_dest er0
1823 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1824 test_gr_a5a5 2
1825 test_gr_a5a5 3
1826 test_gr_a5a5 4
1827 test_gr_a5a5 5
1828 test_gr_a5a5 6
1829 test_gr_a5a5 7
1830 ; 1010 0101 1010 0101 1010 0101 1010 0101
1831 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1832 cmp.l #0xe9696969, @long_dest
1833 beq .Llpredec2
1834 fail
1835 .Llpredec2:
1836 mov #0xa5a5a5a5, @long_dest
1837
1838 shar_l_disp2_2:
1839 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1840 set_ccr_zero
1841
1842 mov #long_dest-8, er0
1843 shar.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2
1844 ;;; .word 0x0106
1845 ;;; .word 0x6908
1846 ;;; .word 0x11f0
1847
1848 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1849 test_zero_clear
1850 test_ovf_clear
1851 test_neg_set
1852
1853 test_h_gr32 long_dest-8 er0
1854 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1855 test_gr_a5a5 2
1856 test_gr_a5a5 3
1857 test_gr_a5a5 4
1858 test_gr_a5a5 5
1859 test_gr_a5a5 6
1860 test_gr_a5a5 7
1861 ; 1010 0101 1010 0101 1010 0101 1010 0101
1862 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1863 cmp.l #0xe9696969, @long_dest
1864 beq .Lldisp22
1865 fail
1866 .Lldisp22:
1867 mov #0xa5a5a5a5, @long_dest
1868
1869 shar_l_disp16_2:
1870 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1871 set_ccr_zero
1872
1873 mov #long_dest-44, er0
1874 shar.l #2, @(44:16, er0) ; shift right arithmetic by two, disp16
1875 ;;; .word 0x0104
1876 ;;; .word 0x6f08
1877 ;;; .word 44
1878 ;;; .word 0x11f0
1879
1880 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1881 test_zero_clear
1882 test_ovf_clear
1883 test_neg_set
1884
1885 test_h_gr32 long_dest-44 er0
1886 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1887 test_gr_a5a5 2
1888 test_gr_a5a5 3
1889 test_gr_a5a5 4
1890 test_gr_a5a5 5
1891 test_gr_a5a5 6
1892 test_gr_a5a5 7
1893 ; 1010 0101 1010 0101 1010 0101 1010 0101
1894 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1895 cmp.l #0xe9696969, @long_dest
1896 beq .Lldisp162
1897 fail
1898 .Lldisp162:
1899 mov #0xa5a5a5a5, @long_dest
1900
1901 shar_l_disp32_2:
1902 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1903 set_ccr_zero
1904
1905 mov #long_dest-666, er0
1906 shar.l #2, @(666:32, er0) ; shift right arithmetic by two, disp32
1907 ;;; .word 0x7884
1908 ;;; .word 0x6b28
1909 ;;; .long 666
1910 ;;; .word 0x11f0
1911
1912 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1913 test_zero_clear
1914 test_ovf_clear
1915 test_neg_set
1916
1917 test_h_gr32 long_dest-666 er0
1918 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1919 test_gr_a5a5 2
1920 test_gr_a5a5 3
1921 test_gr_a5a5 4
1922 test_gr_a5a5 5
1923 test_gr_a5a5 6
1924 test_gr_a5a5 7
1925 ; 1010 0101 1010 0101 1010 0101 1010 0101
1926 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1927 cmp.l #0xe9696969, @long_dest
1928 beq .Lldisp322
1929 fail
1930 .Lldisp322:
1931 mov #0xa5a5a5a5, @long_dest
1932
1933 shar_l_abs16_2:
1934 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1935 set_ccr_zero
1936
1937 shar.l #2, @long_dest:16 ; shift right arithmetic by two, abs16
1938 ;;; .word 0x0104
1939 ;;; .word 0x6b08
1940 ;;; .word long_dest
1941 ;;; .word 0x11f0
1942
1943 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1944 test_zero_clear
1945 test_ovf_clear
1946 test_neg_set
1947
1948 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1949 test_gr_a5a5 1
1950 test_gr_a5a5 2
1951 test_gr_a5a5 3
1952 test_gr_a5a5 4
1953 test_gr_a5a5 5
1954 test_gr_a5a5 6
1955 test_gr_a5a5 7
1956 ; 1010 0101 1010 0101 1010 0101 1010 0101
1957 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1958 cmp.l #0xe9696969, @long_dest
1959 beq .Llabs162
1960 fail
1961 .Llabs162:
1962 mov #0xa5a5a5a5, @long_dest
1963
1964 shar_l_abs32_2:
1965 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1966 set_ccr_zero
1967
1968 shar.l #2, @long_dest:32 ; shift right arithmetic by two, abs32
1969 ;;; .word 0x0104
1970 ;;; .word 0x6b28
1971 ;;; .long long_dest
1972 ;;; .word 0x11f0
1973
1974 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1975 test_zero_clear
1976 test_ovf_clear
1977 test_neg_set
1978
1979 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
1980 test_gr_a5a5 1
1981 test_gr_a5a5 2
1982 test_gr_a5a5 3
1983 test_gr_a5a5 4
1984 test_gr_a5a5 5
1985 test_gr_a5a5 6
1986 test_gr_a5a5 7
1987 ; 1010 0101 1010 0101 1010 0101 1010 0101
1988 ;; -> 1110 1001 0110 1001 0110 1001 0110 1001
1989 cmp.l #0xe9696969, @long_dest
1990 beq .Llabs322
1991 fail
1992 .Llabs322:
1993 mov #0xa5a5a5a5, @long_dest
1994
1995 .endif
1996 .endif
1997 pass
1998
1999 exit 0
2000