sim/testsuite/h8300/subw.s

   1 # Hitachi H8 testcase 'sub.w'
   2 # mach(): all
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12
  13         start
  14 .if (sim_cpu == h8sx)           ; 3-bit immediate mode only for h8sx
  15 sub_w_imm3:                     ; sub.w immediate not available in h8300 mode.
  16         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  17         ;;  fixme set ccr
  18
  19         ;;  sub.w #xx:3,Rd      ; Immediate 3-bit operand
  20         sub.w   #7:3, r0
  21
  22         ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
  23         test_h_gr16 0xa59e r0   ; sub result:   a5a5 - 7
  24         test_h_gr32 0xa5a5a59e er0      ; sub result:   a5a5 - 7
  25         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  26         test_gr_a5a5 2
  27         test_gr_a5a5 3
  28         test_gr_a5a5 4
  29         test_gr_a5a5 5
  30         test_gr_a5a5 6
  31         test_gr_a5a5 7
  32 .endif
  33
  34 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
  35 sub_w_imm16:                    ; sub.w immediate not available in h8300 mode.
  36         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  37         ;;  fixme set ccr
  38
  39         ;;  sub.w #xx:16,Rd
  40         sub.w   #0x111, r0      ; Immediate 16-bit operand
  41
  42         ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
  43         test_h_gr16 0xa494 r0   ; sub result:   a5a5 - 111
  44         test_h_gr32 0xa5a5a494 er0      ; sub result:   a5a5 - 111
  45         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  46         test_gr_a5a5 2
  47         test_gr_a5a5 3
  48         test_gr_a5a5 4
  49         test_gr_a5a5 5
  50         test_gr_a5a5 6
  51         test_gr_a5a5 7
  52 .endif
  53
  54 sub.w.reg:
  55         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  56         ;;  fixme set ccr
  57
  58         ;;  sub.w Rs,Rd
  59         mov.w   #0x111, r1
  60         sub.w   r1, r0          ; Register operand
  61
  62         ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
  63         test_h_gr16 0xa494 r0   ; sub result:   a5a5 - 111
  64         test_h_gr16 0x0111 r1
  65 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
  66         test_h_gr32 0xa5a5a494 er0      ; sub result:   a5a5 - 111
  67         test_h_gr32 0xa5a50111 er1
  68 .endif
  69         test_gr_a5a5 2          ; Make sure other general regs not disturbed
  70         test_gr_a5a5 3
  71         test_gr_a5a5 4
  72         test_gr_a5a5 5
  73         test_gr_a5a5 6
  74         test_gr_a5a5 7
  75
  76         pass
  77
  78         exit 0