sim/testsuite/sh/fsub.s

   1 # sh testcase for fsub
   2 # mach: sh
   3 # as(sh):       -defsym sim_cpu=0
   4
   5         .include "testutils.inc"
   6
   7         start
   8 fsub_single:
   9         set_grs_a5a5
  10         set_fprs_a5a5
  11         # 0.0 - 0.0 = 0.0.
  12         fldi0   fr0
  13         fldi0   fr1
  14         fsub    fr0, fr1
  15         fldi0   fr2
  16         fcmp/eq fr1, fr2
  17         bt      .L0
  18         fail
  19 .L0:
  20         # 1.0 - 0.0 = 1.0.
  21         fldi0   fr0
  22         fldi1   fr1
  23         fsub    fr0, fr1
  24         fldi1   fr2
  25         fcmp/eq fr1, fr2
  26         bt      .L1
  27         fail
  28 .L1:
  29         # 1.0 - 1.0 = 0.0.
  30         fldi1   fr0
  31         fldi1   fr1
  32         fsub    fr0, fr1
  33         fldi0   fr2
  34         fcmp/eq fr1, fr2
  35         bt      .L2
  36         fail
  37 .L2:
  38         # 0.0 - 1.0 = -1.0.
  39         fldi1   fr0
  40         fldi0   fr1
  41         fsub    fr0, fr1
  42         fldi1   fr2
  43         fneg    fr2
  44         fcmp/eq fr1, fr2
  45         bt      .L3
  46         fail
  47 .L3:
  48         test_grs_a5a5
  49         assert_fpreg_i   1, fr0
  50         assert_fpreg_i  -1, fr1
  51         assert_fpreg_i  -1, fr2
  52         test_fpr_a5a5   fr3
  53         test_fpr_a5a5   fr4
  54         test_fpr_a5a5   fr5
  55         test_fpr_a5a5   fr6
  56         test_fpr_a5a5   fr7
  57         test_fpr_a5a5   fr8
  58         test_fpr_a5a5   fr9
  59         test_fpr_a5a5   fr10
  60         test_fpr_a5a5   fr11
  61         test_fpr_a5a5   fr12
  62         test_fpr_a5a5   fr13
  63         test_fpr_a5a5   fr14
  64         test_fpr_a5a5   fr15
  65
  66 fsub_double:
  67         set_grs_a5a5
  68         set_fprs_a5a5
  69         double_prec
  70         # 0.0 - 0.0 = 0.0.
  71         fldi0   fr0
  72         fldi0   fr2
  73         _s2d    fr0, dr0
  74         _s2d    fr2, dr2
  75         fsub    dr0, dr2
  76         fldi0   fr4
  77         _s2d    fr4, dr4
  78         fcmp/eq dr2, dr4
  79         bt      .L10
  80         fail
  81 .L10:
  82         # 1.0 - 0.0 = 1.0.
  83         fldi0   fr0
  84         fldi1   fr2
  85         _s2d    fr0, dr0
  86         _s2d    fr2, dr2
  87         fsub    dr0, dr2
  88         fldi1   fr4
  89         _s2d    fr4, dr4
  90         fcmp/eq dr2, dr4
  91         bt      .L11
  92         fail
  93 .L11:
  94         # 1.0 - 1.0 = 0.0.
  95         fldi1   fr0
  96         fldi1   fr2
  97         _s2d    fr0, dr0
  98         _s2d    fr2, dr2
  99         fsub    dr0, dr2
 100         fldi0   fr4
 101         _s2d    fr4, dr4
 102         fcmp/eq dr2, dr4
 103         bt      .L12
 104         fail
 105 .L12:
 106         # 0.0 - 1.0 = -1.0.
 107         fldi1   fr0
 108         fldi0   fr2
 109         _s2d    fr0, dr0
 110         _s2d    fr2, dr2
 111         fsub    dr0, dr2
 112         fldi1   fr4
 113         single_prec
 114         fneg    fr4
 115         double_prec
 116         _s2d    fr4, dr4
 117         fcmp/eq dr2, dr4
 118         bt      .L13
 119         fail
 120 .L13:
 121         test_grs_a5a5
 122         assert_dpreg_i   1, dr0
 123         assert_dpreg_i  -1, dr2
 124         assert_dpreg_i  -1, dr4
 125         test_fpr_a5a5   fr6
 126         test_fpr_a5a5   fr7
 127         test_fpr_a5a5   fr8
 128         test_fpr_a5a5   fr9
 129         test_fpr_a5a5   fr10
 130         test_fpr_a5a5   fr11
 131         test_fpr_a5a5   fr12
 132         test_fpr_a5a5   fr13
 133         test_fpr_a5a5   fr14
 134         test_fpr_a5a5   fr15
 135         pass
 136         exit 0