sim/testsuite/sim/h8300/addx.s

   1 # Hitachi H8 testcase 'addx'
   2 # mach(): all
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12
  13         # Instructions tested:
  14         # addx.b #xx:8, rd8     ; 9 rd8 xxxxxxxx
  15         # addx.b #xx:8, @erd    ; 7 d erd ???? 9 ???? xxxxxxxx
  16         # addx.b #xx:8, @erd-   ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx
  17         # addx.b rs8, rd8       ; 0 e rs8 rd8
  18         # addx.b rs8, @erd      ; 7 d erd ???? 0 e rs8 ????
  19         # addx.b rs8, @erd-     ; 0 1 7 6 6 c erd 1??? 0 e rs8 ????
  20         # addx.b @ers, rd8      ; 7 c ers ???? 0 e ???? rd8
  21         # addx.b @ers-, rd8     ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8
  22         # addx.b @ers, @erd     ; 0 1 7 4 6 8 ers d 0 erd 1 ????
  23         # addx.b @ers-, @erd-   ; 0 1 7 6 6 c ers d a erd 1 ????
  24         #
  25         # coming soon:
  26         # word ops
  27         # long ops
  28
  29 .data
  30 byte_src:       .byte 0x5
  31 byte_dest:      .byte 0
  32
  33         .align 2
  34 word_src:       .word 0x505
  35 word_dest:      .word 0
  36
  37         .align 4
  38 long_src:       .long 0x50505
  39 long_dest:      .long 0
  40
  41
  42         start
  43
  44 addx_b_imm8_0:
  45         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  46         set_ccr_zero
  47
  48         ;;  addx.b #xx:8,Rd     ; Addx with carry initially zero.
  49         addx.b  #5, r0l         ; Immediate 8-bit operand
  50
  51         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
  52         test_ovf_clear
  53         test_zero_clear
  54         test_neg_set
  55
  56         test_h_gr16 0xa5aa r0   ; add result:   a5 + 5
  57 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
  58         test_h_gr32 0xa5a5a5aa er0      ; add result:    a5 + 5
  59 .endif
  60         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  61         test_gr_a5a5 2
  62         test_gr_a5a5 3
  63         test_gr_a5a5 4
  64         test_gr_a5a5 5
  65         test_gr_a5a5 6
  66         test_gr_a5a5 7
  67
  68 addx_b_imm8_1:
  69         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  70         set_ccr_zero
  71
  72         ;;  addx.b #xx:8,Rd     ; Addx with carry initially one.
  73         set_carry_flag 1
  74         addx.b  #5, r0l         ; Immediate 8-bit operand
  75
  76         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
  77         test_ovf_clear
  78         test_zero_clear
  79         test_neg_set
  80
  81         test_h_gr16 0xa5ab r0   ; add result:   a5 + 5 + 1
  82 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
  83         test_h_gr32 0xa5a5a5ab er0      ; add result:    a5 + 5 + 1
  84 .endif
  85         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  86         test_gr_a5a5 2
  87         test_gr_a5a5 3
  88         test_gr_a5a5 4
  89         test_gr_a5a5 5
  90         test_gr_a5a5 6
  91         test_gr_a5a5 7
  92
  93 .if (sim_cpu == h8sx)
  94 addx_b_imm8_rdind:
  95         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  96         set_ccr_zero
  97
  98         ;;  addx.b #xx:8,@eRd   ; Addx to register indirect
  99         mov     #byte_dest, er0
 100         addx.b  #5, @er0
 101
 102         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 103         test_ovf_clear
 104         test_zero_clear
 105         test_neg_clear
 106
 107         test_h_gr32 byte_dest er0       ; er0 still contains address
 108
 109         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 110         test_gr_a5a5 2
 111         test_gr_a5a5 3
 112         test_gr_a5a5 4
 113         test_gr_a5a5 5
 114         test_gr_a5a5 6
 115         test_gr_a5a5 7
 116
 117         ;; Now check the result of the add to memory.
 118         cmp.b   #5, @byte_dest
 119         beq     .Lb1
 120         fail
 121 .Lb1:
 122
 123 addx_b_imm8_rdpostdec:
 124         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 125         set_ccr_zero
 126
 127         ;;  addx.b #xx:8,@eRd-  ; Addx to register post-decrement
 128         mov     #byte_dest, er0
 129         addx.b  #5, @er0-
 130
 131         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 132         test_ovf_clear
 133         test_zero_clear
 134         test_neg_clear
 135
 136         test_h_gr32 byte_dest-1 er0     ; er0 contains address minus one
 137
 138         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 139         test_gr_a5a5 2
 140         test_gr_a5a5 3
 141         test_gr_a5a5 4
 142         test_gr_a5a5 5
 143         test_gr_a5a5 6
 144         test_gr_a5a5 7
 145
 146         ;; Now check the result of the add to memory.
 147         cmp.b   #10, @byte_dest
 148         beq     .Lb2
 149         fail
 150 .Lb2:
 151 .endif
 152
 153 addx_b_reg8_0:
 154         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 155         set_ccr_zero
 156
 157         ;;  addx.b Rs,Rd        ; addx with carry initially zero
 158         mov.b   #5, r0h
 159         addx.b  r0h, r0l        ; Register operand
 160
 161         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 162         test_ovf_clear
 163         test_zero_clear
 164         test_neg_set
 165
 166         test_h_gr16 0x05aa r0   ; add result:   a5 + 5
 167 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
 168         test_h_gr32 0xa5a505aa er0      ; add result:   a5 + 5
 169 .endif
 170         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 171         test_gr_a5a5 2
 172         test_gr_a5a5 3
 173         test_gr_a5a5 4
 174         test_gr_a5a5 5
 175         test_gr_a5a5 6
 176         test_gr_a5a5 7
 177
 178 addx_b_reg8_1:
 179         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 180         set_ccr_zero
 181
 182         ;;  addx.b Rs,Rd        ; addx with carry initially one
 183         mov.b   #5, r0h
 184         set_carry_flag 1
 185         addx.b  r0h, r0l        ; Register operand
 186
 187         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 188         test_ovf_clear
 189         test_zero_clear
 190         test_neg_set
 191
 192         test_h_gr16 0x05ab r0   ; add result:   a5 + 5 + 1
 193 .if (sim_cpu)                   ; non-zero means h8300h, s, or sx
 194         test_h_gr32 0xa5a505ab er0      ; add result:   a5 + 5 + 1
 195 .endif
 196         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 197         test_gr_a5a5 2
 198         test_gr_a5a5 3
 199         test_gr_a5a5 4
 200         test_gr_a5a5 5
 201         test_gr_a5a5 6
 202         test_gr_a5a5 7
 203
 204 .if (sim_cpu == h8sx)
 205 addx_b_reg8_rdind:
 206         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 207         set_ccr_zero
 208
 209         ;;  addx.b rs8,@eRd     ; Addx to register indirect
 210         mov     #byte_dest, er0
 211         mov.b   #5, r1l
 212         addx.b  r1l, @er0
 213
 214         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 215         test_ovf_clear
 216         test_zero_clear
 217         test_neg_clear
 218
 219         test_h_gr32 byte_dest er0       ; er0 still contains address
 220         test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
 221
 222         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 223         test_gr_a5a5 3
 224         test_gr_a5a5 4
 225         test_gr_a5a5 5
 226         test_gr_a5a5 6
 227         test_gr_a5a5 7
 228
 229         ;; Now check the result of the add to memory.
 230         cmp.b   #15, @byte_dest
 231         beq     .Lb3
 232         fail
 233 .Lb3:
 234
 235 addx_b_reg8_rdpostdec:
 236         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 237         set_ccr_zero
 238
 239         ;;  addx.b rs8,@eRd-    ; Addx to register post-decrement
 240         mov     #byte_dest, er0
 241         mov.b   #5, r1l
 242         addx.b  r1l, @er0-
 243
 244         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 245         test_ovf_clear
 246         test_zero_clear
 247         test_neg_clear
 248
 249         test_h_gr32 byte_dest-1 er0     ; er0 contains address minus one
 250         test_h_gr32 0xa5a5a505 er1      ; er1 contains the test load
 251
 252         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 253         test_gr_a5a5 3
 254         test_gr_a5a5 4
 255         test_gr_a5a5 5
 256         test_gr_a5a5 6
 257         test_gr_a5a5 7
 258
 259         ;; Now check the result of the add to memory.
 260         cmp.b   #20, @byte_dest
 261         beq     .Lb4
 262         fail
 263 .Lb4:
 264
 265 addx_b_rsind_reg8:
 266         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 267         set_ccr_zero
 268
 269         ;;  addx.b @eRs,rd8     ; Addx from reg indirect to reg
 270         mov     #byte_src, er0
 271         addx.b  @er0, r1l
 272
 273         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 274         test_ovf_clear
 275         test_zero_clear
 276         test_neg_set
 277
 278         test_h_gr32 byte_src er0        ; er0 still contains address
 279         test_h_gr32 0xa5a5a5aa er1      ; er1 contains the sum
 280
 281         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 282         test_gr_a5a5 3
 283         test_gr_a5a5 4
 284         test_gr_a5a5 5
 285         test_gr_a5a5 6
 286         test_gr_a5a5 7
 287
 288 addx_b_rspostdec_reg8:
 289         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 290         set_ccr_zero
 291
 292         ;;  addx.b @eRs-,rd8    ; Addx to register post-decrement
 293         mov     #byte_src, er0
 294         addx.b  @er0-, r1l
 295
 296         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 297         test_ovf_clear
 298         test_zero_clear
 299         test_neg_set
 300
 301         test_h_gr32 byte_src-1 er0      ; er0 contains address minus one
 302         test_h_gr32 0xa5a5a5aa er1      ; er1 contains the sum
 303
 304         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 305         test_gr_a5a5 3
 306         test_gr_a5a5 4
 307         test_gr_a5a5 5
 308         test_gr_a5a5 6
 309         test_gr_a5a5 7
 310
 311 addx_b_rsind_rsind:
 312         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 313         set_ccr_zero
 314
 315         ;;  addx.b @eRs,rd8     ; Addx from reg indirect to reg
 316         mov     #byte_src, er0
 317         mov     #byte_dest, er1
 318         addx.b  @er0, @er1
 319
 320         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 321         test_ovf_clear
 322         test_zero_clear
 323         test_neg_clear
 324
 325         test_h_gr32 byte_src er0        ; er0 still contains src address
 326         test_h_gr32 byte_dest er1       ; er1 still contains dst address
 327
 328         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 329         test_gr_a5a5 3
 330         test_gr_a5a5 4
 331         test_gr_a5a5 5
 332         test_gr_a5a5 6
 333         test_gr_a5a5 7
 334         ;; Now check the result of the add to memory.
 335         cmp.b   #25, @byte_dest
 336         beq     .Lb5
 337         fail
 338 .Lb5:
 339
 340 addx_b_rspostdec_rspostdec:
 341         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 342         set_ccr_zero
 343
 344         ;;  addx.b @eRs-,rd8    ; Addx to register post-decrement
 345         mov     #byte_src, er0
 346         mov     #byte_dest, er1
 347         addx.b  @er0-, @er1-
 348
 349         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 350         test_ovf_clear
 351         test_zero_clear
 352         test_neg_clear
 353
 354         test_h_gr32 byte_src-1 er0      ; er0 contains src address minus one
 355         test_h_gr32 byte_dest-1 er1     ; er1 contains dst address minus one
 356
 357         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 358         test_gr_a5a5 3
 359         test_gr_a5a5 4
 360         test_gr_a5a5 5
 361         test_gr_a5a5 6
 362         test_gr_a5a5 7
 363         ;; Now check the result of the add to memory.
 364         cmp.b   #30, @byte_dest
 365         beq     .Lb6
 366         fail
 367 .Lb6:
 368
 369 addx_w_imm16_0:
 370         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 371         set_ccr_zero
 372
 373         ;;  addx.w #xx:16,Rd    ; Addx with carry initially zero.
 374         addx.w  #0x505, r0      ; Immediate 16-bit operand
 375
 376         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 377         test_ovf_clear
 378         test_zero_clear
 379         test_neg_set
 380
 381         test_h_gr16 0xaaaa r0   ; add result:   0xa5a5 + 0x505
 382         test_h_gr32 0xa5a5aaaa er0      ; add result:    0xa5a5 + 0x505
 383         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 384         test_gr_a5a5 2
 385         test_gr_a5a5 3
 386         test_gr_a5a5 4
 387         test_gr_a5a5 5
 388         test_gr_a5a5 6
 389         test_gr_a5a5 7
 390
 391 addx_w_imm16_1:
 392         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 393         set_ccr_zero
 394
 395         ;;  addx.w #xx:16,Rd    ; Addx with carry initially one.
 396         set_carry_flag 1
 397         addx.w  #0x505, r0      ; Immediate 16-bit operand
 398
 399         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 400         test_ovf_clear
 401         test_zero_clear
 402         test_neg_set
 403
 404         test_h_gr16 0xaaab r0   ; add result:   0xa5a5 + 0x505 + 1
 405         test_h_gr32 0xa5a5aaab er0      ; add result:    0xa5a5 + 0x505 + 1
 406         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 407         test_gr_a5a5 2
 408         test_gr_a5a5 3
 409         test_gr_a5a5 4
 410         test_gr_a5a5 5
 411         test_gr_a5a5 6
 412         test_gr_a5a5 7
 413
 414 addx_w_imm16_rdind:
 415         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 416         set_ccr_zero
 417
 418         ;;  addx.w #xx:16,@eRd  ; Addx to register indirect
 419         mov     #word_dest, er0
 420         addx.w  #0x505, @er0
 421
 422         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 423         test_ovf_clear
 424         test_zero_clear
 425         test_neg_clear
 426
 427         test_h_gr32 word_dest er0       ; er0 still contains address
 428
 429         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 430         test_gr_a5a5 2
 431         test_gr_a5a5 3
 432         test_gr_a5a5 4
 433         test_gr_a5a5 5
 434         test_gr_a5a5 6
 435         test_gr_a5a5 7
 436
 437         ;; Now check the result of the add to memory.
 438         cmp.w   #0x505, @word_dest
 439         beq     .Lw1
 440         fail
 441 .Lw1:
 442
 443 addx_w_imm16_rdpostdec:
 444         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 445         set_ccr_zero
 446
 447         ;;  addx.w #xx:16,@eRd- ; Addx to register post-decrement
 448         mov     #word_dest, er0
 449         addx.w  #0x505, @er0-
 450
 451         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 452         test_ovf_clear
 453         test_zero_clear
 454         test_neg_clear
 455
 456         test_h_gr32 word_dest-2 er0     ; er0 contains address minus one
 457
 458         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 459         test_gr_a5a5 2
 460         test_gr_a5a5 3
 461         test_gr_a5a5 4
 462         test_gr_a5a5 5
 463         test_gr_a5a5 6
 464         test_gr_a5a5 7
 465
 466         ;; Now check the result of the add to memory.
 467         cmp.w   #0xa0a, @word_dest
 468         beq     .Lw2
 469         fail
 470 .Lw2:
 471
 472 addx_w_reg16_0:
 473         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 474         set_ccr_zero
 475
 476         ;;  addx.w Rs,Rd        ; addx with carry initially zero
 477         mov.w   #0x505, e0
 478         addx.w  e0, r0          ; Register operand
 479
 480         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 481         test_ovf_clear
 482         test_zero_clear
 483         test_neg_set
 484
 485         test_h_gr32 0x0505aaaa er0      ; add result:
 486         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 487         test_gr_a5a5 2
 488         test_gr_a5a5 3
 489         test_gr_a5a5 4
 490         test_gr_a5a5 5
 491         test_gr_a5a5 6
 492         test_gr_a5a5 7
 493
 494 addx_w_reg16_1:
 495         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 496         set_ccr_zero
 497
 498         ;;  addx.w Rs,Rd        ; addx with carry initially one
 499         mov.w   #0x505, e0
 500         set_carry_flag 1
 501         addx.w  e0, r0          ; Register operand
 502
 503         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 504         test_ovf_clear
 505         test_zero_clear
 506         test_neg_set
 507
 508         test_h_gr32 0x0505aaab er0      ; add result:
 509         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 510         test_gr_a5a5 2
 511         test_gr_a5a5 3
 512         test_gr_a5a5 4
 513         test_gr_a5a5 5
 514         test_gr_a5a5 6
 515         test_gr_a5a5 7
 516
 517 addx_w_reg16_rdind:
 518         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 519         set_ccr_zero
 520
 521         ;;  addx.w rs8,@eRd     ; Addx to register indirect
 522         mov     #word_dest, er0
 523         mov.w   #0x505, r1
 524         addx.w  r1, @er0
 525
 526         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 527         test_ovf_clear
 528         test_zero_clear
 529         test_neg_clear
 530
 531         test_h_gr32 word_dest er0       ; er0 still contains address
 532         test_h_gr32 0xa5a50505 er1      ; er1 has the test load
 533
 534         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 535         test_gr_a5a5 3
 536         test_gr_a5a5 4
 537         test_gr_a5a5 5
 538         test_gr_a5a5 6
 539         test_gr_a5a5 7
 540
 541         ;; Now check the result of the add to memory.
 542         cmp.w   #0xf0f, @word_dest
 543         beq     .Lw3
 544         fail
 545 .Lw3:
 546
 547 addx_w_reg16_rdpostdec:
 548         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 549         set_ccr_zero
 550
 551         ;;  addx.w rs8,@eRd-    ; Addx to register post-decrement
 552         mov     #word_dest, er0
 553         mov.w   #0x505, r1
 554         addx.w  r1, @er0-
 555
 556         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 557         test_ovf_clear
 558         test_zero_clear
 559         test_neg_clear
 560
 561         test_h_gr32 word_dest-2 er0     ; er0 contains address minus one
 562         test_h_gr32 0xa5a50505  er1     ; er1 contains the test load
 563
 564         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 565         test_gr_a5a5 3
 566         test_gr_a5a5 4
 567         test_gr_a5a5 5
 568         test_gr_a5a5 6
 569         test_gr_a5a5 7
 570
 571         ;; Now check the result of the add to memory.
 572         cmp.w   #0x1414, @word_dest
 573         beq     .Lw4
 574         fail
 575 .Lw4:
 576
 577 addx_w_rsind_reg16:
 578         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 579         set_ccr_zero
 580
 581         ;;  addx.w @eRs,rd8     ; Addx from reg indirect to reg
 582         mov     #word_src, er0
 583         addx.w  @er0, r1
 584
 585         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 586         test_ovf_clear
 587         test_zero_clear
 588         test_neg_set
 589
 590         test_h_gr32 word_src er0        ; er0 still contains address
 591         test_h_gr32 0xa5a5aaaa er1      ; er1 contains the sum
 592
 593         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 594         test_gr_a5a5 3
 595         test_gr_a5a5 4
 596         test_gr_a5a5 5
 597         test_gr_a5a5 6
 598         test_gr_a5a5 7
 599
 600 addx_w_rspostdec_reg16:
 601         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 602         set_ccr_zero
 603
 604         ;;  addx.w @eRs-,rd8    ; Addx to register post-decrement
 605         mov     #word_src, er0
 606         addx.w  @er0-, r1
 607
 608         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 609         test_ovf_clear
 610         test_zero_clear
 611         test_neg_set
 612
 613         test_h_gr32 word_src-2 er0      ; er0 contains address minus one
 614         test_h_gr32 0xa5a5aaaa er1      ; er1 contains the sum
 615
 616         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 617         test_gr_a5a5 3
 618         test_gr_a5a5 4
 619         test_gr_a5a5 5
 620         test_gr_a5a5 6
 621         test_gr_a5a5 7
 622
 623 addx_w_rsind_rdind:
 624         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 625         set_ccr_zero
 626
 627         ;;  addx.w @eRs,rd8     ; Addx from reg indirect to reg
 628         mov     #word_src, er0
 629         mov     #word_dest, er1
 630         addx.w  @er0, @er1
 631
 632         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 633         test_ovf_clear
 634         test_zero_clear
 635         test_neg_clear
 636
 637         test_h_gr32 word_src er0        ; er0 still contains src address
 638         test_h_gr32 word_dest er1       ; er1 still contains dst address
 639
 640         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 641         test_gr_a5a5 3
 642         test_gr_a5a5 4
 643         test_gr_a5a5 5
 644         test_gr_a5a5 6
 645         test_gr_a5a5 7
 646         ;; Now check the result of the add to memory.
 647         cmp.w   #0x1919, @word_dest
 648         beq     .Lw5
 649         fail
 650 .Lw5:
 651
 652 addx_w_rspostdec_rdpostdec:
 653         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 654         set_ccr_zero
 655
 656         ;;  addx.w @eRs-,rd8    ; Addx to register post-decrement
 657         mov     #word_src, er0
 658         mov     #word_dest, er1
 659         addx.w  @er0-, @er1-
 660
 661         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 662         test_ovf_clear
 663         test_zero_clear
 664         test_neg_clear
 665
 666         test_h_gr32 word_src-2 er0      ; er0 contains src address minus one
 667         test_h_gr32 word_dest-2 er1     ; er1 contains dst address minus one
 668
 669         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 670         test_gr_a5a5 3
 671         test_gr_a5a5 4
 672         test_gr_a5a5 5
 673         test_gr_a5a5 6
 674         test_gr_a5a5 7
 675         ;; Now check the result of the add to memory.
 676         cmp.w   #0x1e1e, @word_dest
 677         beq     .Lw6
 678         fail
 679 .Lw6:
 680
 681 addx_l_imm32_0:
 682         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 683         set_ccr_zero
 684
 685         ;;  addx.l #xx:32,Rd    ; Addx with carry initially zero.
 686         addx.l  #0x50505, er0   ; Immediate 32-bit operand
 687
 688         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 689         test_ovf_clear
 690         test_zero_clear
 691         test_neg_set
 692
 693         test_h_gr32 0xa5aaaaaa er0      ; add result:
 694         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 695         test_gr_a5a5 2
 696         test_gr_a5a5 3
 697         test_gr_a5a5 4
 698         test_gr_a5a5 5
 699         test_gr_a5a5 6
 700         test_gr_a5a5 7
 701
 702 addx_l_imm32_1:
 703         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 704         set_ccr_zero
 705
 706         ;;  addx.l #xx:32,Rd    ; Addx with carry initially one.
 707         set_carry_flag 1
 708         addx.l  #0x50505, er0   ; Immediate 32-bit operand
 709
 710         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 711         test_ovf_clear
 712         test_zero_clear
 713         test_neg_set
 714
 715         test_h_gr32 0xa5aaaaab er0      ; add result:
 716         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 717         test_gr_a5a5 2
 718         test_gr_a5a5 3
 719         test_gr_a5a5 4
 720         test_gr_a5a5 5
 721         test_gr_a5a5 6
 722         test_gr_a5a5 7
 723
 724 addx_l_imm32_rdind:
 725         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 726         set_ccr_zero
 727
 728         ;;  addx.l #xx:32,@eRd  ; Addx to register indirect
 729         mov     #long_dest, er0
 730         addx.l  #0x50505, @er0
 731
 732         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 733         test_ovf_clear
 734         test_zero_clear
 735         test_neg_clear
 736
 737         test_h_gr32 long_dest er0       ; er0 still contains address
 738
 739         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 740         test_gr_a5a5 2
 741         test_gr_a5a5 3
 742         test_gr_a5a5 4
 743         test_gr_a5a5 5
 744         test_gr_a5a5 6
 745         test_gr_a5a5 7
 746
 747         ;; Now check the result of the add to memory.
 748         cmp.l   #0x50505, @long_dest
 749         beq     .Ll1
 750         fail
 751 .Ll1:
 752
 753 addx_l_imm32_rdpostdec:
 754         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 755         set_ccr_zero
 756
 757         ;;  addx.l #xx:32,@eRd- ; Addx to register post-decrement
 758         mov     #long_dest, er0
 759         addx.l  #0x50505, @er0-
 760
 761         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 762         test_ovf_clear
 763         test_zero_clear
 764         test_neg_clear
 765
 766         test_h_gr32 long_dest-4 er0     ; er0 contains address minus one
 767
 768         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 769         test_gr_a5a5 2
 770         test_gr_a5a5 3
 771         test_gr_a5a5 4
 772         test_gr_a5a5 5
 773         test_gr_a5a5 6
 774         test_gr_a5a5 7
 775
 776         ;; Now check the result of the add to memory.
 777         cmp.l   #0xa0a0a, @long_dest
 778         beq     .Ll2
 779         fail
 780 .Ll2:
 781
 782 addx_l_reg32_0:
 783         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 784         set_ccr_zero
 785
 786         ;;  addx.l Rs,Rd        ; addx with carry initially zero
 787         mov.l   #0x50505, er0
 788         addx.l  er0, er1        ; Register operand
 789
 790         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 791         test_ovf_clear
 792         test_zero_clear
 793         test_neg_set
 794
 795         test_h_gr32 0x50505    er0      ; add load
 796         test_h_gr32 0xa5aaaaaa er1      ; add result:
 797         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 798         test_gr_a5a5 3
 799         test_gr_a5a5 4
 800         test_gr_a5a5 5
 801         test_gr_a5a5 6
 802         test_gr_a5a5 7
 803
 804 addx_l_reg32_1:
 805         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 806         set_ccr_zero
 807
 808         ;;  addx.l Rs,Rd        ; addx with carry initially one
 809         mov.l   #0x50505, er0
 810         set_carry_flag 1
 811         addx.l  er0, er1        ; Register operand
 812
 813         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 814         test_ovf_clear
 815         test_zero_clear
 816         test_neg_set
 817
 818         test_h_gr32 0x50505    er0      ; add result:
 819         test_h_gr32 0xa5aaaaab er1      ; add result:
 820         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 821         test_gr_a5a5 3
 822         test_gr_a5a5 4
 823         test_gr_a5a5 5
 824         test_gr_a5a5 6
 825         test_gr_a5a5 7
 826
 827 addx_l_reg32_rdind:
 828         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 829         set_ccr_zero
 830
 831         ;;  addx.l rs8,@eRd     ; Addx to register indirect
 832         mov     #long_dest, er0
 833         mov.l   #0x50505, er1
 834         addx.l  er1, @er0
 835
 836         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 837         test_ovf_clear
 838         test_zero_clear
 839         test_neg_clear
 840
 841         test_h_gr32 long_dest er0       ; er0 still contains address
 842         test_h_gr32 0x50505   er1       ; er1 has the test load
 843
 844         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 845         test_gr_a5a5 3
 846         test_gr_a5a5 4
 847         test_gr_a5a5 5
 848         test_gr_a5a5 6
 849         test_gr_a5a5 7
 850
 851         ;; Now check the result of the add to memory.
 852         cmp.l   #0xf0f0f, @long_dest
 853         beq     .Ll3
 854         fail
 855 .Ll3:
 856
 857 addx_l_reg32_rdpostdec:
 858         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 859         set_ccr_zero
 860
 861         ;;  addx.l rs8,@eRd-    ; Addx to register post-decrement
 862         mov     #long_dest, er0
 863         mov.l   #0x50505, er1
 864         addx.l  er1, @er0-
 865
 866         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 867         test_ovf_clear
 868         test_zero_clear
 869         test_neg_clear
 870
 871         test_h_gr32 long_dest-4 er0     ; er0 contains address minus one
 872         test_h_gr32 0x50505     er1     ; er1 contains the test load
 873
 874         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 875         test_gr_a5a5 3
 876         test_gr_a5a5 4
 877         test_gr_a5a5 5
 878         test_gr_a5a5 6
 879         test_gr_a5a5 7
 880
 881         ;; Now check the result of the add to memory.
 882         cmp.l   #0x141414, @long_dest
 883         beq     .Ll4
 884         fail
 885 .Ll4:
 886
 887 addx_l_rsind_reg32:
 888         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 889         set_ccr_zero
 890
 891         ;;  addx.l @eRs,rd8     ; Addx from reg indirect to reg
 892         mov     #long_src, er0
 893         addx.l  @er0, er1
 894
 895         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 896         test_ovf_clear
 897         test_zero_clear
 898         test_neg_set
 899
 900         test_h_gr32 long_src er0        ; er0 still contains address
 901         test_h_gr32 0xa5aaaaaa er1      ; er1 contains the sum
 902
 903         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 904         test_gr_a5a5 3
 905         test_gr_a5a5 4
 906         test_gr_a5a5 5
 907         test_gr_a5a5 6
 908         test_gr_a5a5 7
 909
 910 addx_l_rspostdec_reg32:
 911         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 912         set_ccr_zero
 913
 914         ;;  addx.l @eRs-,rd8    ; Addx to register post-decrement
 915         mov     #long_src, er0
 916         addx.l  @er0-, er1
 917
 918         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 919         test_ovf_clear
 920         test_zero_clear
 921         test_neg_set
 922
 923         test_h_gr32 long_src-4 er0      ; er0 contains address minus one
 924         test_h_gr32 0xa5aaaaaa er1      ; er1 contains the sum
 925
 926         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 927         test_gr_a5a5 3
 928         test_gr_a5a5 4
 929         test_gr_a5a5 5
 930         test_gr_a5a5 6
 931         test_gr_a5a5 7
 932
 933 addx_l_rsind_rdind:
 934         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 935         set_ccr_zero
 936
 937         ;;  addx.l @eRs,rd8     ; Addx from reg indirect to reg
 938         mov     #long_src, er0
 939         mov     #long_dest, er1
 940         addx.l  @er0, @er1
 941
 942         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 943         test_ovf_clear
 944         test_zero_clear
 945         test_neg_clear
 946
 947         test_h_gr32 long_src er0        ; er0 still contains src address
 948         test_h_gr32 long_dest er1       ; er1 still contains dst address
 949
 950         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 951         test_gr_a5a5 3
 952         test_gr_a5a5 4
 953         test_gr_a5a5 5
 954         test_gr_a5a5 6
 955         test_gr_a5a5 7
 956         ;; Now check the result of the add to memory.
 957         cmp.l   #0x191919, @long_dest
 958         beq     .Ll5
 959         fail
 960 .Ll5:
 961
 962 addx_l_rspostdec_rdpostdec:
 963         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 964         set_ccr_zero
 965
 966         ;;  addx.l @eRs-,rd8    ; Addx to register post-decrement
 967         mov     #long_src, er0
 968         mov     #long_dest, er1
 969         addx.l  @er0-, @er1-
 970
 971         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 972         test_ovf_clear
 973         test_zero_clear
 974         test_neg_clear
 975
 976         test_h_gr32 long_src-4 er0      ; er0 contains src address minus one
 977         test_h_gr32 long_dest-4 er1     ; er1 contains dst address minus one
 978
 979         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 980         test_gr_a5a5 3
 981         test_gr_a5a5 4
 982         test_gr_a5a5 5
 983         test_gr_a5a5 6
 984         test_gr_a5a5 7
 985         ;; Now check the result of the add to memory.
 986         cmp.l   #0x1e1e1e, @long_dest
 987         beq     .Ll6
 988         fail
 989 .Ll6:
 990 .endif
 991         pass
 992
 993         exit 0