sim/testsuite/sim/h8300/jmp.s

   1 # Hitachi H8 testcase 'jmp'
   2 # mach(): all
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12
  13         start
  14
  15 .if 0                           ; this one isn't right -- it's an indirect
  16 jmp_8:
  17         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  18         set_ccr_zero
  19
  20         ;;  jmp @aa:8           ; 8-bit displacement
  21         jmp @@.Ltgt_8:8
  22         fail
  23
  24 .Ltgt_8:
  25         test_cc_clear
  26         test_gr_a5a5 0          ; Make sure other general regs not disturbed
  27         test_gr_a5a5 1
  28         test_gr_a5a5 2
  29         test_gr_a5a5 3
  30         test_gr_a5a5 4
  31         test_gr_a5a5 5
  32         test_gr_a5a5 6
  33         test_gr_a5a5 7
  34 .endif
  35
  36 jmp_24:
  37         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  38         set_ccr_zero
  39
  40         ;;  jmp @aa:24          ; 24-bit address
  41         jmp @.Ltgt_24:24
  42         fail
  43
  44 .Ltgt_24:
  45         test_cc_clear
  46         test_gr_a5a5 0          ; Make sure other general regs not disturbed
  47         test_gr_a5a5 1
  48         test_gr_a5a5 2
  49         test_gr_a5a5 3
  50         test_gr_a5a5 4
  51         test_gr_a5a5 5
  52         test_gr_a5a5 6
  53         test_gr_a5a5 7
  54
  55 .if     (sim_cpu)               ; Non-zero means h8300h, h8300s, or h8sx
  56 jmp_reg:
  57         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  58         set_ccr_zero
  59
  60         ;;  jmp @ern            ; register indirect
  61         mov.l   #.Ltgt_reg, er5
  62         jmp     @er5
  63         fail
  64
  65 .Ltgt_reg:
  66         test_cc_clear
  67         test_gr_a5a5 0          ; Make sure other general regs not disturbed
  68         test_gr_a5a5 1
  69         test_gr_a5a5 2
  70         test_gr_a5a5 3
  71         test_gr_a5a5 4
  72         test_h_gr32 .Ltgt_reg er5
  73         test_gr_a5a5 6
  74         test_gr_a5a5 7
  75 .endif
  76
  77 .if (sim_cpu == h8sx)
  78 jmp_32:
  79         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  80         set_ccr_zero
  81
  82         ;;  jmp @aa:32          ; 32-bit address
  83 ;       jmp @.Ltgt_32:32        ; NOTE: hard-coded to avoid relaxing
  84         .word   0x5908
  85         .long   .Ltgt_32
  86         fail
  87
  88 .Ltgt_32:
  89         test_cc_clear
  90         test_gr_a5a5 0          ; Make sure other general regs not disturbed
  91         test_gr_a5a5 1
  92         test_gr_a5a5 2
  93         test_gr_a5a5 3
  94         test_gr_a5a5 4
  95         test_gr_a5a5 5
  96         test_gr_a5a5 6
  97         test_gr_a5a5 7
  98 .endif
  99
 100         pass
 101         exit 0
 102
 103