sim/testsuite/sim/h8300/shll.s

   1 # Hitachi H8 testcase 'shll'
   2 # mach(): all
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12
  13         start
  14
  15         .data
  16 byte_dest:      .byte   0xa5
  17         .align 2
  18 word_dest:      .word   0xa5a5
  19         .align 4
  20 long_dest:      .long   0xa5a5a5a5
  21
  22         .text
  23
  24 shll_b_reg8_1:
  25         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  26         set_ccr_zero
  27
  28         shll.b  r0l             ; shift left logical by one
  29 ;;;     .word   0x1008
  30
  31         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
  32         test_zero_clear
  33         test_ovf_clear
  34         test_neg_clear
  35         test_h_gr16 0xa54a r0   ; 1010 0101 -> 0100 1010
  36 .if (sim_cpu)
  37         test_h_gr32 0xa5a5a54a er0
  38 .endif
  39         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  40         test_gr_a5a5 2
  41         test_gr_a5a5 3
  42         test_gr_a5a5 4
  43         test_gr_a5a5 5
  44         test_gr_a5a5 6
  45         test_gr_a5a5 7
  46
  47 shll_b_reg8_2:
  48         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  49         set_ccr_zero
  50
  51         shll.b  #2, r0l         ; shift left logical by two
  52 ;;;     .word   0x1048
  53
  54         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
  55         test_zero_clear
  56         test_ovf_clear
  57         test_neg_set
  58
  59         test_h_gr16 0xa594 r0   ; 1010 0101 -> 1001 0100
  60 .if (sim_cpu)
  61         test_h_gr32 0xa5a5a594 er0
  62 .endif
  63         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  64         test_gr_a5a5 2
  65         test_gr_a5a5 3
  66         test_gr_a5a5 4
  67         test_gr_a5a5 5
  68         test_gr_a5a5 6
  69         test_gr_a5a5 7
  70
  71 .if (sim_cpu == h8sx)
  72 shll_b_reg8_4:
  73         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  74         set_ccr_zero
  75
  76         shll.b  #4, r0l         ; shift left logical by four
  77 ;;;     .word   0x10a8
  78
  79         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
  80         test_zero_clear
  81         test_ovf_clear
  82         test_neg_clear
  83         test_h_gr16 0xa550 r0   ; 1010 0101 -> 0101 0000
  84         test_h_gr32 0xa5a5a550 er0
  85
  86         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  87         test_gr_a5a5 2
  88         test_gr_a5a5 3
  89         test_gr_a5a5 4
  90         test_gr_a5a5 5
  91         test_gr_a5a5 6
  92         test_gr_a5a5 7
  93 .endif
  94
  95 .if (sim_cpu)                   ; Not available in h8300 mode
  96 shll_w_reg16_1:
  97         set_grs_a5a5            ; Fill all general regs with a fixed pattern
  98         set_ccr_zero
  99
 100         shll.w  r0              ; shift left logical by one
 101 ;;;     .word   0x1010
 102
 103         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 104         test_zero_clear
 105         test_ovf_clear
 106         test_neg_clear
 107         test_h_gr16 0x4b4a r0   ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
 108         test_h_gr32 0xa5a54b4a er0
 109
 110         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 111         test_gr_a5a5 2
 112         test_gr_a5a5 3
 113         test_gr_a5a5 4
 114         test_gr_a5a5 5
 115         test_gr_a5a5 6
 116         test_gr_a5a5 7
 117
 118 shll_w_reg16_2:
 119         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 120         set_ccr_zero
 121
 122         shll.w  #2, r0          ; shift left logical by two
 123 ;;;     .word   0x1050
 124
 125         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 126         test_zero_clear
 127         test_ovf_clear
 128         test_neg_set
 129         test_h_gr16 0x9694 r0   ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
 130         test_h_gr32 0xa5a59694 er0
 131
 132         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 133         test_gr_a5a5 2
 134         test_gr_a5a5 3
 135         test_gr_a5a5 4
 136         test_gr_a5a5 5
 137         test_gr_a5a5 6
 138         test_gr_a5a5 7
 139
 140 .if (sim_cpu == h8sx)
 141 shll_w_reg16_4:
 142         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 143         set_ccr_zero
 144
 145         shll.w  #4, r0          ; shift left logical by four
 146 ;;;     .word   0x1020
 147
 148         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 149         test_zero_clear
 150         test_ovf_clear
 151         test_neg_clear
 152         test_h_gr16 0x5a50 r0   ; 1010 0101 1010 0101 -> 0101 1010 0101 0000
 153         test_h_gr32 0xa5a55a50 er0
 154
 155         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 156         test_gr_a5a5 2
 157         test_gr_a5a5 3
 158         test_gr_a5a5 4
 159         test_gr_a5a5 5
 160         test_gr_a5a5 6
 161         test_gr_a5a5 7
 162
 163 shll_w_reg16_8:
 164         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 165         set_ccr_zero
 166
 167         shll.w  #8, r0          ; shift left logical by eight
 168 ;;;     .word   0x1060
 169
 170         test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
 171         test_zero_clear
 172         test_ovf_clear
 173         test_neg_set
 174         test_h_gr16 0xa500 r0   ; 1010 0101 1010 0101 -> 1010 0101 0000 0000
 175         test_h_gr32 0xa5a5a500 er0
 176
 177         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 178         test_gr_a5a5 2
 179         test_gr_a5a5 3
 180         test_gr_a5a5 4
 181         test_gr_a5a5 5
 182         test_gr_a5a5 6
 183         test_gr_a5a5 7
 184 .endif
 185
 186 shll_l_reg32_1:
 187         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 188         set_ccr_zero
 189
 190         shll.l  er0             ; shift left logical by one
 191 ;;;     .word   1030
 192
 193         test_carry_set          ; H=0 N=0 Z=0 V=0 C=1
 194         test_zero_clear
 195         test_ovf_clear
 196         test_neg_clear
 197         ; 1010 0101 1010 0101 1010 0101 1010 0101
 198         ; -> 0100 1011 0100 1011 0100 1011 0100 1010
 199         test_h_gr32 0x4b4b4b4a er0
 200
 201         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 202         test_gr_a5a5 2
 203         test_gr_a5a5 3
 204         test_gr_a5a5 4
 205         test_gr_a5a5 5
 206         test_gr_a5a5 6
 207         test_gr_a5a5 7
 208
 209 shll_l_reg32_2:
 210         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 211         set_ccr_zero
 212
 213         shll.l  #2, er0         ; shift left logical by two
 214 ;;;     .word   0x1070
 215
 216         test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
 217         test_zero_clear
 218         test_ovf_clear
 219         test_neg_set
 220         ; 1010 0101 1010 0101 1010 0101 1010 0101
 221         ; -> 1001 0110 1001 0110 1001 0110 1001 0100
 222         test_h_gr32 0x96969694 er0
 223
 224         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 225         test_gr_a5a5 2
 226         test_gr_a5a5 3
 227         test_gr_a5a5 4
 228         test_gr_a5a5 5
 229         test_gr_a5a5 6
 230         test_gr_a5a5 7
 231
 232 .if (sim_cpu == h8sx)
 233 shll_l_reg32_4:
 234         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 235         set_ccr_zero
 236
 237         shll.l  #4, er0         ; shift left logical by four
 238 ;;;     .word   0x1038
 239
 240         test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
 241         test_zero_clear
 242         test_ovf_clear
 243         test_neg_clear
 244         ; 1010 0101 1010 0101 1010 0101 1010 0101
 245         ; -> 0101 1010 0101 1010 0101 1010 0101 0000
 246         test_h_gr32 0x5a5a5a50 er0
 247
 248         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 249         test_gr_a5a5 2
 250         test_gr_a5a5 3
 251         test_gr_a5a5 4
 252         test_gr_a5a5 5
 253         test_gr_a5a5 6
 254         test_gr_a5a5 7
 255
 256 shll_l_reg32_8:
 257         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 258         set_ccr_zero
 259
 260         shll.l  #8, er0         ; shift left logical by eight
 261 ;;;     .word   0x1078
 262
 263         test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
 264         test_zero_clear
 265         test_ovf_clear
 266         test_neg_set
 267         test_h_gr16 0xa500 r0
 268         ; 1010 0101 1010 0101 1010 0101 1010 0101
 269         ; -> 1010 0101 1010 0101 1010 0101 0000 0000
 270         test_h_gr32 0xa5a5a500 er0
 271
 272         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 273         test_gr_a5a5 2
 274         test_gr_a5a5 3
 275         test_gr_a5a5 4
 276         test_gr_a5a5 5
 277         test_gr_a5a5 6
 278         test_gr_a5a5 7
 279
 280 shll_l_reg32_16:
 281         set_grs_a5a5            ; Fill all general regs with a fixed pattern
 282         set_ccr_zero
 283
 284         shll.l  #16, er0        ; shift left logical by sixteen
 285 ;;;     .word   0x10f8
 286
 287         test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
 288         test_zero_clear
 289         test_ovf_clear
 290         test_neg_set
 291         ; 1010 0101 1010 0101 1010 0101 1010 0101
 292         ;; -> 1010 0101 1010 0101 0000 0000 0000 0000
 293         test_h_gr32 0xa5a50000 er0
 294
 295         test_gr_a5a5 1          ; Make sure other general regs not disturbed
 296         test_gr_a5a5 2
 297         test_gr_a5a5 3
 298         test_gr_a5a5 4
 299         test_gr_a5a5 5
 300         test_gr_a5a5 6
 301         test_gr_a5a5 7
 302 .endif
 303 .endif
 304
 305         pass
 306
 307         exit 0
 308