sim/testsuite/sim/h8300/stc.s

   1 # Hitachi H8 testcase 'stc'
   2 # mach(): all
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12         .data
  13 byte_dest1:
  14         .byte   0
  15 byte_dest2:
  16         .byte   0
  17 byte_dest3:
  18         .byte   0
  19 byte_dest4:
  20         .byte   0
  21 byte_dest5:
  22         .byte   0
  23 byte_dest6:
  24         .byte   0
  25 byte_dest7:
  26         .byte   0
  27 byte_dest8:
  28         .byte   0
  29 byte_dest9:
  30         .byte   0
  31 byte_dest10:
  32         .byte   0
  33 byte_dest11:
  34         .byte   0
  35 byte_dest12:
  36         .byte   0
  37
  38         start
  39
  40 stc_ccr_reg8:
  41         set_grs_a5a5
  42         set_ccr_zero
  43
  44         ldc     #0xff, ccr      ; test value
  45         stc     ccr, r0h        ; copy test value to r0h
  46
  47         test_h_gr16  0xffa5 r0  ; ff in r0h, a5 in r0l
  48 .if (sim_cpu)                   ; h/s/sx
  49         test_h_gr32  0xa5a5ffa5 er0     ; ff in r0h, a5 everywhere else
  50 .endif
  51         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  52         test_gr_a5a5 2
  53         test_gr_a5a5 3
  54         test_gr_a5a5 4
  55         test_gr_a5a5 5
  56         test_gr_a5a5 6
  57         test_gr_a5a5 7
  58
  59 .if (sim_cpu == h8300s || sim_cpu == h8sx)      ; Earlier versions, no exr
  60 stc_exr_reg8:
  61         set_grs_a5a5
  62         set_ccr_zero
  63
  64         ldc     #0x87, exr      ; set exr to 0x87
  65         stc     exr, r0l        ; retrieve and check exr value
  66         cmp.b   #0x87, r0l
  67         beq     .L21
  68         fail
  69 .L21:
  70         test_h_gr32  0xa5a5a587 er0     ; Register 0 modified by test procedure.
  71         test_gr_a5a5 1          ; Make sure other general regs not disturbed
  72         test_gr_a5a5 2
  73         test_gr_a5a5 3
  74         test_gr_a5a5 4
  75         test_gr_a5a5 5
  76         test_gr_a5a5 6
  77         test_gr_a5a5 7
  78
  79 stc_ccr_abs16:
  80         set_grs_a5a5
  81         set_ccr_zero
  82
  83         ldc     #0xff, ccr
  84         stc     ccr, @byte_dest1:16     ; abs16 dest
  85
  86         test_gr_a5a5 0          ; Make sure other general regs not disturbed
  87         test_gr_a5a5 1
  88         test_gr_a5a5 2
  89         test_gr_a5a5 3
  90         test_gr_a5a5 4
  91         test_gr_a5a5 5
  92         test_gr_a5a5 6
  93         test_gr_a5a5 7
  94
  95 stc_exr_abs16:
  96         set_grs_a5a5
  97         set_ccr_zero
  98
  99         ldc     #0x87, exr
 100         stc     exr, @byte_dest2:16     ; abs16 dest
 101
 102         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 103         test_gr_a5a5 1
 104         test_gr_a5a5 2
 105         test_gr_a5a5 3
 106         test_gr_a5a5 4
 107         test_gr_a5a5 5
 108         test_gr_a5a5 6
 109         test_gr_a5a5 7
 110
 111 stc_ccr_abs32:
 112         set_grs_a5a5
 113         set_ccr_zero
 114
 115         ldc     #0xff, ccr
 116         stc     ccr, @byte_dest3:32     ; abs32 dest
 117
 118         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 119         test_gr_a5a5 1
 120         test_gr_a5a5 2
 121         test_gr_a5a5 3
 122         test_gr_a5a5 4
 123         test_gr_a5a5 5
 124         test_gr_a5a5 6
 125         test_gr_a5a5 7
 126
 127 stc_exr_abs32:
 128         set_grs_a5a5
 129         set_ccr_zero
 130
 131         ldc     #0x87, exr
 132         stc     exr, @byte_dest4:32     ; abs32 dest
 133
 134         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 135         test_gr_a5a5 1
 136         test_gr_a5a5 2
 137         test_gr_a5a5 3
 138         test_gr_a5a5 4
 139         test_gr_a5a5 5
 140         test_gr_a5a5 6
 141         test_gr_a5a5 7
 142
 143 stc_ccr_disp16:
 144         set_grs_a5a5
 145         set_ccr_zero
 146
 147         mov     #byte_dest4, er1
 148         ldc     #0xff, ccr
 149         stc     ccr, @(1:16,er1)        ; disp16 dest (5)
 150
 151         test_h_gr32 byte_dest4, er1     ; er1 still contains address
 152
 153         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 154         test_gr_a5a5 2
 155         test_gr_a5a5 3
 156         test_gr_a5a5 4
 157         test_gr_a5a5 5
 158         test_gr_a5a5 6
 159         test_gr_a5a5 7
 160
 161 stc_exr_disp16:
 162         set_grs_a5a5
 163         set_ccr_zero
 164
 165         mov     #byte_dest7, er1
 166         ldc     #0x87, exr
 167         stc     exr, @(-1:16,er1)       ; disp16 dest (6)
 168
 169         test_h_gr32 byte_dest7, er1     ; er1 still contains address
 170
 171         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 172         test_gr_a5a5 2
 173         test_gr_a5a5 3
 174         test_gr_a5a5 4
 175         test_gr_a5a5 5
 176         test_gr_a5a5 6
 177         test_gr_a5a5 7
 178
 179 stc_ccr_disp32:
 180         set_grs_a5a5
 181         set_ccr_zero
 182
 183         mov     #byte_dest6, er1
 184         ldc     #0xff, ccr
 185         stc     ccr, @(1:32,er1)        ; disp32 dest (7)
 186
 187         test_h_gr32 byte_dest6, er1     ; er1 still contains address
 188
 189         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 190         test_gr_a5a5 2
 191         test_gr_a5a5 3
 192         test_gr_a5a5 4
 193         test_gr_a5a5 5
 194         test_gr_a5a5 6
 195         test_gr_a5a5 7
 196
 197 stc_exr_disp32:
 198         set_grs_a5a5
 199         set_ccr_zero
 200
 201         mov     #byte_dest9, er1
 202         ldc     #0x87, exr
 203         stc     exr, @(-1:32,er1)       ; disp16 dest (8)
 204
 205         test_h_gr32 byte_dest9, er1     ; er1 still contains address
 206
 207         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 208         test_gr_a5a5 3
 209         test_gr_a5a5 4
 210         test_gr_a5a5 5
 211         test_gr_a5a5 6
 212         test_gr_a5a5 7
 213
 214 stc_ccr_predecr:
 215         set_grs_a5a5
 216         set_ccr_zero
 217
 218         mov     #byte_dest10, er1
 219         ldc     #0xff, ccr
 220         stc     ccr, @-er1      ; predecr dest (9)
 221
 222         test_h_gr32 byte_dest9, er1     ; er1 still contains address
 223
 224         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 225         test_gr_a5a5 2
 226         test_gr_a5a5 3
 227         test_gr_a5a5 4
 228         test_gr_a5a5 5
 229         test_gr_a5a5 6
 230         test_gr_a5a5 7
 231
 232 stc_exr_predecr:
 233         set_grs_a5a5
 234         set_ccr_zero
 235
 236         mov     #byte_dest11, er1
 237         ldc     #0x87, exr
 238         stc     exr, @-er1      ; predecr dest (10)
 239
 240         test_h_gr32 byte_dest10, er1    ; er1 still contains address
 241
 242         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 243         test_gr_a5a5 2
 244         test_gr_a5a5 3
 245         test_gr_a5a5 4
 246         test_gr_a5a5 5
 247         test_gr_a5a5 6
 248         test_gr_a5a5 7
 249
 250 stc_ccr_ind:
 251         set_grs_a5a5
 252         set_ccr_zero
 253
 254         mov     #byte_dest11, er1
 255         ldc     #0xff, ccr
 256         stc     ccr, @er1       ; postinc dest (11)
 257
 258         test_h_gr32 byte_dest11, er1    ; er1 still contains address
 259
 260         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 261         test_gr_a5a5 2
 262         test_gr_a5a5 3
 263         test_gr_a5a5 4
 264         test_gr_a5a5 5
 265         test_gr_a5a5 6
 266         test_gr_a5a5 7
 267
 268 stc_exr_ind:
 269         set_grs_a5a5
 270         set_ccr_zero
 271
 272         mov     #byte_dest12, er1
 273         ldc     #0x87, exr
 274         stc     exr, @er1, exr  ; postinc dest (12)
 275
 276         test_h_gr32 byte_dest12, er1    ; er1 still contains address
 277
 278         test_gr_a5a5 0          ; Make sure other general regs not disturbed
 279         test_gr_a5a5 2
 280         test_gr_a5a5 3
 281         test_gr_a5a5 4
 282         test_gr_a5a5 5
 283         test_gr_a5a5 6
 284         test_gr_a5a5 7
 285
 286 .endif
 287
 288 .if (sim_cpu == h8sx)           ; New vbr and sbr registers for h8sx
 289 stc_sbr_reg:
 290         set_grs_a5a5
 291         set_ccr_zero
 292
 293         mov     #0xaaaaaaaa, er0
 294         ldc     er0, sbr        ; set sbr to 0xaaaaaaaa
 295         stc     sbr, er1        ; retreive and check sbr value
 296
 297         test_h_gr32 0xaaaaaaaa er1
 298         test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
 299         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 300         test_gr_a5a5 3
 301         test_gr_a5a5 4
 302         test_gr_a5a5 5
 303         test_gr_a5a5 6
 304         test_gr_a5a5 7
 305
 306 stc_vbr_reg:
 307         set_grs_a5a5
 308         set_ccr_zero
 309
 310         mov     #0xaaaaaaaa, er0
 311         ldc     er0, vbr        ; set sbr to 0xaaaaaaaa
 312         stc     vbr, er1        ; retreive and check sbr value
 313
 314         test_h_gr32 0xaaaaaaaa er1
 315         test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
 316         test_gr_a5a5 2          ; Make sure other general regs not disturbed
 317         test_gr_a5a5 3
 318         test_gr_a5a5 4
 319         test_gr_a5a5 5
 320         test_gr_a5a5 6
 321         test_gr_a5a5 7
 322
 323 check_results:
 324         ;; Now check results
 325         mov @byte_dest1, r0h
 326         cmp.b   #0xff, r0h
 327         beq .L1
 328         fail
 329
 330 .L1:    mov @byte_dest2, r0h
 331         cmp.b   #0x87, r0h
 332         beq .L2
 333         fail
 334
 335 .L2:    mov @byte_dest3, r0h
 336         cmp.b   #0xff, r0h
 337         beq .L3
 338         fail
 339
 340 .L3:    mov @byte_dest4, r0h
 341         cmp.b   #0x87, r0h
 342         beq .L4
 343         fail
 344
 345 .L4:    mov @byte_dest5, r0h
 346         cmp.b   #0xff, r0h
 347         beq .L5
 348         fail
 349
 350 .L5:    mov @byte_dest6, r0h
 351         cmp.b   #0x87, r0h
 352         beq .L6
 353         fail
 354
 355 .L6:    mov @byte_dest7, r0h
 356         cmp.b   #0xff, r0h
 357         beq .L7
 358         fail
 359
 360 .L7:    mov @byte_dest8, r0h
 361         cmp.b   #0x87, r0h
 362         beq .L8
 363         fail
 364
 365 .L8:    mov @byte_dest9, r0h
 366         cmp.b   #0xff, r0h
 367         beq .L9
 368         fail
 369
 370 .L9:    mov @byte_dest10, r0h
 371         cmp.b   #0x87, r0h
 372         beq .L10
 373         fail
 374
 375 .L10:   mov @byte_dest11, r0h
 376         cmp.b   #0xff, r0h
 377         beq .L11
 378         fail
 379
 380 .L11:   mov @byte_dest12, r0h
 381         cmp.b   #0x87, r0h
 382         beq .L12
 383         fail
 384
 385 .L12:
 386 .endif
 387         pass
 388
 389         exit 0