sim/tic80/ChangeLog

   1 Fri May 16 11:57:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
   2
   3         * ic (compute): Drop check for REG == 0, now always forced to
   4         zero.
   5
   6         * cpu.h (GPR_SET): New macro update the gpr.
   7         * insns (do_add): Use GPR_SET to update the GPR register.
   8
   9         * sim-calls.c (sim_fetch_register): Pretend that r0 is zero.
  10
  11         * Makefile.in (tmp-igen): Specify zero-r0 so that every
  12         instruction clears r0.
  13
  14         * interp.c (engine_run_until_stop): Igen now generates code to
  15         clear r0.
  16         (engine_step): Ditto.
  17
  18 Thu May 15 11:45:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  19
  20         * insns (do_shift): When rot==0 and zero/sign merge treat it as
  21         32.
  22         (set_fp_reg): For interger conversion, use sim-fpu fpu2i
  23         functions.
  24         (do_fmpy): Perform iii and uuu using integer arithmetic.
  25
  26         * Makefile.in (ENGINE_H): Assume everything depends on the fpu.
  27
  28         * insns (get_fp_reg): Use sim_fpu_u32to to perform unsigned
  29         conversion.
  30         (do_fcmp): Update to use new fp compare functions. Make reg nr arg
  31         instead of reg.  Stops fp overflow.
  32         (get_fp_reg): Assume val is valid when reg == 0.
  33         (set_fp_reg): Fix double conversion.
  34
  35         * misc.c (tic80_trace_fpu1): New function, trace simple fp op.
  36
  37         * insns (do_frnd): Add tracing.
  38
  39         * cpu.h (TRACE_FPU1): Ditto.
  40
  41         * insns (do_trap): Printf formatting.
  42
  43 Wed May 14 18:05:50 1997  Mike Meissner  <meissner@cygnus.com>
  44
  45         * misc.c (tic80_trace_fpu{3,2,2i}): Align columns with other
  46         insns.  Use %g to print floating point instead of %f in case the
  47         numbers are real large.
  48
  49 Tue May 13 18:00:10 1997  Mike Meissner  <meissner@cygnus.com>
  50
  51         * insns (do_trap): For system calls that are defined, but not
  52         provided return EINVAL. Temporarily add traps 74-79 to just print
  53         the register state.
  54
  55         * interp.c (engine_{run_until_stop,step}): Before executing
  56         instructions, make sure r0 == 0.
  57
  58 Tue May 13 16:39:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  59
  60         * alu.h (IMEM): Take full cia not just IP as argument.
  61
  62         * interp.c (engine_run_until_stop): Delete handling of annuled
  63         instructions.
  64         (engine_step): Ditto.
  65
  66         * insn (do_branch): New function.
  67         (do_bbo, do_bbz, do_bcnd, do_bsr, do_jsr): Use do_branch to handle
  68         annuled branches.
  69
  70 Mon May 12 17:15:52 1997  Mike Meissner  <meissner@cygnus.com>
  71
  72         * insns (do_{ld,st}): Fix tracing for ld/st.
  73
  74 Mon May 12 11:12:24 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  75
  76         * sim-calls.c (sim_stop_reason): Restore keep_running after a
  77         CNTRL-C, don't re-clear it.
  78
  79         * interp.c (engine_error): stop rather than signal with SIGABRT
  80         when an error.
  81
  82         * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
  83         rDest + 1. Also done by Michael Meissner  <meissner@cygnus.com>
  84         (do_st): Converse for store.
  85
  86         * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
  87
  88 Sun May 11 11:02:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  89
  90         * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
  91         was cleared.
  92
  93         * interp.c (engine_step): New function.  Single step the simulator
  94         taking care of cntrl-c during a step.
  95
  96         * sim-calls.c (sim_resume): Differentiate between stepping and
  97         running so that a cntrl-c during a step is reported.
  98
  99 Sun May 11 10:54:31 1997  Mark Alexander    <marka@cygnus.com>
 100
 101         * sim-calls.c (sim_fetch_register): Use correct reg base.
 102         (sim_store_register): Ditto.
 103
 104 Sun May 11 10:25:14 1997  Michael Meissner  <meissner@cygnus.com>
 105
 106         * cpu.h (tic80_trace_shift): Add declaration.
 107         (TRACE_SHIFT): New macro to trace shift instructions.
 108
 109         * misc.c (tic80_trace_alu2): Align spacing.
 110         (tic80_trace_shift): New function to trace shifts.
 111
 112         * insns (lmo): Add missing 0b prefix to bits.
 113         (do_shift): Use ~ (unsigned32)0, instead of -1.  Use TRACE_SHIFT
 114         instead of TRACE_ALU2.
 115         (sl r): Use EndMask as is, instead of using Source+1 register.
 116         (subu): Operands are unsigned, not signed.
 117         (do_{ld,st}): Fix endian problems with ld.d/st.d.
 118
 119 Sat May 10 12:35:47 1997  Michael Meissner  <meissner@cygnus.com>
 120
 121         * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
 122         signed.
 123
 124 Fri May  9 15:47:36 1997  Mike Meissner  <meissner@cygnus.com>
 125
 126         * insns (cmp_vals,do_cmp): Produce the correct bits as specified
 127         by the architecture.
 128         (xor): Fix xor immediate patterns to use the correct bits.
 129
 130 Fri May  9 09:55:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 131
 132         * alu.h (long_immediate): Adjust the CIA delay-pointer as well as
 133         the NIA when a 64bit insn.
 134
 135 Thu May  8 11:57:47 1997  Michael Meissner  <meissner@cygnus.com>
 136
 137         * insns (jsr,bsr): For non-allulled calls, set r31 so that the
 138         return address does not reexecute the instruction in the delay
 139         slot.
 140         (bbo,bbz): Complement bit number to reverse the one's complement
 141         that the assembler is required to do.
 142
 143         * misc.c (tic80_trace_*): Change format slightly to accomidate
 144         real large decimal values.
 145
 146 Thu May  8 14:07:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 147
 148         * sim-calls.c (sim_do_command): Implement.
 149         (sim_store_register): Fix typo T2H v H2T.
 150
 151 Wed May  7 11:48:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 152
 153         * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
 154         * insn: Clean up fpu tracing.
 155
 156         * sim-calls.c (sim_create_inferior): Start out with interrupts
 157         enabled.
 158
 159         * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
 160         sink
 161
 162         * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
 163
 164         * insns (do_*): Remove MY_INDEX/indx argument from support functions,
 165         igen now handles this.
 166
 167         * cpu.h (CR): New macro - access TIc80 control registers.
 168
 169         * misc.c: New file.
 170         (tic80_cr2index): New function, map control register opcode index
 171         into the internal CR enum.
 172
 173         * interp.c
 174         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
 175         here
 176         * misc.c: to here.
 177
 178         * Makefile.in (SIM_OBJS): Add misc.o.
 179
 180 Tue May  6 15:22:58 1997  Mike Meissner  <meissner@cygnus.com>
 181
 182         * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
 183         big endian hosts.
 184         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
 185         new functions.
 186         (TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
 187         trace various instruction types.
 188
 189         * insns: Modify all instructions to support semantic tracing.
 190
 191         * interp.c (toplevel): Include itable.h.
 192         (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
 193         functions to provide semantic level tracing information.
 194
 195 Mon May  5 11:50:43 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 196
 197         * alu.h: Update usage of core object to reflect recent changes in
 198         ../common/sim-*core.
 199         * sim-calls.c (sim_open): Ditto.
 200
 201 Mon May  5 14:10:17 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 202
 203         * insn (cmnd): No-op cache flushes.
 204
 205         * insns (do_trap): Allow writes to STDERR.
 206
 207         * Makefile.in (SIM_OBJS): Link in sim-fpu.o.
 208         (SIM_EXTRA_LIBS): Link in the math library.
 209
 210         * alu.h: Add support for floating point unit using sim-alu.
 211
 212         * insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
 213
 214 Fri May  2 14:57:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 215
 216         * sim-calls.c: Include sim-utils.h and sim-options.h.
 217
 218         * sim-main.h (sim_state): Drop sim_events and sim_core members,
 219         moved to simulator base type.
 220
 221         * alu.h (IMEM, MEM, STORE): Update track changes in common
 222         directory.
 223
 224         * insns: Drop cia argument from functions, igen now handles this.
 225
 226         * interp.c (engine_init): Include string.h/strings.h to define
 227         memset et.al.
 228
 229         * sim-main.h (sim_cia): Delcare, tracking common dir changes.
 230
 231         * cpu.h (sim_cpu): Update instruction_address with sim_cia.
 232
 233 Wed Apr 30 11:26:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 234
 235         * sim-main.h (signal.h): Include so that SIG* available to all
 236         callers of sig_halt.
 237
 238         * insns (do_shift): New function, implement shift operations.
 239         (do_trap): Add handler for trap 73 - SIGTRAP.
 240
 241 Tue Apr 29 10:58:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 242
 243         * alu.h (MEM, STORE): Force addresses to be correctly aligned.
 244
 245         * insns (do_jsr): Fix.
 246         (do_st, do_ld): Handle 64bit transfers.
 247         (do_trap): Match libgloss.
 248         (rdcr): Implement nop - Dest == r0 - variant.
 249
 250         * sim-calls.c (sim_create_inferior): Initialize SP.
 251
 252         * Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
 253         (support.o): Depends on ENGINE_H.
 254
 255         * cpu.h: Four accumulators.
 256
 257         * Makefile.in (tmp-igen): Include line number information in
 258         generated files.
 259
 260         * insns (dld, dst): Fill in.
 261
 262 Mon Apr 28 13:02:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 263
 264         * insns (vld): Fix instruction format wrong.
 265
 266 Thu Apr 24 16:43:09 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 267
 268         * dc: Add additional rules so that minor opcode files are
 269         detected.
 270         * insns: Enable more instructions.
 271
 272         * sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
 273         Implement.
 274
 275 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
 276
 277         * configure: Regenerated to track ../common/aclocal.m4 changes.
 278         * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
 279         * sim-calls.c (sim_open): Call sim_module_uninstall if argument
 280         parsing fails.  Call sim_post_argv_init.
 281         (sim_close): Call sim_module_uninstall.
 282
 283 Wed Apr 23 20:05:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 284
 285         * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
 286         * ic: Add fields for enabled instructions.
 287