sim/tic80/insns

   1 // Texas Instruments TMS320C80 (MVP) Simulator.
   2 // Copyright (C) 1997 Free Software Foundation, Inc.
   3 // Contributed by Cygnus Support.
   4 //
   5 // This file is part of GDB, the GNU debugger.
   6 //
   7 // This program is free software; you can redistribute it and/or modify
   8 // it under the terms of the GNU General Public License as published by
   9 // the Free Software Foundation; either version 2, or (at your option)
  10 // any later version.
  11 //
  12 // This program is distributed in the hope that it will be useful,
  13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 // GNU General Public License for more details.
  16 //
  17 // You should have received a copy of the GNU General Public License along
  18 // with this program; if not, write to the Free Software Foundation, Inc.,
  19 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21
  22 // The following is called when ever an illegal instruction is encountered.
  23 ::internal::illegal
  24         engine_error (SD, CPU, cia,
  25                       "illegal instruction at 0x%lx", cia.ip);
  26 // The following is called when ever an FP op is attempted with FPU disabled.
  27 ::internal::fp_unavailable
  28         engine_error (SD, CPU, cia,
  29                       "floating-point unavailable at 0x%lx", cia.ip);
  30
  31 // Handle a branch instruction
  32 instruction_address::function::do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink
  33         instruction_address nia;
  34         if (annul)
  35           {
  36             if (rLink_p)
  37               *rLink = cia.dp;
  38             nia.ip = target;
  39             nia.dp = target + 4;
  40           }
  41         else
  42           {
  43             if (rLink_p)
  44               *rLink = cia.dp + sizeof (instruction_word);
  45             nia.ip = cia.dp;
  46             nia.dp = target;
  47           }
  48         return nia;
  49
  50 // Signed Integer Add - add source1, source2, dest
  51 void::function::do_add:unsigned32 *rDest, signed32 source1, signed32 source2
  52         unsigned32 result;
  53         ALU_BEGIN (source1);
  54         ALU_ADD (source2);
  55         ALU_END (result);
  56         *rDest = result;
  57         TRACE_ALU3 (MY_INDEX, result, source1, source2);
  58         /* FIXME - a signed add may cause an exception */
  59 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
  60         do_add (_SD, rDest, vSource1, vSource2);
  61 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
  62         do_add (_SD, rDest, vSource1, vSource2);
  63 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
  64         long_immediate (LongSignedImmediate);
  65         do_add (_SD, rDest, LongSignedImmediate, vSource2);
  66
  67
  68 // Unsigned Integer Add - addu source1, source2, dest
  69 void::function::do_addu:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
  70         unsigned32 result = source1 + source2;
  71         TRACE_ALU3 (MY_INDEX, result, source1, source2);
  72         *rDest = result;
  73
  74 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
  75         do_addu (_SD, rDest, vSource1, vSource2);
  76 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
  77         do_addu (_SD, rDest, vSource1, vSource2);
  78 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
  79         long_immediate (LongSignedImmediate);
  80         do_addu (_SD, rDest, LongSignedImmediate, vSource2);
  81
  82
  83 void::function::do_and:signed32 *rDest, signed32 source1, signed32 source2
  84         unsigned32 result = source1 & source2;
  85         TRACE_ALU3 (MY_INDEX, result, source1, source2);
  86         *rDest = result;
  87
  88
  89 // and, and.tt
  90 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
  91         do_and (_SD, rDest, vSource1, vSource2);
  92 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
  93         do_and (_SD, rDest, vSource1, vSource2);
  94 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
  95         long_immediate (LongSignedImmediate);
  96         do_and (_SD, rDest, LongSignedImmediate, vSource2);
  97
  98
  99 // and.ff
 100 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
 101         do_and (_SD, rDest, ~vSource1, ~vSource2);
 102 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
 103         do_and (_SD, rDest, ~vSource1, ~vSource2);
 104 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
 105         long_immediate (LongSignedImmediate);
 106         do_and (_SD, rDest, ~LongSignedImmediate, ~vSource2);
 107
 108
 109 // and.ft
 110 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
 111         do_and (_SD, rDest, ~vSource1, vSource2);
 112 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
 113         do_and (_SD, rDest, ~vSource1, vSource2);
 114 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
 115         long_immediate (LongSignedImmediate);
 116         do_and (_SD, rDest, ~LongSignedImmediate, vSource2);
 117
 118
 119 // and.tf
 120 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
 121         do_and (_SD, rDest, vSource1, ~vSource2);
 122 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
 123         do_and (_SD, rDest, vSource1, ~vSource2);
 124 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
 125         long_immediate (LongSignedImmediate);
 126         do_and (_SD, rDest, LongSignedImmediate, ~vSource2);
 127
 128
 129 // bbo.[a]
 130 instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 131         int jump_p;
 132         address_word target = cia.ip + 4 * offset;
 133         bitnum = (~ bitnum) & 0x1f;
 134         if (MASKED32 (source, bitnum, bitnum))
 135           {
 136             nia = do_branch (_SD, annul, target, 0, NULL);
 137             jump_p = 1;
 138           }
 139         else
 140           jump_p = 0;
 141         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 142         return nia;
 143 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
 144         nia = do_bbo (_SD, nia, BITNUM, vSource, A, vSignedOffset);
 145 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
 146         nia = do_bbo (_SD, nia, BITNUM, vSource, A, rIndOff);
 147 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
 148         long_immediate (LongSignedImmediate);
 149         nia = do_bbo (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
 150
 151
 152 // bbz[.a]
 153 instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 154         int jump_p;
 155         address_word target = cia.ip + 4 * offset;
 156         bitnum = (~ bitnum) & 0x1f;
 157         if (!MASKED32 (source, bitnum, bitnum))
 158           {
 159             nia = do_branch (_SD, annul, target, 0, NULL);
 160             jump_p = 1;
 161           }
 162         else
 163           jump_p = 0;
 164         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 165         return nia;
 166 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
 167         nia = do_bbz (_SD, nia, BITNUM, vSource, A, vSignedOffset);
 168 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
 169         nia = do_bbz (_SD, nia, BITNUM, vSource, A, rIndOff);
 170 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
 171         long_immediate (LongSignedImmediate);
 172         nia = do_bbz (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
 173
 174
 175 // bcnd[.a]
 176 instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
 177         int condition;
 178         int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
 179         int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
 180         signed32 val = 0;
 181         address_word target = cia.ip + 4 * offset;
 182         switch (size)
 183           {
 184           case 0: val = SEXT32 (source, 7); break;
 185           case 1: val = SEXT32 (source, 15); break;
 186           case 2: val = source; break;
 187           default: engine_error (SD, CPU, cia, "bcnd - reserved size");
 188           }
 189         switch (code)
 190           {
 191           case 0: condition = 0; break;
 192           case 1: condition = val > 0; break;
 193           case 2: condition = val == 0; break;
 194           case 3: condition = val >= 0; break;
 195           case 4: condition = val < 0; break;
 196           case 5: condition = val != 0; break;
 197           case 6: condition = val <= 0; break;
 198           default: condition = 1; break;
 199           }
 200         if (condition)
 201           {
 202             nia = do_branch (_SD, annul, target, 0, NULL);
 203           }
 204         TRACE_COND_BR(MY_INDEX, condition, source, target);
 205         return nia;
 206 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
 207         nia = do_bcnd (_SD, nia, Code, vSource, A, vSignedOffset);
 208 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
 209         nia = do_bcnd (_SD, nia, Code, vSource, A, rIndOff);
 210 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
 211         long_immediate (LongSignedImmediate);
 212         nia = do_bcnd (_SD, nia, Code, vSource, A, LongSignedImmediate);
 213
 214
 215 // br[.a] - see bbz[.a]
 216
 217
 218 // brcr
 219 sim_cia::function::do_brcr:instruction_address nia, int cr
 220         if (cr >= 0x4000 || !(CPU)->is_user_mode)
 221           {
 222             unsigned32 control = CR (cr);
 223             unsigned32 ie = control & 0x00000001;
 224             unsigned32 pc = control & 0xfffffffc;
 225             unsigned32 is_user_mode = control & 0x00000002;
 226             (CPU)->is_user_mode = is_user_mode;
 227             nia.dp = pc;
 228             if (ie)
 229               (CPU)->cr[IE_CR] |= IE_CR_IE;
 230             else
 231               (CPU)->cr[IE_CR] &= ~IE_CR_IE;
 232           }
 233         TRACE_UCOND_BR (MY_INDEX, nia.dp);
 234         return nia;
 235 31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i
 236         nia = do_brcr (_SD, nia, UCRN);
 237 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r
 238         nia = do_brcr (_SD, nia, UCRN);
 239 31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l
 240         long_immediate (UnsignedControlRegisterNumber)
 241         nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber);
 242
 243
 244 // bsr[.a]
 245 instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
 246         address_word target = cia.ip + 4 * offset;
 247         nia = do_branch (_SD, annul, target, 1, rLink);
 248         TRACE_UCOND_BR (MY_INDEX, target);
 249         return nia;
 250 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
 251         nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
 252 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
 253         nia = do_bsr (_SD, nia, rLink, A, rIndOff);
 254 31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
 255         long_immediate (LongSignedImmediate);
 256         nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
 257
 258
 259 // cmnd
 260 void::function::do_cmnd:signed32 source
 261         int Reset = EXTRACTED32 (source, 31, 31);
 262         int Halt = EXTRACTED32 (source, 30, 30);
 263         int Unhalt = EXTRACTED32 (source, 29, 29);
 264         /* int ICR = EXTRACTED32 (source, 28, 28); */
 265         /* int DCR = EXTRACTED32 (source, 27, 27); */
 266         int Task = EXTRACTED32 (source, 14, 14);
 267         int Msg = EXTRACTED32 (source, 13, 13);
 268         int VC = EXTRACTED32 (source, 10, 10);
 269         int TC = EXTRACTED32 (source, 9, 9);
 270         int MP = EXTRACTED32 (source, 8, 8);
 271         int PP = EXTRACTED32 (source, 3, 0);
 272         /* what is implemented? */
 273         if (PP != 0)
 274           engine_error (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
 275                         (unsigned long) cia.ip);
 276         if (VC != 0)
 277           engine_error (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
 278                         (unsigned long) cia.ip);
 279         if (TC != 0)
 280           engine_error (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
 281                         (unsigned long) cia.ip);
 282         if (MP)
 283           {
 284             if (Reset || Halt)
 285               engine_halt (SD, CPU, cia, sim_exited, 0);
 286             if (Unhalt)
 287               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
 288                             (unsigned long) cia.ip);
 289             /* if (ICR || DCR); */
 290             if (Task)
 291               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
 292                             (unsigned long) cia.ip);
 293             if (Msg)
 294               engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
 295                             (unsigned long) cia.ip);
 296           }
 297         TRACE_SINK1 (MY_INDEX, source);
 298 31./,21.0b0000010,14.UI::::cmnd i
 299         do_cmnd (_SD, UI);
 300 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
 301         do_cmnd (_SD, vSource);
 302 31./,21.0b110000010,12.1,11./::::cmnd l
 303         long_immediate (LongUnsignedImmediate);
 304         do_cmnd (_SD, LongUnsignedImmediate);
 305
 306 // cmp
 307 unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
 308         unsigned32 field = 0;
 309         if (s1 == s2) field |= 0x001;
 310         if (s1 != s2) field |= 0x002;
 311         if (s1 >  s2) field |= 0x004;
 312         if (s1 <= s2) field |= 0x008;
 313         if (s1 <  s2) field |= 0x010;
 314         if (s1 >= s2) field |= 0x020;
 315         if (u1 >  u2) field |= 0x040;
 316         if (u1 <= u2) field |= 0x080;
 317         if (u1 <  u2) field |= 0x100;
 318         if (u1 >= u2) field |= 0x200;
 319         return field;
 320 void::function::do_cmp:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
 321         unsigned32 field = 0;
 322         field |= cmp_vals (_SD, source1, source1, source2, source2) << 20;
 323         field |= cmp_vals (_SD, (signed16)source1, (unsigned16)source1,
 324                            (signed16)source2, (unsigned16)source2) << 10;
 325         field |= cmp_vals (_SD, (signed8)source1, (unsigned8)source1,
 326                             (signed8)source2, (unsigned8)source2);
 327         TRACE_ALU3 (MY_INDEX, field, source1, source2);
 328         *rDest = field;
 329 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
 330         do_cmp (_SD, rDest, vSource1, vSource2);
 331 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
 332         do_cmp (_SD, rDest, vSource1, vSource2);
 333 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
 334         long_immediate (LongSignedImmediate);
 335         do_cmp (_SD, rDest, LongSignedImmediate, vSource2);
 336
 337
 338 // dcache
 339 31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i
 340         TRACE_NOP (MY_INDEX);
 341         /* NOP */
 342 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r
 343         TRACE_NOP (MY_INDEX);
 344         /* NOP */
 345 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l
 346         long_immediate (LongSignedImmediate);
 347         LongSignedImmediate++;
 348         TRACE_NOP (MY_INDEX);
 349         /* NOP */
 350
 351
 352 // dld[{.b|.h|.d}]
 353 void::function::do_dld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 354         do_ld (_SD, Dest, base, rBase, m, sz, S, offset);
 355 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
 356         do_dld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
 357 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
 358         long_immediate (LongSignedImmediateOffset);
 359         do_dld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 360
 361
 362 // dld.u[{.b|.h|.d}]
 363 void::function::do_dld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 364         do_ld_u (_SD, rDest, base, rBase, m, sz, S, offset);
 365 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
 366         do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
 367 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
 368         long_immediate (LongSignedImmediateOffset);
 369         do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 370
 371
 372 // dst[{.b|.h|.d}]
 373 void::function::do_dst:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 374         do_st (_SD, Source, base, rBase, m, sz, S, offset);
 375 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
 376         do_dst (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
 377 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
 378         long_immediate (LongSignedImmediateOffset);
 379         do_dst (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 380
 381
 382 // estop
 383 31./,21.0b1111111,14.1,13.0,12.0,11./::::estop
 384
 385 // etrap
 386 31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
 387 31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
 388 31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
 389
 390
 391 // exts - see shift.ds
 392
 393
 394 // extu - see shift.dz
 395
 396
 397 sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
 398         switch (precision)
 399           {
 400           case 0: /* single */
 401             return sim_fpu_32to (val);
 402           case 1: /* double */
 403             if (reg < 0)
 404               engine_error (SD, CPU, cia, "DP immediate invalid");
 405             if (reg & 1)
 406               engine_error (SD, CPU, cia, "DP FP register must be even");
 407             if (reg <= 1)
 408               engine_error (SD, CPU, cia, "DP FP register must be >= 2");
 409             return sim_fpu_64to (INSERTED64 (GPR (reg + 1), 63, 32)
 410                                  | INSERTED64 (GPR (reg), 31, 0));
 411           case 2: /* 32 bit signed integer */
 412             return sim_fpu_i32to (val);
 413           case 3: /* 32 bit unsigned integer */
 414             return sim_fpu_u32to (val);
 415           default:
 416             engine_error (SD, CPU, cia, "Unsupported FP precision");
 417           }
 418         return sim_fpu_i32to (0);
 419 void::function::set_fp_reg:int Dest, sim_fpu val, int PD
 420         switch (PD)
 421           {
 422           case 0: /* single */
 423             {
 424               GPR (Dest) = sim_fpu_to32 (val);
 425               break;
 426             }
 427           case 1: /* double */
 428             {
 429               unsigned64 v = sim_fpu_to64 (val);
 430               if (Dest & 1)
 431                 engine_error (SD, CPU, cia, "DP FP Dest register must be even");
 432               if (Dest <= 1)
 433                 engine_error (SD, CPU, cia, "DP FP Dest register must be >= 2");
 434               GPR (Dest + 0) = VL4_8 (v);
 435               GPR (Dest + 1) = VH4_8 (v);
 436               break;
 437             }
 438           case 2: /* signed */
 439             {
 440               GPR (Dest) = sim_fpu_to32i (val);
 441               break;
 442             }
 443           case 3: /* unsigned */
 444             {
 445               GPR (Dest) = sim_fpu_to32u (val);
 446               break;
 447             }
 448           default:
 449             engine_error (SD, CPU, cia, "Unsupported FP precision");
 450           }
 451
 452 // fadd.{s|d}{s|d}{s|d}
 453 void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
 454         sim_fpu ans = sim_fpu_add (s1, s2);
 455         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 456         set_fp_reg (_SD, Dest, ans, PD);
 457 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
 458         do_fadd (_SD, Dest, PD,
 459                  get_fp_reg (_SD, Source1, vSource1, P1),
 460                  get_fp_reg (_SD, Source2, vSource2, P2));
 461 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
 462         long_immediate (SinglePrecisionFloatingPoint);
 463         do_fadd (_SD, Dest, PD,
 464                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 465                  get_fp_reg (_SD, Source2, vSource2, P2));
 466
 467
 468 // fcmp.{s|d}{s|d}{s|d}
 469 void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
 470         unsigned32 result = 0;
 471         if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
 472           result |= BIT32 (30);
 473         else
 474           {
 475             result |= BIT32 (31);
 476             if (sim_fpu_is_eq (s1, s2)) result |= BIT32(20);
 477             if (sim_fpu_is_ne (s1, s2)) result |= BIT32(21);
 478             if (sim_fpu_is_gt (s1, s2)) result |= BIT32(22);
 479             if (sim_fpu_is_le (s1, s2)) result |= BIT32(23);
 480             if (sim_fpu_is_lt (s1, s2)) result |= BIT32(24);
 481             if (sim_fpu_is_ge (s1, s2)) result |= BIT32(25);
 482             if (sim_fpu_is_lt (s1, sim_fpu_i32to (0))
 483                 || sim_fpu_is_gt (s1, s2)) result |= BIT32(26);
 484             if (sim_fpu_is_lt (sim_fpu_i32to (0), s1)
 485                 && sim_fpu_is_lt (s1, s2)) result |= BIT32(27);
 486             if (sim_fpu_is_le (sim_fpu_i32to (0), s1)
 487                 && sim_fpu_is_le (s1, s2)) result |= BIT32(28);
 488             if (sim_fpu_is_le (s1, sim_fpu_i32to (0))
 489                 || sim_fpu_is_ge (s1, s2)) result |= BIT32(29);
 490           }
 491         *rDest = result;
 492         TRACE_FPU2I (MY_INDEX, result, s1, s2);
 493 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
 494         do_fcmp (_SD, rDest,
 495                  get_fp_reg (_SD, Source1, vSource1, P1),
 496                  get_fp_reg (_SD, Source2, vSource2, P2));
 497 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
 498         long_immediate (SinglePrecisionFloatingPoint);
 499         do_fcmp (_SD, rDest,
 500                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 501                  get_fp_reg (_SD, Source2, vSource2, P2));
 502
 503
 504
 505 // fdiv.{s|d}{s|d}{s|d}
 506 void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
 507         sim_fpu ans = sim_fpu_div (s1, s2);
 508         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 509         set_fp_reg (_SD, Dest, ans, PD);
 510 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
 511         do_fdiv (_SD, Dest, PD,
 512                  get_fp_reg (_SD, Source1, vSource1, P1),
 513                  get_fp_reg (_SD, Source2, vSource2, P2));
 514 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
 515         long_immediate (SinglePrecisionFloatingPoint);
 516         do_fdiv (_SD, Dest, PD,
 517                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 518                  get_fp_reg (_SD, Source2, vSource2, P2));
 519
 520
 521 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 522 void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
 523         switch (PD)
 524           {
 525           case 2: /* signed */
 526             {
 527               GPR (Dest) = sim_fpu_to64i (s1) * sim_fpu_to64i (s2);
 528               TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
 529               break;
 530             }
 531           case 3: /* unsigned */
 532             {
 533               GPR (Dest) = sim_fpu_to64u (s1) * sim_fpu_to64u (s2);
 534               TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
 535               break;
 536             }
 537           default:
 538             {
 539               sim_fpu ans = sim_fpu_mul (s1, s2);
 540               set_fp_reg (_SD, Dest, ans, PD);
 541               TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 542             }
 543           }
 544 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
 545         do_fmpy (_SD, Dest, PD,
 546                  get_fp_reg (_SD, Source1, vSource1, P1),
 547                  get_fp_reg (_SD, Source2, vSource2, P2));
 548 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
 549         long_immediate (SinglePrecisionFloatingPoint);
 550         do_fmpy (_SD, Dest, PD,
 551                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 552                  get_fp_reg (_SD, Source2, vSource2, P2));
 553
 554
 555 // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 556 void::function::do_frnd:int Dest, int PD, sim_fpu s1
 557         set_fp_reg (_SD, Dest, s1, PD);
 558         TRACE_FPU1 (MY_INDEX, s1);
 559 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
 560         do_frnd (_SD, Dest, PD,
 561                  get_fp_reg (_SD, Source, vSource, P1));
 562 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
 563         long_immediate (SinglePrecisionFloatingPoint);
 564         do_frnd (_SD, Dest, PD,
 565                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 566
 567
 568 // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 569 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
 570         do_frnd (_SD, Dest, PD,
 571                  get_fp_reg (_SD, Source, vSource, P1));
 572 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
 573         long_immediate (SinglePrecisionFloatingPoint);
 574         do_frnd (_SD, Dest, PD,
 575                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 576
 577
 578 // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 579 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
 580         do_frnd (_SD, Dest, PD,
 581                  get_fp_reg (_SD, Source, vSource, P1));
 582 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
 583         long_immediate (SinglePrecisionFloatingPoint);
 584         do_frnd (_SD, Dest, PD,
 585                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 586
 587
 588 // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 589 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
 590         do_frnd (_SD, Dest, PD,
 591                  get_fp_reg (_SD, Source, vSource, P1));
 592 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
 593         long_immediate (SinglePrecisionFloatingPoint);
 594         do_frnd (_SD, Dest, PD,
 595                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 596
 597
 598 // fsqrt.{s|d}{s|d}{s|d}
 599 #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 600 #       sim_io_error ("fsqrt");
 601 31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
 602 #       do_fsqrt (_SD, rDest, vSource1, vSource2);
 603 31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
 604 #       do_fsqrt (_SD, rDest, LongSignedImmediate, vSource2);
 605
 606
 607 // fsub.{s|d}{s|d}{s|d}
 608 void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
 609         sim_fpu ans = sim_fpu_sub (s1, s2);
 610         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 611         set_fp_reg (_SD, Dest, ans, PD);
 612 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
 613         do_fsub (_SD, Dest, PD,
 614                  get_fp_reg (_SD, Source1, vSource1, P1),
 615                  get_fp_reg (_SD, Source2, vSource2, P2));
 616 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
 617         long_immediate (SinglePrecisionFloatingPoint);
 618         do_fsub (_SD, Dest, PD,
 619                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 620                  get_fp_reg (_SD, Source2, vSource2, P2));
 621
 622
 623 // illop
 624 31./,21.0b0000000,14./::::illop
 625 31./,21.0b111111111,12./::::illop l
 626
 627
 628 // ins - see sl.im
 629
 630
 631 // jsr[.a]
 632 instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
 633         address_word target = offset + base;
 634         TRACE_UCOND_BR (MY_INDEX, target);
 635         nia = do_branch (_SD, annul, target, 1, rLink);
 636         if (nia.dp & 0x3)
 637           engine_error (SD, CPU, cia,
 638                         "0x%lx: destination address 0x%lx misaligned",
 639                         (unsigned long) cia.ip,
 640                         (unsigned long) nia.dp);
 641         return nia;
 642 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
 643         nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, vBase);
 644 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
 645         nia = do_jsr (_SD, nia, rLink, A, vSource1, vBase);
 646 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
 647         long_immediate (LongSignedImmediate);
 648         nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, vBase);
 649
 650
 651 // ld[{.b.h.d}]
 652 void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 653         unsigned32 addr;
 654         switch (sz)
 655           {
 656           case 0:
 657             addr = base + (S ? (offset << 0) : offset);
 658             if (m)
 659               *rBase = addr;
 660             GPR(Dest) = MEM (signed, addr, 1);
 661             break;
 662           case 1:
 663             addr = base + (S ? (offset << 1) : offset);
 664             if (m)
 665               *rBase = addr;
 666             GPR(Dest) = MEM (signed, addr, 2);
 667             break;
 668           case 2:
 669             addr = base + (S ? (offset << 2) : offset);
 670             if (m)
 671               *rBase = addr;
 672             GPR(Dest) = MEM (signed, addr, 4);
 673             break;
 674           case 3:
 675             {
 676               signed64 val;
 677               if (Dest & 0x1)
 678                 engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
 679                               cia.ip, Dest);
 680               addr = base + (S ? (offset << 3) : offset);
 681               if (m)
 682                 *rBase = addr;
 683               val = MEM (signed, addr, 8);
 684               GPR(Dest + 1) = VH4_8 (val);
 685               GPR(Dest + 0) = VL4_8 (val);
 686             }
 687             break;
 688           default:
 689             addr = -1;
 690             engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
 691           }
 692         TRACE_LD (MY_INDEX, GPR(Dest), m, S, base, offset);
 693 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
 694         do_ld (_SD, Dest, vBase, rBase, m, sz, 0, vSignedOffset);
 695 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
 696         do_ld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
 697 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
 698         long_immediate (LongSignedImmediateOffset);
 699         do_ld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 700
 701
 702 // ld.u[{.b.h.d}]
 703 void::function::do_ld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 704         unsigned32 addr;
 705         switch (sz)
 706           {
 707           case 0:
 708             addr = base + (S ? (offset << 0) : offset);
 709             *rDest = MEM (unsigned, addr, 1);
 710             break;
 711           case 1:
 712             addr = base + (S ? (offset << 1) : offset);
 713             *rDest = MEM (unsigned, addr, 2);
 714             break;
 715           default:
 716             addr = -1;
 717             engine_error (SD, CPU, cia, "ld.u - invalid sz %d", sz);
 718           }
 719         if (m)
 720           *rBase = addr;
 721         TRACE_LD (MY_INDEX, m, S, *rDest, base, offset);
 722 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
 723         do_ld_u (_SD, rDest, vBase, rBase, m, sz, 0, vSignedOffset);
 724 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
 725         do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
 726 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
 727         long_immediate (LongSignedImmediateOffset);
 728         do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 729
 730
 731 // lmo
 732 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
 733         int b;
 734         for (b = 0; b < 32; b++)
 735           if (vSource & BIT32 (31 - b))
 736             break;
 737         TRACE_ALU2 (MY_INDEX, b, vSource);
 738         *rDest = b;
 739
 740
 741 // nop - see rdcr 0, r0
 742
 743
 744 void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 745         unsigned32 result = Source1 | Source2;
 746         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 747         *rDest = result;
 748
 749
 750 // or, or.tt
 751 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
 752         do_or (_SD, rDest, vSource1, vSource2);
 753 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
 754         do_or (_SD, rDest, vSource1, vSource2);
 755 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
 756         long_immediate (LongUnsignedImmediate);
 757         do_or (_SD, rDest, LongUnsignedImmediate, vSource2);
 758
 759
 760 // or.ff
 761 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
 762         do_or (_SD, rDest, ~vSource1, ~vSource2);
 763 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
 764         do_or (_SD, rDest, ~vSource1, ~vSource2);
 765 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
 766         long_immediate (LongUnsignedImmediate);
 767         do_or (_SD, rDest, ~LongUnsignedImmediate, ~vSource2);
 768
 769
 770 // or.ft
 771 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
 772         do_or (_SD, rDest, ~vSource1, vSource2);
 773 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
 774         do_or (_SD, rDest, ~vSource1, vSource2);
 775 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
 776         long_immediate (LongUnsignedImmediate);
 777         do_or (_SD, rDest, ~LongUnsignedImmediate, vSource2);
 778
 779
 780 // or.tf
 781 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
 782         do_or (_SD, rDest, vSource1, ~vSource2);
 783 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
 784         do_or (_SD, rDest, vSource1, ~vSource2);
 785 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
 786         long_immediate (LongUnsignedImmediate);
 787         do_or (_SD, rDest, LongUnsignedImmediate, ~vSource2);
 788
 789
 790 // rdcr
 791 void::function::do_rdcr:unsigned32 Dest, int cr
 792         TRACE_SINK2 (MY_INDEX, Dest, cr);
 793         GPR (Dest) = CR (cr);
 794 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
 795         do_rdcr (_SD, Dest, UCRN);
 796 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
 797         do_rdcr (_SD, Dest, UCRN);
 798 31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
 799         long_immediate (UnsignedControlRegisterNumber);
 800         do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
 801
 802
 803 // rmo
 804 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
 805         int b;
 806         for (b = 0; b < 32; b++)
 807           if (vSource & BIT32 (b))
 808             break;
 809         if (b < 32)
 810           b = 31 - b;
 811         TRACE_ALU2 (MY_INDEX, b, vSource);
 812         *rDest = b;
 813
 814
 815 // rotl - see sl.dz
 816
 817
 818 // rotr - see sl.dz
 819
 820
 821 // shl - see sl.iz
 822
 823
 824 // sl.{d|e|i}{m|s|z}
 825 void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, int EndMask, int Rotate
 826         /* see 10-30 for a reasonable description */
 827         unsigned32 input = source;
 828         unsigned32 rotated;
 829         unsigned32 endmask;
 830         unsigned32 shiftmask;
 831         unsigned32 cm;
 832         int nRotate;
 833         /* rotate the source */
 834         if (n)
 835           {
 836             rotated = ROTR32 (source, Rotate);
 837             nRotate = (- Rotate) & 31;
 838           }
 839         else
 840           {
 841             rotated = ROTL32 (source, Rotate);
 842             nRotate = Rotate;
 843           }
 844         /* form the end mask */
 845         if (EndMask == 0)
 846           endmask = ~ (unsigned32)0;
 847         else
 848           endmask = (1 << EndMask) - 1;
 849         if (i)
 850           endmask = ~endmask;
 851         /* form the shiftmask */
 852         switch (Merge)
 853           {
 854           case 0: case 1: case 2:
 855             shiftmask = ~ (unsigned32)0;        /* disabled */
 856             break;
 857           case 3: case 5:                       /* enabled - 0 -> 32 */
 858             if (nRotate == 0)
 859               shiftmask = ~ (unsigned32)0;
 860             else
 861               shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
 862             break;
 863           case 4:
 864             shiftmask = ((1 << nRotate) - 1);   /* enabled - 0 -> 0 */
 865             break;
 866           case 6: case 7:
 867             shiftmask = ~((1 << nRotate) - 1);  /* inverted */
 868             break;
 869           default:
 870             engine_error (SD, CPU, cia,
 871                           "0x%lx: Invalid merge (%d) for shift",
 872                           cia.ip, source);
 873             shiftmask = 0;
 874           }
 875         /* and the composite mask */
 876         cm = shiftmask & endmask;
 877         /* and merge */
 878         switch (Merge)
 879           {
 880           case 0: case 3: case 6:               /* zero */
 881             GPR (Dest) = rotated & cm;
 882             break;
 883           case 1: case 4: case 7:               /* merge */
 884             GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
 885             break;
 886           case 2: case 5:                       /* sign */
 887             {
 888               int b;
 889               GPR (Dest) = rotated & cm;
 890               for (b = 1; b <= 31; b++)
 891                 if (!MASKED32 (cm, b, b))
 892                   GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
 893                                             b, b);
 894             }
 895             break;
 896           default:
 897             engine_error (SD, CPU, cia,
 898                           "0x%lx: Invalid merge (%d)",
 899                           cia.ip, source);
 900
 901           }
 902         TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
 903 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
 904         do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, Rotate);
 905 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
 906         do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, GPR (RotReg) & 31);
 907
 908
 909 // sli.{d|e|i}{m|s|z} - see shift
 910
 911
 912 // sr.{d|e|i}{m|s|z} - see shift
 913
 914
 915 // sra - see sr.es - see shift
 916
 917
 918 // sri.{d|e|i}{m|s|z} - see shift
 919
 920
 921 // srl - see sr.ez
 922
 923
 924 // st[{.b|.h|.d}]
 925 void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 926         unsigned32 addr;
 927         switch (sz)
 928           {
 929           case 0:
 930             addr = base + (S ? (offset << 0) : offset);
 931             STORE (addr, 1, GPR(Source));
 932             break;
 933           case 1:
 934             addr = base + (S ? (offset << 1) : offset);
 935             STORE (addr, 2, GPR(Source));
 936             break;
 937           case 2:
 938             addr = base + (S ? (offset << 2) : offset);
 939             STORE (addr, 4, GPR(Source));
 940             break;
 941           case 3:
 942             {
 943               signed64 val;
 944               if (Source & 0x1)
 945                 engine_error (SD, CPU, cia,
 946                               "0x%lx: st.d with odd source register %d",
 947                               cia.ip, Source);
 948               addr = base + (S ? (offset << 3) : offset);
 949               val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
 950               STORE (addr, 8, val);
 951             }
 952             break;
 953           default:
 954             addr = -1;
 955             engine_error (SD, CPU, cia, "st - invalid sz %d", sz);
 956           }
 957         if (m)
 958           *rBase = addr;
 959         TRACE_ST (MY_INDEX, Source, m, S, base, offset);
 960 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
 961         do_st (_SD, Source, vBase, rBase, m, sz, 0, vSignedOffset);
 962 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
 963         do_st (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
 964 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
 965         long_immediate (LongSignedImmediateOffset);
 966         do_st (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 967
 968
 969 // sub
 970 void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
 971         ALU_BEGIN (Source1);
 972         ALU_SUB (Source2);
 973         ALU_END (*rDest);
 974         TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
 975 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
 976         do_sub (_SD, rDest, vSource1, vSource2);
 977 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
 978         do_sub (_SD, rDest, vSource1, vSource2);
 979 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
 980         long_immediate (LongSignedImmediate);
 981         do_sub (_SD, rDest, LongSignedImmediate, vSource2);
 982
 983
 984 // subu
 985 void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
 986         unsigned32 result = Source1 - Source2;
 987         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 988         *rDest = result;
 989 // NOTE - the book has 15.1 which conflicts with subu.
 990 31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i
 991         do_subu (_SD, rDest, vSource1, vSource2);
 992 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
 993         do_subu (_SD, rDest, vSource1, vSource2);
 994 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
 995         long_immediate (LongSignedImmediate);
 996         do_subu (_SD, rDest, LongSignedImmediate, vSource2);
 997
 998
 999 // swcr
1000 void::function::do_swcr:int Dest, signed32 source, signed32 cr
1001         tic80_control_regs reg = tic80_index2cr (cr);
1002         /* cache the old CR value */
1003         unsigned32 old_cr = CR (cr);
1004         /* Handle the write if allowed */
1005         if (cr >= 0x4000 || !(CPU)->is_user_mode)
1006           switch (reg)
1007             {
1008             case INTPEN_CR:
1009               CR (cr) &= ~source;
1010               break;
1011             default:
1012               CR (cr) = source;
1013               break;
1014             }
1015         /* Finish off the read */
1016         GPR (Dest) = old_cr;
1017         TRACE_SINK3 (MY_INDEX, source, cr, Dest);
1018 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
1019         do_swcr (_SD, Dest, vSource, UCRN);
1020 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
1021         do_swcr (_SD, Dest, vSource, UCRN);
1022 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
1023         long_immediate (LongUnsignedControlRegister);
1024         do_swcr (_SD, Dest, vSource, LongUnsignedControlRegister);
1025
1026
1027 // trap
1028 void::function::do_trap:unsigned32 trap_number
1029         int i;
1030         TRACE_SINK1 (MY_INDEX, trap_number);
1031         switch (trap_number)
1032           {
1033           case 72:
1034             switch (GPR(15))
1035               {
1036               case 1: /* EXIT */
1037                 {
1038                   engine_halt (SD, CPU, cia, sim_exited, GPR(2));
1039                   break;
1040                 }
1041               case 4: /* WRITE */
1042                 {
1043                   int i;
1044                   if (GPR(2) == 1)
1045                     for (i = 0; i < GPR(6); i++)
1046                       {
1047                         char c;
1048                         c = MEM (unsigned, GPR(4) + i, 1);
1049                         sim_io_write_stdout (SD, &c, 1);
1050                       }
1051                   else if (GPR(2) == 2)
1052                     for (i = 0; i < GPR(6); i++)
1053                       {
1054                         char c;
1055                         c = MEM (unsigned, GPR(4) + i, 1);
1056                         sim_io_write_stderr (SD, &c, 1);
1057                       }
1058                   else
1059                     engine_error (SD, CPU, cia,
1060                                   "0x%lx: write to invalid fid %d",
1061                                   (unsigned long) cia.ip, GPR(2));
1062                   GPR(2) = GPR(6);
1063                   break;
1064                 }
1065               default:
1066                 /* For system calls which are defined, just return EINVAL instead of trapping */
1067                 if (GPR(15) <= 204)
1068                   {
1069                     GPR(2) = -22;               /* -EINVAL */
1070                     break;
1071                   }
1072                 engine_error (SD, CPU, cia,
1073                               "0x%lx: unknown syscall %d",
1074                               (unsigned long) cia.ip, GPR(15));
1075               }
1076             break;
1077           case 73:
1078             engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP);
1079
1080           /* Add a few traps for now to print the register state */
1081           case 74:
1082           case 75:
1083           case 76:
1084           case 77:
1085           case 78:
1086           case 79:
1087             if (!TRACE_ALU_P (CPU))
1088               trace_one_insn (SD, CPU, cia.ip, 1, itable[MY_INDEX].file,
1089                               itable[MY_INDEX].line_nr, "trap",
1090                               "Trap %ld", (long) trap_number);
1091
1092             for (i = 0; i < 32; i++)
1093               sim_io_eprintf (SD, "%s0x%.8lx%s", ((i % 8) == 0) ? "\t" : " ", (long)GPR(i),
1094                               (((i+1) % 8) == 0) ? "\n" : "");
1095             sim_io_write_stderr (SD, "\n", 1);
1096             break;
1097
1098           default:
1099             engine_error (SD, CPU, cia,
1100                           "0x%lx: unsupported trap %d",
1101                           (unsigned long) cia.ip, trap_number);
1102           }
1103 31./,27.0,26./,21.0b0000001,14.UTN::::trap i
1104         do_trap (_SD, UTN);
1105 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
1106         do_trap (_SD, UTN);
1107 31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
1108         long_immediate (UTN);
1109         do_trap (_SD, UTN);
1110
1111
1112 // vadd.{s|d}{s|d}
1113 31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r
1114 31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l
1115
1116
1117 // vld{0|1}.{s|d} - see above - same instruction
1118 #31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld
1119
1120
1121 // vmac.ss{s|d}
1122 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra
1123 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr
1124 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia
1125 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir
1126
1127
1128 // vmpy.{s|d}{s|d}
1129 31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r
1130 31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l
1131
1132
1133 // vmsc.ss{s|d}
1134 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra
1135 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr
1136 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia
1137 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir
1138
1139
1140 // vmsub.{s|d}{s|d}
1141 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r
1142 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l
1143
1144
1145 // vrnd.{s|d}{s|d}
1146 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r
1147 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l
1148
1149
1150 // vrnd.{i|u}{s|d}
1151 31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r
1152 31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l
1153
1154
1155 // vst.{s|d} - see above - same instruction
1156 #31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst
1157
1158
1159 // vsub.{i|u}{s|d}
1160 31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r
1161 31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l
1162
1163
1164 // wrcr - see swcr, creg, source, r0
1165
1166
1167 // xnor
1168 void::function::do_xnor:signed32 *rDest, signed32 source1, signed32 source2
1169         unsigned32 result = ~ (source1 ^ source2);
1170         TRACE_ALU3 (MY_INDEX, result, source1, source2);
1171         *rDest = result;
1172 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
1173         do_xnor (_SD, rDest, vSource1, vSource2);
1174 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
1175         do_xnor (_SD, rDest, vSource1, vSource2);
1176 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
1177         long_immediate (LongUnsignedImmediate);
1178         do_xnor (_SD, rDest, LongUnsignedImmediate, vSource2);
1179
1180
1181 // xor
1182 void::function::do_xor:signed32 *rDest, signed32 source1, signed32 source2
1183         unsigned32 result = source1 ^ source2;
1184         TRACE_ALU3 (MY_INDEX, result, source1, source2);
1185         *rDest = result;
1186 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
1187         do_xor (_SD, rDest, vSource1, vSource2);
1188 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
1189         do_xor (_SD, rDest, vSource1, vSource2);
1190 31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l
1191         long_immediate (LongUnsignedImmediate);
1192         do_xor (_SD, rDest, LongUnsignedImmediate, vSource2);