sim/tic80/insns

   1 // Texas Instruments TMS320C80 (MVP) Simulator.
   2 // Copyright (C) 1997 Free Software Foundation, Inc.
   3 // Contributed by Cygnus Support.
   4 //
   5 // This file is part of GDB, the GNU debugger.
   6 //
   7 // This program is free software; you can redistribute it and/or modify
   8 // it under the terms of the GNU General Public License as published by
   9 // the Free Software Foundation; either version 2, or (at your option)
  10 // any later version.
  11 //
  12 // This program is distributed in the hope that it will be useful,
  13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 // GNU General Public License for more details.
  16 //
  17 // You should have received a copy of the GNU General Public License along
  18 // with this program; if not, write to the Free Software Foundation, Inc.,
  19 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21
  22 // The following is called when ever an illegal instruction is
  23 // encountered
  24 ::internal::illegal
  25         engine_error (SD, CPU, cia, "illegal instruction at 0x%lx", cia.ip);
  26
  27 // Signed Integer Add - add source1, source2, dest
  28 void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2
  29         ALU_BEGIN (Source1);
  30         ALU_ADD (Source2);
  31         ALU_END (*rDest);
  32         /* FIXME - a signed add may cause an exception */
  33 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
  34         do_add (_SD, rDest, vSource1, rSource2);
  35 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
  36         do_add (_SD, rDest, rSource1, rSource2);
  37 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
  38         long_immediate (LongSignedImmediate);
  39         do_add (_SD, rDest, LongSignedImmediate, rSource2);
  40
  41
  42 // Unsigned Integer Add - addu source1, source2, dest
  43 void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
  44         *rDest = Source1 + Source2;
  45 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
  46         do_addu (_SD, rDest, vSource1, rSource2);
  47 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
  48         do_addu (_SD, rDest, rSource1, rSource2);
  49 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
  50         long_immediate (LongSignedImmediate);
  51         do_addu (_SD, rDest, LongSignedImmediate, rSource2);
  52
  53
  54 void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
  55         *rDest = Source1 & Source2;
  56
  57
  58 // and, and.tt
  59 31.Dest,26.Source2,21.0b0010001,14.SignedImmediate::::and.tt i
  60         do_and (_SD, rDest, vSource1, rSource2);
  61 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
  62         do_and (_SD, rDest, rSource1, rSource2);
  63 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
  64         long_immediate (LongSignedImmediate);
  65         do_and (_SD, rDest, LongSignedImmediate, rSource2);
  66
  67
  68 // and.ff
  69 31.Dest,26.Source2,21.0b0011000,14.SignedImmediate::::and.ff i
  70         do_and (_SD, rDest, ~vSource1, ~rSource2);
  71 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
  72         do_and (_SD, rDest, ~rSource1, ~rSource2);
  73 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
  74         long_immediate (LongSignedImmediate);
  75         do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2);
  76
  77
  78 // and.ft
  79 31.Dest,26.Source2,21.0b0010100,14.SignedImmediate::::and.ft i
  80         do_and (_SD, rDest, ~vSource1, rSource2);
  81 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
  82         do_and (_SD, rDest, ~rSource1, rSource2);
  83 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
  84         long_immediate (LongSignedImmediate);
  85         do_and (_SD, rDest, ~LongSignedImmediate, rSource2);
  86
  87
  88 // and.tf
  89 31.Dest,26.Source2,21.0b0010010,14.SignedImmediate::::and.tf i
  90         do_and (_SD, rDest, vSource1, ~rSource2);
  91 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
  92         do_and (_SD, rDest, rSource1, ~rSource2);
  93 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
  94         long_immediate (LongSignedImmediate);
  95         do_and (_SD, rDest, LongSignedImmediate, ~rSource2);
  96
  97
  98 // bbo.[a]
  99 instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 100         if (MASKED32 (source, bitnum, bitnum))
 101           {
 102             if (annul)
 103               nia.ip = -1;
 104             nia.dp = cia.ip + 4 * offset;
 105           }
 106         return nia;
 107 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
 108         nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset);
 109 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
 110         nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff);
 111 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
 112         long_immediate (LongSignedImmediate);
 113         nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
 114
 115
 116 // bbz[.a]
 117 instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 118         if (!MASKED32 (source, bitnum, bitnum))
 119           {
 120             if (annul)
 121               nia.ip = -1;
 122             nia.dp = cia.ip + 4 * offset;
 123           }
 124         return nia;
 125 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
 126         nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset);
 127 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
 128         nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff);
 129 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
 130         long_immediate (LongSignedImmediate);
 131         nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
 132
 133
 134 // bcnd[.a]
 135 instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
 136         int condition;
 137         int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
 138         int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
 139         signed32 val = 0;
 140         switch (size)
 141           {
 142           case 0: val = SEXT32 (source, 7); break;
 143           case 1: val = SEXT32 (source, 15); break;
 144           case 2: val = source; break;
 145           default: engine_error (SD, CPU, cia, "bcnd - reserved size");
 146           }
 147         switch (code)
 148           {
 149           case 0: condition = 0; break;
 150           case 1: condition = val > 0; break;
 151           case 2: condition = val == 0; break;
 152           case 3: condition = val >= 0; break;
 153           case 4: condition = val < 0; break;
 154           case 5: condition = val != 0; break;
 155           case 6: condition = val <= 0; break;
 156           default: condition = 1; break;
 157           }
 158         if (condition)
 159           {
 160             if (annul)
 161               nia.ip = -1;
 162             nia.dp = cia.ip + 4 * offset;
 163           }
 164         return nia;
 165 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
 166         nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset);
 167 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
 168         nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff);
 169 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
 170         long_immediate (LongSignedImmediate);
 171         nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate);
 172
 173
 174 // br[.a] - see bbz[.a]
 175
 176
 177 // brcr
 178 #void::function::do_brcr:unsigned32 offset
 179 #       sim_io_error ("brcr");
 180 31.//,27.0,26.//,21.0b0000110,14.CRN::::brcr i
 181 #       nia = do_brcr (_SD, rCRN_val);
 182 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.Source1::::brcr r
 183 #       nia = do_brcr (_SD, CRN[rSource1]);
 184 31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l
 185 #       nia = do_brcr (_SD, CRN[SL]);
 186
 187
 188 // bsr[.a]
 189 instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
 190         if (annul)
 191           {
 192             *rLink = nia.ip;
 193             nia.ip = -1;
 194           }
 195         else
 196           *rLink = cia.dp + sizeof (instruction_word);
 197         nia.dp = cia.ip + 4 * offset;
 198         return nia;
 199 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
 200         nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
 201 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
 202         nia = do_bsr (_SD, nia, rLink, A, rIndOff);
 203 31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
 204         long_immediate (LongSignedImmediate);
 205         nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
 206
 207
 208 // cmnd
 209 void::function::do_cmnd:signed32 source
 210         int Reset = EXTRACTED32 (source, 31, 31);
 211         int Halt = EXTRACTED32 (source, 30, 30);
 212         int Unhalt = EXTRACTED32 (source, 29, 29);
 213         /* int ICR = EXTRACTED32 (source, 28, 28); */
 214         /* int DCR = EXTRACTED32 (source, 27, 27); */
 215         int Task = EXTRACTED32 (source, 14, 14);
 216         int Msg = EXTRACTED32 (source, 13, 13);
 217         int VC = EXTRACTED32 (source, 10, 10);
 218         int TC = EXTRACTED32 (source, 9, 9);
 219         int MP = EXTRACTED32 (source, 8, 8);
 220         int PP = EXTRACTED32 (source, 3, 0);
 221         /* what is implemented? */
 222         if (PP != 0)
 223           engine_error (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
 224                         (unsigned long) cia.ip);
 225         if (VC != 0)
 226           engine_error (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
 227                         (unsigned long) cia.ip);
 228         if (TC != 0)
 229           engine_error (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
 230                         (unsigned long) cia.ip);
 231         if (MP)
 232           {
 233             if (Reset || Halt)
 234               engine_halt (SD, CPU, cia, sim_exited, 0);
 235             if (Unhalt)
 236               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
 237                             (unsigned long) cia.ip);
 238             /* if (ICR || DCR); */
 239             if (Task)
 240               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
 241                             (unsigned long) cia.ip);
 242             if (Msg)
 243               engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
 244                             (unsigned long) cia.ip);
 245           }
 246 31./,21.0b0000010,14.UI::::cmnd i
 247         do_cmnd (_SD, UI);
 248 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
 249         do_cmnd (_SD, rSource);
 250 31./,21.0b110000010,12.1,11./::::cmnd l
 251         long_immediate (LongUnsignedImmediate);
 252         do_cmnd (_SD, LongUnsignedImmediate);
 253
 254 // cmp
 255 unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
 256         unsigned32 field = 0;
 257         if (s1 == s2) field |= BIT32 (0);
 258         if (s1 != s2) field |= BIT32 (1);
 259         if (s1 >  s2) field |= BIT32 (2);
 260         if (s1 <= s2) field |= BIT32 (3);
 261         if (s1 <  s2) field |= BIT32 (4);
 262         if (s1 >= s2) field |= BIT32 (5);
 263         if (u1 >  u2) field |= BIT32 (6);
 264         if (u1 <= u2) field |= BIT32 (7);
 265         if (u1 <  u2) field |= BIT32 (8);
 266         if (u1 >= u2) field |= BIT32 (9);
 267         return field;
 268 void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 269         unsigned32 field = 0;
 270         field |= INSERTED32 (cmp_vals (_SD, Source2, Source1, Source2, Source2),
 271                              29, 20);
 272         field |= INSERTED32 (cmp_vals (_SD, (signed16)Source1, (unsigned16)Source1,
 273                                        (signed16)Source2, (unsigned16)Source2),
 274                              19, 10);
 275         field |= INSERTED32 (cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1,
 276                                        (signed8)Source2, (unsigned8)Source2),
 277                              9, 0);
 278         *rDest = field;
 279 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
 280         do_cmp (_SD, rDest, vSource1, rSource2);
 281 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
 282         do_cmp (_SD, rDest, rSource1, rSource2);
 283 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
 284         long_immediate (LongSignedImmediate);
 285         do_cmp (_SD, rDest, LongSignedImmediate, rSource2);
 286
 287
 288 // dcache
 289 31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i
 290         /* NOP */
 291 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r
 292         /* NOP */
 293 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l
 294         long_immediate (LongSignedImmediate);
 295         LongSignedImmediate++;
 296         /* NOP */
 297
 298
 299 // dld[{.b|.h|.d}]
 300 void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 301         do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset);
 302 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
 303         do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
 304 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
 305         long_immediate (LongSignedImmediateOffset);
 306         do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 307
 308
 309 // dld.u[{.b|.h|.d}]
 310 void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 311         do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset);
 312 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
 313         do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
 314 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
 315         long_immediate (LongSignedImmediateOffset);
 316         do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 317
 318
 319 // dst[{.b|.h|.d}]
 320 void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 321         do_st (_SD, Source, Base, rBase, m, sz, S, Offset);
 322 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
 323         do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
 324 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
 325         long_immediate (LongSignedImmediateOffset);
 326         do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 327
 328
 329 // estop
 330 31./,21.0b1111111,14.1,13.0,12.0,11./::::estop
 331
 332
 333 // etrap
 334 31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
 335 31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
 336 31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
 337
 338
 339 // exts - see shift.ds
 340
 341
 342 // extu - see shift.dz
 343
 344
 345 sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
 346         switch (precision)
 347           {
 348           case 0: /* single */
 349             if (reg == 0)
 350               return sim_fpu_32to (0);
 351             else
 352               return sim_fpu_32to (val);
 353           case 1: /* double */
 354             if (reg < 0)
 355               return sim_fpu_32to (val);
 356             if (reg & 1)
 357               engine_error (SD, CPU, cia, "DP FP register must be even");
 358             if (reg <= 1)
 359               engine_error (SD, CPU, cia, "DP FP register must be >= 2");
 360             return sim_fpu_64to (INSERTED64 (GPR(reg + 1), 63, 32)
 361                                  | INSERTED64 (GPR(reg), 31, 0));
 362           case 2: /* 32 bit signed integer */
 363             if (reg == 0)
 364               return sim_fpu_32to (0);
 365             else
 366               return sim_fpu_d2 ((signed32) val);
 367           case 3: /* 32 bit unsigned integer */
 368             if (reg == 0)
 369               return sim_fpu_32to (0);
 370             else
 371               return sim_fpu_d2 ((unsigned32) val);
 372           default:
 373             engine_error (SD, CPU, cia, "Unsupported FP precision");
 374           }
 375         return sim_fpu_32to (0);
 376 void::function::set_fp_reg:int Dest, sim_fpu val, int PD
 377         switch (PD)
 378           {
 379           case 0: /* single */
 380             {
 381               GPR (Dest) = sim_fpu_to32 (val);
 382               break;
 383             }
 384           case 1: /* double */
 385             {
 386               unsigned64 v = *(unsigned64*) &val;
 387               if (Dest & 1)
 388                 engine_error (SD, CPU, cia, "DP FP Dest register must be even");
 389               if (Dest <= 1)
 390                 engine_error (SD, CPU, cia, "DP FP Dest register must be >= 2");
 391               GPR (Dest) = EXTRACTED64 (v, 21, 0);
 392               GPR (Dest + 1) = EXTRACTED64 (v, 63, 32);
 393               break;
 394             }
 395           case 2: /* signed */
 396             /* FIXME - rounding */
 397             GPR (Dest) = sim_fpu_2d (val);
 398             break;
 399           case 3: /* unsigned */
 400             /* FIXME - rounding */
 401             GPR (Dest) = sim_fpu_2d (val);
 402             break;
 403           default:
 404             engine_error (SD, CPU, cia, "Unsupported FP precision");
 405           }
 406
 407 // fadd.{s|d}{s|d}{s|d}
 408 void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
 409         sim_fpu ans = sim_fpu_add (s1, s2);
 410         if (TRACE_FPU_P(CPU))
 411           trace_printf (SD, CPU, "0x%lx: fadd - %f + %f = %f\n",
 412                         (unsigned long) cia.ip,
 413                         sim_fpu_2d (s1), sim_fpu_2d (s2),
 414                         sim_fpu_2d (ans));
 415         set_fp_reg (_SD, Dest, ans, PD);
 416 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::::fadd r
 417         do_fadd (_SD, Dest, PD,
 418                  get_fp_reg (_SD, Source1, rSource1, P1),
 419                  get_fp_reg (_SD, Source2, rSource2, P2));
 420 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::::fadd l
 421         long_immediate (SinglePrecisionFloatingPoint);
 422         do_fadd (_SD, Dest, PD,
 423                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 424                  get_fp_reg (_SD, Source2, rSource2, P2));
 425
 426
 427 // fcmp.{s|d}{s|d}{s|d}
 428 void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
 429         *rDest = 0;
 430         if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
 431           *rDest |= BIT32 (30);
 432         else
 433           {
 434             *rDest |= BIT32 (31);
 435             if (sim_fpu_cmp (s1, s2) == 0) *rDest |= BIT32(20);
 436             if (sim_fpu_cmp (s1, s2) != 0) *rDest |= BIT32(21);
 437             if (sim_fpu_cmp (s1, s2) >  0) *rDest |= BIT32(22);
 438             if (sim_fpu_cmp (s1, s2) <= 0) *rDest |= BIT32(23);
 439             if (sim_fpu_cmp (s1, s2) <  0) *rDest |= BIT32(24);
 440             if (sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(25);
 441             if (sim_fpu_cmp (s1, sim_fpu_32to (0)) < 0
 442                 || sim_fpu_cmp (s1, s2) > 0) *rDest |= BIT32(26);
 443             if (sim_fpu_cmp (sim_fpu_32to (0), s1) < 0
 444                 && sim_fpu_cmp (s1, s2) < 0) *rDest |= BIT32(27);
 445             if (sim_fpu_cmp (sim_fpu_32to (0), s1) <= 0
 446                 && sim_fpu_cmp (s1, s2) <= 0) *rDest |= BIT32(28);
 447             if (sim_fpu_cmp (s1, sim_fpu_32to (0)) <= 0
 448                 || sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(29);
 449           }
 450         if (TRACE_FPU_P (CPU))
 451           trace_printf (SD, CPU, "0x%lx: fcmp - %f >=< %f - 0x%08x\n",
 452                         (unsigned long) cia.ip,
 453                         sim_fpu_2d (s1), sim_fpu_2d (s2),
 454                         (unsigned long) *rDest);
 455 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::::fcmp r
 456         do_fcmp (_SD, rDest,
 457                  get_fp_reg (_SD, Source1, rSource1, P1),
 458                  get_fp_reg (_SD, Source2, rSource2, P2));
 459 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::::fcmp l
 460         long_immediate (SinglePrecisionFloatingPoint);
 461         do_fcmp (_SD, rDest,
 462                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 463                  get_fp_reg (_SD, Source2, rSource2, P2));
 464
 465
 466
 467 // fdiv.{s|d}{s|d}{s|d}
 468 void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
 469         sim_fpu ans = sim_fpu_div (s1, s2);
 470         if (TRACE_FPU_P(CPU))
 471           trace_printf (SD, CPU, "0x%lx: fdiv - %f / %f = %f\n",
 472                         (unsigned long) cia.ip,
 473                         sim_fpu_2d (s1), sim_fpu_2d (s2),
 474                         sim_fpu_2d (ans));
 475         set_fp_reg (_SD, Dest, ans, PD);
 476 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::::fdiv r
 477         do_fdiv (_SD, Dest, PD,
 478                  get_fp_reg (_SD, Source1, rSource1, P1),
 479                  get_fp_reg (_SD, Source2, rSource2, P2));
 480 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::::fdiv l
 481         long_immediate (SinglePrecisionFloatingPoint);
 482         do_fdiv (_SD, Dest, PD,
 483                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 484                  get_fp_reg (_SD, Source2, rSource2, P2));
 485
 486
 487 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 488 void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
 489         sim_fpu ans = sim_fpu_mul (s1, s2);
 490         if (TRACE_FPU_P(CPU))
 491           trace_printf (SD, CPU, "0x%lx: fmpy - %f * %f = %f\n",
 492                         (unsigned long) cia.ip,
 493                         sim_fpu_2d (s1), sim_fpu_2d (s2),
 494                         sim_fpu_2d (ans));
 495         set_fp_reg (_SD, Dest, ans, PD);
 496 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::::fmpy r
 497         do_fmpy (_SD, Dest, PD,
 498                  get_fp_reg (_SD, Source1, rSource1, P1),
 499                  get_fp_reg (_SD, Source2, rSource2, P2));
 500 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::::fmpy l
 501         long_immediate (SinglePrecisionFloatingPoint);
 502         do_fmpy (_SD, Dest, PD,
 503                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 504                  get_fp_reg (_SD, Source2, rSource2, P2));
 505
 506
 507 // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 508 void::function::do_frnd:int Dest, int PD, sim_fpu s1
 509         set_fp_reg (_SD, Dest, s1, PD);
 510 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::::frndm r
 511         do_frnd (_SD, Dest, PD,
 512                  get_fp_reg (_SD, Source, rSource, P1));
 513 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::::frndm l
 514         long_immediate (SinglePrecisionFloatingPoint);
 515         do_frnd (_SD, Dest, PD,
 516                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 517
 518
 519 // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 520 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::::frndn r
 521         do_frnd (_SD, Dest, PD,
 522                  get_fp_reg (_SD, Source, rSource, P1));
 523 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::::frndn l
 524         long_immediate (SinglePrecisionFloatingPoint);
 525         do_frnd (_SD, Dest, PD,
 526                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 527
 528
 529 // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 530 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::::frndp r
 531         do_frnd (_SD, Dest, PD,
 532                  get_fp_reg (_SD, Source, rSource, P1));
 533 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::::frndp l
 534         long_immediate (SinglePrecisionFloatingPoint);
 535         do_frnd (_SD, Dest, PD,
 536                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 537
 538
 539 // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 540 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::::frndz r
 541         do_frnd (_SD, Dest, PD,
 542                  get_fp_reg (_SD, Source, rSource, P1));
 543 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::::frndz l
 544         long_immediate (SinglePrecisionFloatingPoint);
 545         do_frnd (_SD, Dest, PD,
 546                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 547
 548
 549 // fsqrt.{s|d}{s|d}{s|d}
 550 #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 551 #       sim_io_error ("fsqrt");
 552 31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::::fsqrt r
 553 #       do_fsqrt (_SD, rDest, rSource1, rSource2);
 554 31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::::fsqrt l
 555 #       do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2);
 556
 557
 558 // fsub.{s|d}{s|d}{s|d}
 559 void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
 560         sim_fpu ans = sim_fpu_sub (s1, s2);
 561         if (TRACE_FPU_P(CPU))
 562           trace_printf (SD, CPU, "0x%lx: fsub - %f + %f = %f\n",
 563                         (unsigned long) cia.ip,
 564                         sim_fpu_2d (s1), sim_fpu_2d (s2),
 565                         sim_fpu_2d (ans));
 566         set_fp_reg (_SD, Dest, ans, PD);
 567 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::::fsub r
 568         do_fsub (_SD, Dest, PD,
 569                  get_fp_reg (_SD, Source1, rSource1, P1),
 570                  get_fp_reg (_SD, Source2, rSource2, P2));
 571 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::::fsub l
 572         long_immediate (SinglePrecisionFloatingPoint);
 573         do_fsub (_SD, Dest, PD,
 574                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 575                  get_fp_reg (_SD, Source2, rSource2, P2));
 576
 577
 578 // illop
 579 31./,21.0b0000000,14./::::illop
 580 31./,21.0b111111111,12./::::illop l
 581
 582
 583 // ins - see sl.im
 584
 585
 586 // jsr[.a]
 587 instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
 588         if (annul)
 589           {
 590             *rLink = nia.ip;
 591             nia.ip = -1;
 592           }
 593         else
 594           *rLink = cia.dp + sizeof (instruction_word);
 595         nia.dp = offset + base;
 596         if (nia.dp & 0x3)
 597           engine_error (SD, CPU, cia,
 598                         "0x%lx: destination address 0x%lx misaligned",
 599                         (unsigned long) cia.ip,
 600                         (unsigned long) nia.dp);
 601         return nia;
 602 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
 603         nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase);
 604 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
 605         nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase);
 606 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
 607         long_immediate (LongSignedImmediate);
 608         nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase);
 609
 610
 611 // ld[{.b.h.d}]
 612 void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 613         unsigned32 addr;
 614         switch (sz)
 615           {
 616           case 0:
 617             addr = Base + (S ? (Offset << 0) : Offset);
 618             if (m)
 619               *rBase = addr;
 620             GPR(Dest) = MEM (signed, addr, 1);
 621             break;
 622           case 1:
 623             addr = Base + (S ? (Offset << 1) : Offset);
 624             if (m)
 625               *rBase = addr;
 626             GPR(Dest) = MEM (signed, addr, 2);
 627             break;
 628           case 2:
 629             addr = Base + (S ? (Offset << 2) : Offset);
 630             if (m)
 631               *rBase = addr;
 632             GPR(Dest) = MEM (signed, addr, 4);
 633             break;
 634           case 3:
 635             if (Dest & 0x1)
 636               engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
 637                             cia.ip, Dest);
 638             addr = Base + (S ? (Offset << 3) : Offset);
 639             if (m)
 640               *rBase = addr;
 641             *(unsigned64*)(&GPR(Dest)) = MEM (signed, addr, 8);
 642             break;
 643           default:
 644             addr = -1;
 645             engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
 646           }
 647 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
 648         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 649 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
 650         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
 651 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
 652         long_immediate (LongSignedImmediateOffset);
 653         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 654
 655
 656 // ld.u[{.b.h.d}]
 657 void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 658         unsigned32 addr;
 659         switch (sz)
 660           {
 661           case 0:
 662             addr = Base + (S ? (Offset << 0) : Offset);
 663             *rDest = MEM (unsigned, addr, 1);
 664             break;
 665           case 1:
 666             addr = Base + (S ? (Offset << 1) : Offset);
 667             *rDest = MEM (unsigned, addr, 2);
 668             break;
 669           default:
 670             addr = -1;
 671             engine_error (SD, CPU, cia, "ld.u - invalid sz %d", sz);
 672           }
 673         if (m)
 674           *rBase = addr;
 675 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
 676         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 677 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
 678         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
 679 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
 680         long_immediate (LongSignedImmediateOffset);
 681         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 682
 683
 684 // lmo
 685 31.Dest,26.Source,21.111111000,12.0,11./::::lmo
 686
 687
 688 // nop - see rdcr 0, r0
 689
 690
 691 void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 692         *rDest = Source1 | Source2;
 693
 694
 695 // or, or.tt
 696 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
 697         do_or (_SD, rDest, vSource1, rSource2);
 698 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
 699         do_or (_SD, rDest, rSource1, rSource2);
 700 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
 701         long_immediate (LongUnsignedImmediate);
 702         do_or (_SD, rDest, LongUnsignedImmediate, rSource2);
 703
 704
 705 // or.ff
 706 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
 707         do_or (_SD, rDest, ~vSource1, ~rSource2);
 708 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
 709         do_or (_SD, rDest, ~rSource1, ~rSource2);
 710 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
 711         long_immediate (LongUnsignedImmediate);
 712         do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2);
 713
 714
 715 // or.ft
 716 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
 717         do_or (_SD, rDest, ~vSource1, rSource2);
 718 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
 719         do_or (_SD, rDest, ~rSource1, rSource2);
 720 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
 721         long_immediate (LongUnsignedImmediate);
 722         do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2);
 723
 724
 725 // or.tf
 726 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
 727         do_or (_SD, rDest, vSource1, ~rSource2);
 728 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
 729         do_or (_SD, rDest, rSource1, ~rSource2);
 730 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
 731         long_immediate (LongUnsignedImmediate);
 732         do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2);
 733
 734
 735 // rdcr
 736 void::function::do_rdcr:unsigned32 Dest, int cr
 737         if (Dest != 0)
 738           engine_error (SD, CPU, cia, "rdcr unimplement");
 739 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
 740         do_rdcr (_SD, Dest, UCRN);
 741 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
 742         do_rdcr (_SD, Dest, UCRN);
 743 31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
 744         long_immediate (UnsignedControlRegisterNumber);
 745         do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
 746
 747
 748 // rmo
 749 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
 750
 751
 752 // rotl - see sl.dz
 753
 754
 755 //rotr - see sl.dz
 756
 757
 758 // shl - see sl.iz
 759
 760
 761 // sl.{d|e|i}{m|s|z}
 762 void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
 763         /* see 10-30 for a reasonable description */
 764         unsigned32 rotated;
 765         unsigned32 endmask;
 766         unsigned32 shiftmask;
 767         unsigned32 cm;
 768         int nRotate;
 769         /* rotate the source */
 770         if (n)
 771           {
 772             rotated = ROTR32 (GPR (Source), Rotate);
 773             nRotate = (- Rotate) & 31;
 774           }
 775         else
 776           {
 777             rotated = ROTL32 (GPR (Source), Rotate);
 778             nRotate = Rotate;
 779           }
 780         /* form the end mask */
 781         if (EndMask == 0)
 782           endmask = -1;
 783         else
 784           endmask = (1 << EndMask) - 1;
 785         if (i)
 786           endmask = ~endmask;
 787         /* form the shiftmask */
 788         switch (Merge)
 789           {
 790           case 0: case 1: case 2:
 791             shiftmask = -1; /* disabled */
 792             break;
 793           case 3: case 4: case 5:
 794             shiftmask = ((1 << nRotate) - 1); /* enabled */
 795             break;
 796           case 6: case 7:
 797             shiftmask = ~((1 << nRotate) - 1); /* inverted */
 798             break;
 799           default:
 800             engine_error (SD, CPU, cia,
 801                           "0x%lx: Invalid merge (%d) for shift",
 802                           cia.ip, Source);
 803             shiftmask = 0;
 804           }
 805         /* and the composite mask */
 806         cm = shiftmask & endmask;
 807         /* and merge */
 808         switch (Merge)
 809           {
 810           case 0: case 3: case 6: /* zero */
 811             GPR (Dest) = rotated & cm;
 812             break;
 813           case 1: case 4: case 7: /* merge */
 814             GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
 815             break;
 816           case 2: case 5: /* sign */
 817             {
 818               int b;
 819               GPR (Dest) = rotated & cm;
 820               for (b = 1; b <= 31; b++)
 821                 if (!MASKED32 (cm, b, b))
 822                   GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
 823                                             b, b);
 824             }
 825             break;
 826           default:
 827             engine_error (SD, CPU, cia,
 828                           "0x%lx: Invalid merge (%d)",
 829                           cia.ip, Source);
 830
 831           }
 832 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
 833         do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate);
 834 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
 835         int endmask;
 836         if (EndMask == 0)
 837           endmask = EndMask;
 838         else
 839           {
 840             if (Source & 1)
 841               engine_error (SD, CPU, cia,
 842                             "0x%lx: Invalid source (%d) for shift",
 843                             cia.ip, Source);
 844             endmask = GPR (Source + 1) & 31;
 845           }
 846         do_shift (_SD, Dest, Source, Merge, i, n, endmask, GPR (RotReg) & 31);
 847
 848
 849 // sli.{d|e|i}{m|s|z}
 850 #31.Dest,26.Source,21.0b0001,17.Merge,14./,11.1,10.0,9.EndMask,4.Rotate::::sli i
 851 #31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.1,10.0,9.EndMask,4.RotReg::::sli r
 852
 853
 854 // sr.{d|e|i}{m|s|z}
 855 #31.Dest,26.Source,21.0b0001,17.Merge,14./,11.0,10.1,9.EndMask,4.Rotate::::sr i
 856 #31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.0,10.1,9.EndMask,4.RotReg::::sr r
 857
 858
 859 // sra - see sr.es
 860
 861
 862 // sri.{d|e|i}{m|s|z}
 863 #31.Dest,26.Source,21.0b0001,17.Merge,14./,11.1,10.1,9.EndMask,4.Rotate::::sri i
 864 #31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.1,10.1,9.EndMask,4.RotReg::::sri r
 865
 866
 867 // srl - see sr.ez
 868
 869
 870 // st[{.b|.h|.d}]
 871 void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 872         unsigned32 addr;
 873         switch (sz)
 874           {
 875           case 0:
 876             addr = Base + (S ? (Offset << 0) : Offset);
 877             STORE (addr, 1, GPR(Source));
 878             break;
 879           case 1:
 880             addr = Base + (S ? (Offset << 1) : Offset);
 881             STORE (addr, 2, GPR(Source));
 882             break;
 883           case 2:
 884             addr = Base + (S ? (Offset << 2) : Offset);
 885             STORE (addr, 4, GPR(Source));
 886             break;
 887           case 3:
 888             if (Source & 0x1)
 889               engine_error (SD, CPU, cia, "0x%lx: st.d with odd source register %d",
 890                             cia.ip, Source);
 891             addr = Base + (S ? (Offset << 3) : Offset);
 892             STORE (addr, 8, *(unsigned64*)&GPR(Source));
 893             break;
 894           default:
 895             addr = -1;
 896             engine_error (SD, CPU, cia, "st - invalid sz %d", sz);
 897           }
 898         if (m)
 899           *rBase = addr;
 900 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
 901         do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 902 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
 903         do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
 904 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
 905         long_immediate (LongSignedImmediateOffset);
 906         do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 907
 908
 909 // sub
 910 void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
 911         ALU_BEGIN (Source1);
 912         ALU_SUB (Source2);
 913         ALU_END (*rDest);
 914 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
 915         do_sub (_SD, rDest, vSource1, rSource2);
 916 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
 917         do_sub (_SD, rDest, rSource1, rSource2);
 918 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
 919         long_immediate (LongSignedImmediate);
 920         do_sub (_SD, rDest, LongSignedImmediate, rSource2);
 921
 922
 923 // subu
 924 void::function::do_subu:signed32 *rDest, signed32 Source1, signed32 Source2
 925         *rDest = Source1 - Source2;
 926 // NOTE - the book has 15.1 which conflicts with subu.
 927 31.Dest,26.Source2,21.0b101101,15.1,14.SignedImmediate::::subu i
 928         do_subu (_SD, rDest, vSource1, rSource2);
 929 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
 930         do_subu (_SD, rDest, rSource1, rSource2);
 931 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
 932         long_immediate (LongSignedImmediate);
 933         do_subu (_SD, rDest, LongSignedImmediate, rSource2);
 934
 935
 936 // swcr
 937 #void::function::do_swcr:signed32 *rDest, signed32 Source1, signed32 Source2
 938 31.Dest,26.Source,21.0b000010,15.1,14.SignedImmediate::::swcr i
 939 #       do_swcr (_SD, rDest, SI, rSource2);
 940 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
 941 #       do_swcr (_SD, rDest, rSource1, rSource2);
 942 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
 943 #       do_swcr (_SD, rDest, LongSignedImmediate, rSource2);
 944
 945
 946 // trap
 947 void::function::do_trap:unsigned32 trap_number
 948         switch (trap_number)
 949           {
 950           case 72:
 951             switch (GPR(15))
 952               {
 953               case 1: /* EXIT */
 954                 {
 955                   engine_halt (SD, CPU, cia, sim_exited, GPR(2));
 956                   break;
 957                 }
 958               case 4: /* WRITE */
 959                 {
 960                   int i;
 961                   if (GPR(2) == 1)
 962                     for (i = 0; i < GPR(6); i++)
 963                       {
 964                         char c;
 965                         c = MEM (unsigned, GPR(4) + i, 1);
 966                         sim_io_write_stdout (SD, &c, 1);
 967                       }
 968                   else if (GPR(2) == 2)
 969                     for (i = 0; i < GPR(6); i++)
 970                       {
 971                         char c;
 972                         c = MEM (unsigned, GPR(4) + i, 1);
 973                         sim_io_write_stderr (SD, &c, 1);
 974                       }
 975                   else
 976                     engine_error (SD, CPU, cia,
 977                                   "0x%lx: write to invalid fid %d",
 978                                   (unsigned long) cia.ip, GPR(2));
 979                   GPR(2) = GPR(6);
 980                   break;
 981                 }
 982               default:
 983                 engine_error (SD, CPU, cia,
 984                               "0x%lx: unknown syscall %d",
 985                               (unsigned long) cia.ip, GPR(15));
 986               }
 987             break;
 988           case 73:
 989             engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP);
 990           default:
 991             engine_error (SD, CPU, cia,
 992                           "0x%lx: unsupported trap %d",
 993                           (unsigned long) cia.ip, trap_number);
 994           }
 995 31./,27.0,26./,21.0b0000001,14.UTN::::trap i
 996         do_trap (_SD, UTN);
 997 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
 998         do_trap (_SD, UTN);
 999 31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
1000         long_immediate (UTN);
1001         do_trap (_SD, UTN);
1002
1003
1004 // vadd.{s|d}{s|d}
1005 31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::::vadd r
1006 31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::::vadd l
1007
1008
1009 // vld{0|1}.{s|d} - see above - same instruction
1010 #31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::::vld
1011
1012
1013 // vmac.ss{s|d}
1014 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::::vmac.ss ra
1015 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::::vmac.ss rr
1016 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::::vmac.ss ia
1017 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::::vmac.ss ir
1018
1019
1020 // vmpy.{s|d}{s|d}
1021 31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::::vmpy r
1022 31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::::vmpy l
1023
1024
1025 // vmsc.ss{s|d}
1026 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::::vmsc.ss ra
1027 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::::vmsc.ss rr
1028 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::::vmsc.ss ia
1029 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::::vmsc.ss ir
1030
1031
1032 // vmsub.{s|d}{s|d}
1033 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::::vmsub r
1034 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::::vmsub l
1035
1036
1037 // vrnd.{s|d}{s|d}
1038 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::::vrnd f r
1039 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::::vrnd f l
1040
1041
1042 // vrnd.{i|u}{s|d}
1043 31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::::vrnd i r
1044 31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::::vrnd i l
1045
1046
1047 // vst.{s|d} - see above - same instruction
1048 #31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::::vst
1049
1050
1051 // vsub.{i|u}{s|d}
1052 31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::::vsub r
1053 31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::::vsub l
1054
1055
1056 // wrcr - see swcr, creg, source, r0
1057
1058
1059 // xnor
1060 void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2
1061         *rDest = ~ (Source1 ^ Source2);
1062 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
1063         do_xnor (_SD, rDest, vSource1, rSource2);
1064 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
1065         do_xnor (_SD, rDest, rSource1, rSource2);
1066 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
1067         long_immediate (LongUnsignedImmediate);
1068         do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2);
1069
1070
1071 // xor
1072 void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2
1073         *rDest = Source1 ^ Source2;
1074 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
1075         do_xor (_SD, rDest, vSource1, rSource2);
1076 31.Dest,26.Source2,21.0b110010110,13.0,12.0,11./,4.Source1::::xor r
1077         do_xor (_SD, rDest, rSource1, rSource2);
1078 31.Dest,26.Source2,21.0b110010110,13.0,12.1,11./::::xor l
1079         long_immediate (LongUnsignedImmediate);
1080         do_xor (_SD, rDest, LongUnsignedImmediate, rSource2);