sim/tic80/insns

   1 // Texas Instruments TMS320C80 (MVP) Simulator.
   2 // Copyright (C) 1997 Free Software Foundation, Inc.
   3 // Contributed by Cygnus Support.
   4 //
   5 // This file is part of GDB, the GNU debugger.
   6 //
   7 // This program is free software; you can redistribute it and/or modify
   8 // it under the terms of the GNU General Public License as published by
   9 // the Free Software Foundation; either version 2, or (at your option)
  10 // any later version.
  11 //
  12 // This program is distributed in the hope that it will be useful,
  13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 // GNU General Public License for more details.
  16 //
  17 // You should have received a copy of the GNU General Public License along
  18 // with this program; if not, write to the Free Software Foundation, Inc.,
  19 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21
  22 // The following is called when ever an illegal instruction is encountered.
  23 ::internal::illegal
  24         sim_io_eprintf (SD, "0x%lx: illegal instruction\n", (unsigned long) cia.ip);
  25         sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  26
  27 // The following is called when ever an FP op is attempted with FPU disabled.
  28 ::internal::fp_unavailable
  29         sim_io_eprintf (SD, "0x%lx: floating-point unavailable\n", (unsigned long) cia.ip);
  30         sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGFPE);
  31
  32 // Handle a branch instruction
  33 instruction_address::function::do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink
  34         instruction_address nia;
  35         if (annul)
  36           {
  37             if (rLink_p)
  38               *rLink = cia.dp;
  39             nia.ip = target;
  40             nia.dp = target + 4;
  41           }
  42         else
  43           {
  44             if (rLink_p)
  45               *rLink = cia.dp + sizeof (instruction_word);
  46             nia.ip = cia.dp;
  47             nia.dp = target;
  48           }
  49         return nia;
  50
  51 // Signed Integer Add - add source1, source2, dest
  52 void::function::do_add:unsigned32 *rDest, signed32 source1, signed32 source2
  53         unsigned32 result;
  54         ALU_BEGIN (source1);
  55         ALU_ADD (source2);
  56         ALU_END (result);
  57         *rDest = result;
  58         TRACE_ALU3 (MY_INDEX, result, source1, source2);
  59         /* FIXME - a signed add may cause an exception */
  60 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
  61         do_add (_SD, rDest, vSource1, vSource2);
  62 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
  63         do_add (_SD, rDest, vSource1, vSource2);
  64 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
  65         long_immediate (LongSignedImmediate);
  66         do_add (_SD, rDest, LongSignedImmediate, vSource2);
  67
  68
  69 // Unsigned Integer Add - addu source1, source2, dest
  70 void::function::do_addu:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
  71         unsigned32 result = source1 + source2;
  72         TRACE_ALU3 (MY_INDEX, result, source1, source2);
  73         *rDest = result;
  74
  75 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
  76         do_addu (_SD, rDest, vSource1, vSource2);
  77 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
  78         do_addu (_SD, rDest, vSource1, vSource2);
  79 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
  80         long_immediate (LongSignedImmediate);
  81         do_addu (_SD, rDest, LongSignedImmediate, vSource2);
  82
  83
  84 void::function::do_and:signed32 *rDest, signed32 source1, signed32 source2
  85         unsigned32 result = source1 & source2;
  86         TRACE_ALU3 (MY_INDEX, result, source1, source2);
  87         *rDest = result;
  88
  89
  90 // and, and.tt
  91 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
  92         do_and (_SD, rDest, vSource1, vSource2);
  93 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
  94         do_and (_SD, rDest, vSource1, vSource2);
  95 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
  96         long_immediate (LongSignedImmediate);
  97         do_and (_SD, rDest, LongSignedImmediate, vSource2);
  98
  99
 100 // and.ff
 101 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
 102         do_and (_SD, rDest, ~vSource1, ~vSource2);
 103 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
 104         do_and (_SD, rDest, ~vSource1, ~vSource2);
 105 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
 106         long_immediate (LongSignedImmediate);
 107         do_and (_SD, rDest, ~LongSignedImmediate, ~vSource2);
 108
 109
 110 // and.ft
 111 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
 112         do_and (_SD, rDest, ~vSource1, vSource2);
 113 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
 114         do_and (_SD, rDest, ~vSource1, vSource2);
 115 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
 116         long_immediate (LongSignedImmediate);
 117         do_and (_SD, rDest, ~LongSignedImmediate, vSource2);
 118
 119
 120 // and.tf
 121 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
 122         do_and (_SD, rDest, vSource1, ~vSource2);
 123 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
 124         do_and (_SD, rDest, vSource1, ~vSource2);
 125 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
 126         long_immediate (LongSignedImmediate);
 127         do_and (_SD, rDest, LongSignedImmediate, ~vSource2);
 128
 129
 130 // bbo.[a]
 131 instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 132         int jump_p;
 133         address_word target = cia.ip + 4 * offset;
 134         bitnum = (~ bitnum) & 0x1f;
 135         if (MASKED32 (source, bitnum, bitnum))
 136           {
 137             nia = do_branch (_SD, annul, target, 0, NULL);
 138             jump_p = 1;
 139           }
 140         else
 141           jump_p = 0;
 142         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 143         return nia;
 144 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
 145         nia = do_bbo (_SD, nia, BITNUM, vSource, A, vSignedOffset);
 146 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
 147         nia = do_bbo (_SD, nia, BITNUM, vSource, A, rIndOff);
 148 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
 149         long_immediate (LongSignedImmediate);
 150         nia = do_bbo (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
 151
 152
 153 // bbz[.a]
 154 instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 155         int jump_p;
 156         address_word target = cia.ip + 4 * offset;
 157         bitnum = (~ bitnum) & 0x1f;
 158         if (!MASKED32 (source, bitnum, bitnum))
 159           {
 160             nia = do_branch (_SD, annul, target, 0, NULL);
 161             jump_p = 1;
 162           }
 163         else
 164           jump_p = 0;
 165         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 166         return nia;
 167 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
 168         nia = do_bbz (_SD, nia, BITNUM, vSource, A, vSignedOffset);
 169 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
 170         nia = do_bbz (_SD, nia, BITNUM, vSource, A, rIndOff);
 171 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
 172         long_immediate (LongSignedImmediate);
 173         nia = do_bbz (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
 174
 175
 176 // bcnd[.a]
 177 instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
 178         int condition;
 179         int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
 180         int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
 181         signed32 val = 0;
 182         address_word target = cia.ip + 4 * offset;
 183         switch (size)
 184           {
 185           case 0: val = SEXT32 (source, 7); break;
 186           case 1: val = SEXT32 (source, 15); break;
 187           case 2: val = source; break;
 188           default: sim_engine_abort (SD, CPU, cia, "bcnd - reserved size");
 189           }
 190         switch (code)
 191           {
 192           case 0: condition = 0; break;
 193           case 1: condition = val > 0; break;
 194           case 2: condition = val == 0; break;
 195           case 3: condition = val >= 0; break;
 196           case 4: condition = val < 0; break;
 197           case 5: condition = val != 0; break;
 198           case 6: condition = val <= 0; break;
 199           default: condition = 1; break;
 200           }
 201         if (condition)
 202           {
 203             nia = do_branch (_SD, annul, target, 0, NULL);
 204           }
 205         TRACE_COND_BR(MY_INDEX, condition, source, target);
 206         return nia;
 207 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
 208         nia = do_bcnd (_SD, nia, Code, vSource, A, vSignedOffset);
 209 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
 210         nia = do_bcnd (_SD, nia, Code, vSource, A, rIndOff);
 211 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
 212         long_immediate (LongSignedImmediate);
 213         nia = do_bcnd (_SD, nia, Code, vSource, A, LongSignedImmediate);
 214
 215
 216 // br[.a] - see bbz[.a]
 217
 218
 219 // brcr
 220 sim_cia::function::do_brcr:instruction_address nia, int cr
 221         if (cr >= 0x4000 || !(CPU)->is_user_mode)
 222           {
 223             unsigned32 control = CR (cr);
 224             unsigned32 ie = control & 0x00000001;
 225             unsigned32 pc = control & 0xfffffffc;
 226             unsigned32 is_user_mode = control & 0x00000002;
 227             (CPU)->is_user_mode = is_user_mode;
 228             nia.dp = pc;
 229             if (ie)
 230               (CPU)->cr[IE_CR] |= IE_CR_IE;
 231             else
 232               (CPU)->cr[IE_CR] &= ~IE_CR_IE;
 233           }
 234         TRACE_UCOND_BR (MY_INDEX, nia.dp);
 235         return nia;
 236 31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i
 237         nia = do_brcr (_SD, nia, UCRN);
 238 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r
 239         nia = do_brcr (_SD, nia, UCRN);
 240 31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l
 241         long_immediate (UnsignedControlRegisterNumber)
 242         nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber);
 243
 244
 245 // bsr[.a]
 246 instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
 247         address_word target = cia.ip + 4 * offset;
 248         nia = do_branch (_SD, annul, target, 1, rLink);
 249         TRACE_UCOND_BR (MY_INDEX, target);
 250         return nia;
 251 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
 252         nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
 253 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
 254         nia = do_bsr (_SD, nia, rLink, A, rIndOff);
 255 31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
 256         long_immediate (LongSignedImmediate);
 257         nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
 258
 259
 260 // cmnd
 261 void::function::do_cmnd:signed32 source
 262         int Reset = EXTRACTED32 (source, 31, 31);
 263         int Halt = EXTRACTED32 (source, 30, 30);
 264         int Unhalt = EXTRACTED32 (source, 29, 29);
 265         /* int ICR = EXTRACTED32 (source, 28, 28); */
 266         /* int DCR = EXTRACTED32 (source, 27, 27); */
 267         int Task = EXTRACTED32 (source, 14, 14);
 268         int Msg = EXTRACTED32 (source, 13, 13);
 269         int VC = EXTRACTED32 (source, 10, 10);
 270         int TC = EXTRACTED32 (source, 9, 9);
 271         int MP = EXTRACTED32 (source, 8, 8);
 272         int PP = EXTRACTED32 (source, 3, 0);
 273         /* what is implemented? */
 274         if (PP != 0)
 275           sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
 276                             (unsigned long) cia.ip);
 277         if (VC != 0)
 278           sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
 279                             (unsigned long) cia.ip);
 280         if (TC != 0)
 281           sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
 282                             (unsigned long) cia.ip);
 283         if (MP)
 284           {
 285             if (Reset || Halt)
 286               sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
 287             if (Unhalt)
 288               sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
 289                                 (unsigned long) cia.ip);
 290             /* if (ICR || DCR); */
 291             if (Task)
 292               sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
 293                                 (unsigned long) cia.ip);
 294             if (Msg)
 295               sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
 296                                 (unsigned long) cia.ip);
 297           }
 298         TRACE_SINK1 (MY_INDEX, source);
 299 31./,21.0b0000010,14.UI::::cmnd i
 300         do_cmnd (_SD, UI);
 301 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
 302         do_cmnd (_SD, vSource);
 303 31./,21.0b110000010,12.1,11./::::cmnd l
 304         long_immediate (LongUnsignedImmediate);
 305         do_cmnd (_SD, LongUnsignedImmediate);
 306
 307 // cmp
 308 unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
 309         unsigned32 field = 0;
 310         if (s1 == s2) field |= 0x001;
 311         if (s1 != s2) field |= 0x002;
 312         if (s1 >  s2) field |= 0x004;
 313         if (s1 <= s2) field |= 0x008;
 314         if (s1 <  s2) field |= 0x010;
 315         if (s1 >= s2) field |= 0x020;
 316         if (u1 >  u2) field |= 0x040;
 317         if (u1 <= u2) field |= 0x080;
 318         if (u1 <  u2) field |= 0x100;
 319         if (u1 >= u2) field |= 0x200;
 320         return field;
 321 void::function::do_cmp:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
 322         unsigned32 field = 0;
 323         field |= cmp_vals (_SD, source1, source1, source2, source2) << 20;
 324         field |= cmp_vals (_SD, (signed16)source1, (unsigned16)source1,
 325                            (signed16)source2, (unsigned16)source2) << 10;
 326         field |= cmp_vals (_SD, (signed8)source1, (unsigned8)source1,
 327                             (signed8)source2, (unsigned8)source2);
 328         TRACE_ALU3 (MY_INDEX, field, source1, source2);
 329         *rDest = field;
 330 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
 331         do_cmp (_SD, rDest, vSource1, vSource2);
 332 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
 333         do_cmp (_SD, rDest, vSource1, vSource2);
 334 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
 335         long_immediate (LongSignedImmediate);
 336         do_cmp (_SD, rDest, LongSignedImmediate, vSource2);
 337
 338
 339 // dcache
 340 31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i
 341         TRACE_NOP (MY_INDEX);
 342         /* NOP */
 343 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r
 344         TRACE_NOP (MY_INDEX);
 345         /* NOP */
 346 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l
 347         long_immediate (LongSignedImmediate);
 348         LongSignedImmediate++;
 349         TRACE_NOP (MY_INDEX);
 350         /* NOP */
 351
 352
 353 // dld[{.b|.h|.d}]
 354 void::function::do_dld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 355         do_ld (_SD, Dest, base, rBase, m, sz, S, offset);
 356 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
 357         do_dld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
 358 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
 359         long_immediate (LongSignedImmediateOffset);
 360         do_dld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 361
 362
 363 // dld.u[{.b|.h|.d}]
 364 void::function::do_dld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 365         do_ld_u (_SD, rDest, base, rBase, m, sz, S, offset);
 366 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
 367         do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
 368 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
 369         long_immediate (LongSignedImmediateOffset);
 370         do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 371
 372
 373 // dst[{.b|.h|.d}]
 374 void::function::do_dst:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 375         do_st (_SD, Source, base, rBase, m, sz, S, offset);
 376 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
 377         do_dst (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
 378 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
 379         long_immediate (LongSignedImmediateOffset);
 380         do_dst (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 381
 382
 383 // estop
 384 31./,21.0b1111111,14.1,13.0,12.0,11./::::estop
 385
 386 // etrap
 387 31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
 388 31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
 389 31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
 390
 391
 392 // exts - see shift.ds
 393
 394
 395 // extu - see shift.dz
 396
 397
 398 sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
 399         switch (precision)
 400           {
 401           case 0: /* single */
 402             return sim_fpu_32to (val);
 403           case 1: /* double */
 404             if (reg < 0)
 405               sim_engine_abort (SD, CPU, cia, "DP immediate invalid");
 406             if (reg & 1)
 407               sim_engine_abort (SD, CPU, cia, "DP FP register must be even");
 408             if (reg <= 1)
 409               sim_engine_abort (SD, CPU, cia, "DP FP register must be >= 2");
 410             return sim_fpu_64to (INSERTED64 (GPR (reg + 1), 63, 32)
 411                                  | INSERTED64 (GPR (reg), 31, 0));
 412           case 2: /* 32 bit signed integer */
 413             return sim_fpu_i32to (val);
 414           case 3: /* 32 bit unsigned integer */
 415             return sim_fpu_u32to (val);
 416           default:
 417             sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
 418           }
 419         return sim_fpu_i32to (0);
 420 void::function::set_fp_reg:int Dest, sim_fpu val, int PD
 421         switch (PD)
 422           {
 423           case 0: /* single */
 424             {
 425               GPR (Dest) = sim_fpu_to32 (val);
 426               break;
 427             }
 428           case 1: /* double */
 429             {
 430               unsigned64 v = sim_fpu_to64 (val);
 431               if (Dest & 1)
 432                 sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be even");
 433               if (Dest <= 1)
 434                 sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be >= 2");
 435               GPR (Dest + 0) = VL4_8 (v);
 436               GPR (Dest + 1) = VH4_8 (v);
 437               break;
 438             }
 439           case 2: /* signed */
 440             {
 441               GPR (Dest) = sim_fpu_to32i (val);
 442               break;
 443             }
 444           case 3: /* unsigned */
 445             {
 446               GPR (Dest) = sim_fpu_to32u (val);
 447               break;
 448             }
 449           default:
 450             sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
 451           }
 452
 453 // fadd.{s|d}{s|d}{s|d}
 454 void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
 455         sim_fpu ans = sim_fpu_add (s1, s2);
 456         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 457         set_fp_reg (_SD, Dest, ans, PD);
 458 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
 459         do_fadd (_SD, Dest, PD,
 460                  get_fp_reg (_SD, Source1, vSource1, P1),
 461                  get_fp_reg (_SD, Source2, vSource2, P2));
 462 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
 463         long_immediate (SinglePrecisionFloatingPoint);
 464         do_fadd (_SD, Dest, PD,
 465                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 466                  get_fp_reg (_SD, Source2, vSource2, P2));
 467
 468
 469 // fcmp.{s|d}{s|d}{s|d}
 470 void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
 471         unsigned32 result = 0;
 472         if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
 473           result |= BIT32 (30);
 474         else
 475           {
 476             result |= BIT32 (31);
 477             if (sim_fpu_is_eq (s1, s2)) result |= BIT32(20);
 478             if (sim_fpu_is_ne (s1, s2)) result |= BIT32(21);
 479             if (sim_fpu_is_gt (s1, s2)) result |= BIT32(22);
 480             if (sim_fpu_is_le (s1, s2)) result |= BIT32(23);
 481             if (sim_fpu_is_lt (s1, s2)) result |= BIT32(24);
 482             if (sim_fpu_is_ge (s1, s2)) result |= BIT32(25);
 483             if (sim_fpu_is_lt (s1, sim_fpu_i32to (0))
 484                 || sim_fpu_is_gt (s1, s2)) result |= BIT32(26);
 485             if (sim_fpu_is_lt (sim_fpu_i32to (0), s1)
 486                 && sim_fpu_is_lt (s1, s2)) result |= BIT32(27);
 487             if (sim_fpu_is_le (sim_fpu_i32to (0), s1)
 488                 && sim_fpu_is_le (s1, s2)) result |= BIT32(28);
 489             if (sim_fpu_is_le (s1, sim_fpu_i32to (0))
 490                 || sim_fpu_is_ge (s1, s2)) result |= BIT32(29);
 491           }
 492         *rDest = result;
 493         TRACE_FPU2I (MY_INDEX, result, s1, s2);
 494 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
 495         do_fcmp (_SD, rDest,
 496                  get_fp_reg (_SD, Source1, vSource1, P1),
 497                  get_fp_reg (_SD, Source2, vSource2, P2));
 498 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
 499         long_immediate (SinglePrecisionFloatingPoint);
 500         do_fcmp (_SD, rDest,
 501                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 502                  get_fp_reg (_SD, Source2, vSource2, P2));
 503
 504
 505
 506 // fdiv.{s|d}{s|d}{s|d}
 507 void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
 508         sim_fpu ans = sim_fpu_div (s1, s2);
 509         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 510         set_fp_reg (_SD, Dest, ans, PD);
 511 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
 512         do_fdiv (_SD, Dest, PD,
 513                  get_fp_reg (_SD, Source1, vSource1, P1),
 514                  get_fp_reg (_SD, Source2, vSource2, P2));
 515 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
 516         long_immediate (SinglePrecisionFloatingPoint);
 517         do_fdiv (_SD, Dest, PD,
 518                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 519                  get_fp_reg (_SD, Source2, vSource2, P2));
 520
 521
 522 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 523 void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
 524         switch (PD)
 525           {
 526           case 2: /* signed */
 527             {
 528               GPR (Dest) = sim_fpu_to64i (s1) * sim_fpu_to64i (s2);
 529               TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
 530               break;
 531             }
 532           case 3: /* unsigned */
 533             {
 534               GPR (Dest) = sim_fpu_to64u (s1) * sim_fpu_to64u (s2);
 535               TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
 536               break;
 537             }
 538           default:
 539             {
 540               sim_fpu ans = sim_fpu_mul (s1, s2);
 541               set_fp_reg (_SD, Dest, ans, PD);
 542               TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 543             }
 544           }
 545 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
 546         do_fmpy (_SD, Dest, PD,
 547                  get_fp_reg (_SD, Source1, vSource1, P1),
 548                  get_fp_reg (_SD, Source2, vSource2, P2));
 549 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
 550         long_immediate (SinglePrecisionFloatingPoint);
 551         do_fmpy (_SD, Dest, PD,
 552                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 553                  get_fp_reg (_SD, Source2, vSource2, P2));
 554
 555
 556 // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 557 void::function::do_frnd:int Dest, int PD, sim_fpu s1
 558         set_fp_reg (_SD, Dest, s1, PD);
 559         TRACE_FPU1 (MY_INDEX, s1);
 560 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
 561         do_frnd (_SD, Dest, PD,
 562                  get_fp_reg (_SD, Source, vSource, P1));
 563 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
 564         long_immediate (SinglePrecisionFloatingPoint);
 565         do_frnd (_SD, Dest, PD,
 566                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 567
 568
 569 // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 570 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
 571         do_frnd (_SD, Dest, PD,
 572                  get_fp_reg (_SD, Source, vSource, P1));
 573 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
 574         long_immediate (SinglePrecisionFloatingPoint);
 575         do_frnd (_SD, Dest, PD,
 576                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 577
 578
 579 // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 580 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
 581         do_frnd (_SD, Dest, PD,
 582                  get_fp_reg (_SD, Source, vSource, P1));
 583 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
 584         long_immediate (SinglePrecisionFloatingPoint);
 585         do_frnd (_SD, Dest, PD,
 586                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 587
 588
 589 // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 590 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
 591         do_frnd (_SD, Dest, PD,
 592                  get_fp_reg (_SD, Source, vSource, P1));
 593 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
 594         long_immediate (SinglePrecisionFloatingPoint);
 595         do_frnd (_SD, Dest, PD,
 596                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 597
 598
 599 // fsqrt.{s|d}{s|d}{s|d}
 600 #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 601 #       sim_io_error ("fsqrt");
 602 31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
 603 #       do_fsqrt (_SD, rDest, vSource1, vSource2);
 604 31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
 605 #       do_fsqrt (_SD, rDest, LongSignedImmediate, vSource2);
 606
 607
 608 // fsub.{s|d}{s|d}{s|d}
 609 void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
 610         sim_fpu ans = sim_fpu_sub (s1, s2);
 611         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 612         set_fp_reg (_SD, Dest, ans, PD);
 613 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
 614         do_fsub (_SD, Dest, PD,
 615                  get_fp_reg (_SD, Source1, vSource1, P1),
 616                  get_fp_reg (_SD, Source2, vSource2, P2));
 617 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
 618         long_immediate (SinglePrecisionFloatingPoint);
 619         do_fsub (_SD, Dest, PD,
 620                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 621                  get_fp_reg (_SD, Source2, vSource2, P2));
 622
 623
 624 // illop
 625 31./,21.0b0000000,14./::::illop
 626 31./,21.0b111111111,12./::::illop l
 627
 628
 629 // ins - see sl.im
 630
 631
 632 // jsr[.a]
 633 instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
 634         address_word target = offset + base;
 635         TRACE_UCOND_BR (MY_INDEX, target);
 636         nia = do_branch (_SD, annul, target, 1, rLink);
 637         if (nia.dp & 0x3)
 638           sim_engine_abort (SD, CPU, cia,
 639                             "0x%lx: destination address 0x%lx misaligned",
 640                             (unsigned long) cia.ip,
 641                             (unsigned long) nia.dp);
 642         return nia;
 643 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
 644         nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, vBase);
 645 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
 646         nia = do_jsr (_SD, nia, rLink, A, vSource1, vBase);
 647 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
 648         long_immediate (LongSignedImmediate);
 649         nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, vBase);
 650
 651
 652 // ld[{.b.h.d}]
 653 void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 654         unsigned32 addr;
 655         switch (sz)
 656           {
 657           case 0:
 658             addr = base + (S ? (offset << 0) : offset);
 659             if (m)
 660               *rBase = addr;
 661             GPR(Dest) = MEM (signed, addr, 1);
 662             break;
 663           case 1:
 664             addr = base + (S ? (offset << 1) : offset);
 665             if (m)
 666               *rBase = addr;
 667             GPR(Dest) = MEM (signed, addr, 2);
 668             break;
 669           case 2:
 670             addr = base + (S ? (offset << 2) : offset);
 671             if (m)
 672               *rBase = addr;
 673             GPR(Dest) = MEM (signed, addr, 4);
 674             break;
 675           case 3:
 676             {
 677               signed64 val;
 678               if (Dest & 0x1)
 679                 sim_engine_abort (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
 680                                   cia.ip, Dest);
 681               addr = base + (S ? (offset << 3) : offset);
 682               if (m)
 683                 *rBase = addr;
 684               val = MEM (signed, addr, 8);
 685               GPR(Dest + 1) = VH4_8 (val);
 686               GPR(Dest + 0) = VL4_8 (val);
 687             }
 688             break;
 689           default:
 690             addr = -1;
 691             sim_engine_abort (SD, CPU, cia, "ld - invalid sz %d", sz);
 692           }
 693         TRACE_LD (MY_INDEX, GPR(Dest), m, S, base, offset);
 694 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
 695         do_ld (_SD, Dest, vBase, rBase, m, sz, 0, vSignedOffset);
 696 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
 697         do_ld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
 698 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
 699         long_immediate (LongSignedImmediateOffset);
 700         do_ld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 701
 702
 703 // ld.u[{.b.h.d}]
 704 void::function::do_ld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 705         unsigned32 addr;
 706         switch (sz)
 707           {
 708           case 0:
 709             addr = base + (S ? (offset << 0) : offset);
 710             *rDest = MEM (unsigned, addr, 1);
 711             break;
 712           case 1:
 713             addr = base + (S ? (offset << 1) : offset);
 714             *rDest = MEM (unsigned, addr, 2);
 715             break;
 716           default:
 717             addr = -1;
 718             sim_engine_abort (SD, CPU, cia, "ld.u - invalid sz %d", sz);
 719           }
 720         if (m)
 721           *rBase = addr;
 722         TRACE_LD (MY_INDEX, m, S, *rDest, base, offset);
 723 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
 724         do_ld_u (_SD, rDest, vBase, rBase, m, sz, 0, vSignedOffset);
 725 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
 726         do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
 727 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
 728         long_immediate (LongSignedImmediateOffset);
 729         do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 730
 731
 732 // lmo
 733 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
 734         int b;
 735         for (b = 0; b < 32; b++)
 736           if (vSource & BIT32 (31 - b))
 737             break;
 738         TRACE_ALU2 (MY_INDEX, b, vSource);
 739         *rDest = b;
 740
 741
 742 // nop - see rdcr 0, r0
 743
 744
 745 void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 746         unsigned32 result = Source1 | Source2;
 747         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 748         *rDest = result;
 749
 750
 751 // or, or.tt
 752 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
 753         do_or (_SD, rDest, vSource1, vSource2);
 754 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
 755         do_or (_SD, rDest, vSource1, vSource2);
 756 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
 757         long_immediate (LongUnsignedImmediate);
 758         do_or (_SD, rDest, LongUnsignedImmediate, vSource2);
 759
 760
 761 // or.ff
 762 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
 763         do_or (_SD, rDest, ~vSource1, ~vSource2);
 764 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
 765         do_or (_SD, rDest, ~vSource1, ~vSource2);
 766 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
 767         long_immediate (LongUnsignedImmediate);
 768         do_or (_SD, rDest, ~LongUnsignedImmediate, ~vSource2);
 769
 770
 771 // or.ft
 772 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
 773         do_or (_SD, rDest, ~vSource1, vSource2);
 774 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
 775         do_or (_SD, rDest, ~vSource1, vSource2);
 776 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
 777         long_immediate (LongUnsignedImmediate);
 778         do_or (_SD, rDest, ~LongUnsignedImmediate, vSource2);
 779
 780
 781 // or.tf
 782 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
 783         do_or (_SD, rDest, vSource1, ~vSource2);
 784 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
 785         do_or (_SD, rDest, vSource1, ~vSource2);
 786 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
 787         long_immediate (LongUnsignedImmediate);
 788         do_or (_SD, rDest, LongUnsignedImmediate, ~vSource2);
 789
 790
 791 // rdcr
 792 void::function::do_rdcr:unsigned32 Dest, int cr
 793         TRACE_SINK2 (MY_INDEX, Dest, cr);
 794         GPR (Dest) = CR (cr);
 795 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
 796         do_rdcr (_SD, Dest, UCRN);
 797 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
 798         do_rdcr (_SD, Dest, UCRN);
 799 31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
 800         long_immediate (UnsignedControlRegisterNumber);
 801         do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
 802
 803
 804 // rmo
 805 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
 806         int b;
 807         for (b = 0; b < 32; b++)
 808           if (vSource & BIT32 (b))
 809             break;
 810         if (b < 32)
 811           b = 31 - b;
 812         TRACE_ALU2 (MY_INDEX, b, vSource);
 813         *rDest = b;
 814
 815
 816 // rotl - see sl.dz
 817
 818
 819 // rotr - see sl.dz
 820
 821
 822 // shl - see sl.iz
 823
 824
 825 // sl.{d|e|i}{m|s|z}
 826 void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, int EndMask, int Rotate
 827         /* see 10-30 for a reasonable description */
 828         unsigned32 input = source;
 829         unsigned32 rotated;
 830         unsigned32 endmask;
 831         unsigned32 shiftmask;
 832         unsigned32 cm;
 833         int nRotate;
 834         /* rotate the source */
 835         if (n)
 836           {
 837             rotated = ROTR32 (source, Rotate);
 838             nRotate = (- Rotate) & 31;
 839           }
 840         else
 841           {
 842             rotated = ROTL32 (source, Rotate);
 843             nRotate = Rotate;
 844           }
 845         /* form the end mask */
 846         if (EndMask == 0)
 847           endmask = ~ (unsigned32)0;
 848         else
 849           endmask = (1 << EndMask) - 1;
 850         if (i)
 851           endmask = ~endmask;
 852         /* form the shiftmask */
 853         switch (Merge)
 854           {
 855           case 0: case 1: case 2:
 856             shiftmask = ~ (unsigned32)0;        /* disabled */
 857             break;
 858           case 3: case 5:                       /* enabled - 0 -> 32 */
 859             if (nRotate == 0)
 860               shiftmask = ~ (unsigned32)0;
 861             else
 862               shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
 863             break;
 864           case 4:
 865             shiftmask = ((1 << nRotate) - 1);   /* enabled - 0 -> 0 */
 866             break;
 867           case 6: case 7:
 868             shiftmask = ~((1 << nRotate) - 1);  /* inverted */
 869             break;
 870           default:
 871             sim_engine_abort (SD, CPU, cia,
 872                               "0x%lx: Invalid merge (%d) for shift",
 873                               cia.ip, source);
 874             shiftmask = 0;
 875           }
 876         /* and the composite mask */
 877         cm = shiftmask & endmask;
 878         /* and merge */
 879         switch (Merge)
 880           {
 881           case 0: case 3: case 6:               /* zero */
 882             GPR (Dest) = rotated & cm;
 883             break;
 884           case 1: case 4: case 7:               /* merge */
 885             GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
 886             break;
 887           case 2: case 5:                       /* sign */
 888             {
 889               int b;
 890               GPR (Dest) = rotated & cm;
 891               for (b = 1; b <= 31; b++)
 892                 if (!MASKED32 (cm, b, b))
 893                   GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
 894                                             b, b);
 895             }
 896             break;
 897           default:
 898             sim_engine_abort (SD, CPU, cia,
 899                               "0x%lx: Invalid merge (%d)",
 900                               cia.ip, source);
 901
 902           }
 903         TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
 904 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
 905         do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, Rotate);
 906 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
 907         do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, GPR (RotReg) & 31);
 908
 909
 910 // sli.{d|e|i}{m|s|z} - see shift
 911
 912
 913 // sr.{d|e|i}{m|s|z} - see shift
 914
 915
 916 // sra - see sr.es - see shift
 917
 918
 919 // sri.{d|e|i}{m|s|z} - see shift
 920
 921
 922 // srl - see sr.ez
 923
 924
 925 // st[{.b|.h|.d}]
 926 void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 927         unsigned32 addr;
 928         switch (sz)
 929           {
 930           case 0:
 931             addr = base + (S ? (offset << 0) : offset);
 932             STORE (addr, 1, GPR(Source));
 933             break;
 934           case 1:
 935             addr = base + (S ? (offset << 1) : offset);
 936             STORE (addr, 2, GPR(Source));
 937             break;
 938           case 2:
 939             addr = base + (S ? (offset << 2) : offset);
 940             STORE (addr, 4, GPR(Source));
 941             break;
 942           case 3:
 943             {
 944               signed64 val;
 945               if (Source & 0x1)
 946                 sim_engine_abort (SD, CPU, cia,
 947                                   "0x%lx: st.d with odd source register %d",
 948                                   cia.ip, Source);
 949               addr = base + (S ? (offset << 3) : offset);
 950               val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
 951               STORE (addr, 8, val);
 952             }
 953             break;
 954           default:
 955             addr = -1;
 956             sim_engine_abort (SD, CPU, cia, "st - invalid sz %d", sz);
 957           }
 958         if (m)
 959           *rBase = addr;
 960         TRACE_ST (MY_INDEX, Source, m, S, base, offset);
 961 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
 962         do_st (_SD, Source, vBase, rBase, m, sz, 0, vSignedOffset);
 963 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
 964         do_st (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
 965 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
 966         long_immediate (LongSignedImmediateOffset);
 967         do_st (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 968
 969
 970 // sub
 971 void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
 972         ALU_BEGIN (Source1);
 973         ALU_SUB (Source2);
 974         ALU_END (*rDest);
 975         TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
 976 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
 977         do_sub (_SD, rDest, vSource1, vSource2);
 978 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
 979         do_sub (_SD, rDest, vSource1, vSource2);
 980 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
 981         long_immediate (LongSignedImmediate);
 982         do_sub (_SD, rDest, LongSignedImmediate, vSource2);
 983
 984
 985 // subu
 986 void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
 987         unsigned32 result = Source1 - Source2;
 988         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 989         *rDest = result;
 990 // NOTE - the book has 15.1 which conflicts with subu.
 991 31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i
 992         do_subu (_SD, rDest, vSource1, vSource2);
 993 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
 994         do_subu (_SD, rDest, vSource1, vSource2);
 995 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
 996         long_immediate (LongSignedImmediate);
 997         do_subu (_SD, rDest, LongSignedImmediate, vSource2);
 998
 999
1000 // swcr
1001 void::function::do_swcr:int Dest, signed32 source, signed32 cr
1002         tic80_control_regs reg = tic80_index2cr (cr);
1003         /* cache the old CR value */
1004         unsigned32 old_cr = CR (cr);
1005         /* Handle the write if allowed */
1006         if (cr >= 0x4000 || !(CPU)->is_user_mode)
1007           switch (reg)
1008             {
1009             case INTPEN_CR:
1010               CR (cr) &= ~source;
1011               break;
1012             default:
1013               CR (cr) = source;
1014               break;
1015             }
1016         /* Finish off the read */
1017         GPR (Dest) = old_cr;
1018         TRACE_SINK3 (MY_INDEX, source, cr, Dest);
1019 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
1020         do_swcr (_SD, Dest, vSource, UCRN);
1021 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
1022         do_swcr (_SD, Dest, vSource, UCRN);
1023 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
1024         long_immediate (LongUnsignedControlRegister);
1025         do_swcr (_SD, Dest, vSource, LongUnsignedControlRegister);
1026
1027
1028 // trap
1029 void::function::do_trap:unsigned32 trap_number
1030         int i;
1031         TRACE_SINK1 (MY_INDEX, trap_number);
1032         switch (trap_number)
1033           {
1034           case 72:
1035             switch (GPR(15))
1036               {
1037               case 1: /* EXIT */
1038                 {
1039                   sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR(2));
1040                   break;
1041                 }
1042               case 4: /* WRITE */
1043                 {
1044                   int i;
1045                   if (GPR(2) == 1)
1046                     for (i = 0; i < GPR(6); i++)
1047                       {
1048                         char c;
1049                         c = MEM (unsigned, GPR(4) + i, 1);
1050                         sim_io_write_stdout (SD, &c, 1);
1051                       }
1052                   else if (GPR(2) == 2)
1053                     for (i = 0; i < GPR(6); i++)
1054                       {
1055                         char c;
1056                         c = MEM (unsigned, GPR(4) + i, 1);
1057                         sim_io_write_stderr (SD, &c, 1);
1058                       }
1059                   else
1060                     sim_engine_abort (SD, CPU, cia,
1061                                       "0x%lx: write to invalid fid %d",
1062                                       (unsigned long) cia.ip, GPR(2));
1063                   GPR(2) = GPR(6);
1064                   break;
1065                 }
1066               default:
1067                 /* For system calls which are defined, just return EINVAL instead of trapping */
1068                 if (GPR(15) <= 204)
1069                   {
1070                     GPR(2) = -22;               /* -EINVAL */
1071                     break;
1072                   }
1073                 sim_engine_abort (SD, CPU, cia,
1074                                   "0x%lx: unknown syscall %d",
1075                                   (unsigned long) cia.ip, GPR(15));
1076               }
1077             break;
1078           case 73:
1079             sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1080
1081           /* Add a few traps for now to print the register state */
1082           case 74:
1083           case 75:
1084           case 76:
1085           case 77:
1086           case 78:
1087           case 79:
1088             if (!TRACE_ALU_P (CPU))
1089               trace_one_insn (SD, CPU, cia.ip, 1, itable[MY_INDEX].file,
1090                               itable[MY_INDEX].line_nr, "trap",
1091                               "Trap %ld", (long) trap_number);
1092
1093             for (i = 0; i < 32; i++)
1094               sim_io_eprintf (SD, "%s0x%.8lx%s", ((i % 8) == 0) ? "\t" : " ", (long)GPR(i),
1095                               (((i+1) % 8) == 0) ? "\n" : "");
1096             sim_io_write_stderr (SD, "\n", 1);
1097             break;
1098
1099           default:
1100             sim_engine_abort (SD, CPU, cia,
1101                               "0x%lx: unsupported trap %d",
1102                               (unsigned long) cia.ip, trap_number);
1103           }
1104 31./,27.0,26./,21.0b0000001,14.UTN::::trap i
1105         do_trap (_SD, UTN);
1106 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
1107         do_trap (_SD, UTN);
1108 31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
1109         long_immediate (UTN);
1110         do_trap (_SD, UTN);
1111
1112
1113 // vadd.{s|d}{s|d}
1114 31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r
1115 31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l
1116
1117
1118 // vld{0|1}.{s|d} - see above - same instruction
1119 #31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld
1120
1121
1122 // vmac.ss{s|d}
1123 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra
1124 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr
1125 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia
1126 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir
1127
1128
1129 // vmpy.{s|d}{s|d}
1130 31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r
1131 31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l
1132
1133
1134 // vmsc.ss{s|d}
1135 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra
1136 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr
1137 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia
1138 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir
1139
1140
1141 // vmsub.{s|d}{s|d}
1142 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r
1143 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l
1144
1145
1146 // vrnd.{s|d}{s|d}
1147 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r
1148 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l
1149
1150
1151 // vrnd.{i|u}{s|d}
1152 31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r
1153 31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l
1154
1155
1156 // vst.{s|d} - see above - same instruction
1157 #31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst
1158
1159
1160 // vsub.{i|u}{s|d}
1161 31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r
1162 31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l
1163
1164
1165 // wrcr - see swcr, creg, source, r0
1166
1167
1168 // xnor
1169 void::function::do_xnor:signed32 *rDest, signed32 source1, signed32 source2
1170         unsigned32 result = ~ (source1 ^ source2);
1171         TRACE_ALU3 (MY_INDEX, result, source1, source2);
1172         *rDest = result;
1173 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
1174         do_xnor (_SD, rDest, vSource1, vSource2);
1175 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
1176         do_xnor (_SD, rDest, vSource1, vSource2);
1177 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
1178         long_immediate (LongUnsignedImmediate);
1179         do_xnor (_SD, rDest, LongUnsignedImmediate, vSource2);
1180
1181
1182 // xor
1183 void::function::do_xor:signed32 *rDest, signed32 source1, signed32 source2
1184         unsigned32 result = source1 ^ source2;
1185         TRACE_ALU3 (MY_INDEX, result, source1, source2);
1186         *rDest = result;
1187 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
1188         do_xor (_SD, rDest, vSource1, vSource2);
1189 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
1190         do_xor (_SD, rDest, vSource1, vSource2);
1191 31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l
1192         long_immediate (LongUnsignedImmediate);
1193         do_xor (_SD, rDest, LongUnsignedImmediate, vSource2);