sim/tic80/insns

   1 // Texas Instruments TMS320C80 (MVP) Simulator.
   2 // Copyright (C) 1997 Free Software Foundation, Inc.
   3 // Contributed by Cygnus Support.
   4 //
   5 // This file is part of GDB, the GNU debugger.
   6 //
   7 // This program is free software; you can redistribute it and/or modify
   8 // it under the terms of the GNU General Public License as published by
   9 // the Free Software Foundation; either version 2, or (at your option)
  10 // any later version.
  11 //
  12 // This program is distributed in the hope that it will be useful,
  13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 // GNU General Public License for more details.
  16 //
  17 // You should have received a copy of the GNU General Public License along
  18 // with this program; if not, write to the Free Software Foundation, Inc.,
  19 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21
  22 // The following is called when ever an illegal instruction is encountered.
  23 ::internal::illegal
  24         engine_error (SD, CPU, cia,
  25                       "illegal instruction at 0x%lx", cia.ip);
  26 // The following is called when ever an FP op is attempted with FPU disabled.
  27 ::internal::fp_unavailable
  28         engine_error (SD, CPU, cia,
  29                       "floating-point unavailable at 0x%lx", cia.ip);
  30
  31 // Handle a branch instruction
  32 instruction_address::function::do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink
  33         instruction_address nia;
  34         if (annul)
  35           {
  36             if (rLink_p)
  37               *rLink = cia.dp;
  38             nia.ip = target;
  39             nia.dp = target + 4;
  40           }
  41         else
  42           {
  43             if (rLink_p)
  44               *rLink = cia.dp + sizeof (instruction_word);
  45             nia.ip = cia.dp;
  46             nia.dp = target;
  47           }
  48         return nia;
  49
  50 // Signed Integer Add - add source1, source2, dest
  51 void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2
  52         ALU_BEGIN (Source1);
  53         ALU_ADD (Source2);
  54         ALU_END (*rDest);
  55         TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
  56         /* FIXME - a signed add may cause an exception */
  57 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
  58         do_add (_SD, rDest, vSource1, rSource2);
  59 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
  60         do_add (_SD, rDest, rSource1, rSource2);
  61 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
  62         long_immediate (LongSignedImmediate);
  63         do_add (_SD, rDest, LongSignedImmediate, rSource2);
  64
  65
  66 // Unsigned Integer Add - addu source1, source2, dest
  67 void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
  68         unsigned32 result = Source1 + Source2;
  69         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
  70         *rDest = result;
  71
  72 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
  73         do_addu (_SD, rDest, vSource1, rSource2);
  74 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
  75         do_addu (_SD, rDest, rSource1, rSource2);
  76 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
  77         long_immediate (LongSignedImmediate);
  78         do_addu (_SD, rDest, LongSignedImmediate, rSource2);
  79
  80
  81 void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
  82         unsigned32 result = Source1 & Source2;
  83         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
  84         *rDest = result;
  85
  86
  87 // and, and.tt
  88 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
  89         do_and (_SD, rDest, vSource1, rSource2);
  90 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
  91         do_and (_SD, rDest, rSource1, rSource2);
  92 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
  93         long_immediate (LongSignedImmediate);
  94         do_and (_SD, rDest, LongSignedImmediate, rSource2);
  95
  96
  97 // and.ff
  98 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
  99         do_and (_SD, rDest, ~vSource1, ~rSource2);
 100 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
 101         do_and (_SD, rDest, ~rSource1, ~rSource2);
 102 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
 103         long_immediate (LongSignedImmediate);
 104         do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2);
 105
 106
 107 // and.ft
 108 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
 109         do_and (_SD, rDest, ~vSource1, rSource2);
 110 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
 111         do_and (_SD, rDest, ~rSource1, rSource2);
 112 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
 113         long_immediate (LongSignedImmediate);
 114         do_and (_SD, rDest, ~LongSignedImmediate, rSource2);
 115
 116
 117 // and.tf
 118 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
 119         do_and (_SD, rDest, vSource1, ~rSource2);
 120 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
 121         do_and (_SD, rDest, rSource1, ~rSource2);
 122 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
 123         long_immediate (LongSignedImmediate);
 124         do_and (_SD, rDest, LongSignedImmediate, ~rSource2);
 125
 126
 127 // bbo.[a]
 128 instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 129         int jump_p;
 130         address_word target = cia.ip + 4 * offset;
 131         bitnum = (~ bitnum) & 0x1f;
 132         if (MASKED32 (source, bitnum, bitnum))
 133           {
 134             nia = do_branch (_SD, annul, target, 0, NULL);
 135             jump_p = 1;
 136           }
 137         else
 138           jump_p = 0;
 139         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 140         return nia;
 141 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
 142         nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset);
 143 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
 144         nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff);
 145 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
 146         long_immediate (LongSignedImmediate);
 147         nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
 148
 149
 150 // bbz[.a]
 151 instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
 152         int jump_p;
 153         address_word target = cia.ip + 4 * offset;
 154         bitnum = (~ bitnum) & 0x1f;
 155         if (!MASKED32 (source, bitnum, bitnum))
 156           {
 157             nia = do_branch (_SD, annul, target, 0, NULL);
 158             jump_p = 1;
 159           }
 160         else
 161           jump_p = 0;
 162         TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 163         return nia;
 164 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
 165         nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset);
 166 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
 167         nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff);
 168 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
 169         long_immediate (LongSignedImmediate);
 170         nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
 171
 172
 173 // bcnd[.a]
 174 instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
 175         int condition;
 176         int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
 177         int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
 178         signed32 val = 0;
 179         address_word target = cia.ip + 4 * offset;
 180         switch (size)
 181           {
 182           case 0: val = SEXT32 (source, 7); break;
 183           case 1: val = SEXT32 (source, 15); break;
 184           case 2: val = source; break;
 185           default: engine_error (SD, CPU, cia, "bcnd - reserved size");
 186           }
 187         switch (code)
 188           {
 189           case 0: condition = 0; break;
 190           case 1: condition = val > 0; break;
 191           case 2: condition = val == 0; break;
 192           case 3: condition = val >= 0; break;
 193           case 4: condition = val < 0; break;
 194           case 5: condition = val != 0; break;
 195           case 6: condition = val <= 0; break;
 196           default: condition = 1; break;
 197           }
 198         if (condition)
 199           {
 200             nia = do_branch (_SD, annul, target, 0, NULL);
 201           }
 202         TRACE_COND_BR(MY_INDEX, condition, source, target);
 203         return nia;
 204 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
 205         nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset);
 206 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
 207         nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff);
 208 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
 209         long_immediate (LongSignedImmediate);
 210         nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate);
 211
 212
 213 // br[.a] - see bbz[.a]
 214
 215
 216 // brcr
 217 sim_cia::function::do_brcr:instruction_address nia, int cr
 218         if (cr >= 0x4000 || !(CPU)->is_user_mode)
 219           {
 220             unsigned32 control = CR (cr);
 221             unsigned32 ie = control & 0x00000001;
 222             unsigned32 pc = control & 0xfffffffc;
 223             unsigned32 is_user_mode = control & 0x00000002;
 224             (CPU)->is_user_mode = is_user_mode;
 225             nia.dp = pc;
 226             if (ie)
 227               (CPU)->cr[IE_CR] |= IE_CR_IE;
 228             else
 229               (CPU)->cr[IE_CR] &= ~IE_CR_IE;
 230           }
 231         TRACE_UCOND_BR (MY_INDEX, nia.dp);
 232         return nia;
 233 31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i
 234         nia = do_brcr (_SD, nia, UCRN);
 235 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r
 236         nia = do_brcr (_SD, nia, UCRN);
 237 31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l
 238         long_immediate (UnsignedControlRegisterNumber)
 239         nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber);
 240
 241
 242 // bsr[.a]
 243 instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
 244         address_word target = cia.ip + 4 * offset;
 245         nia = do_branch (_SD, annul, target, 1, rLink);
 246         TRACE_UCOND_BR (MY_INDEX, target);
 247         return nia;
 248 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
 249         nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
 250 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
 251         nia = do_bsr (_SD, nia, rLink, A, rIndOff);
 252 31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
 253         long_immediate (LongSignedImmediate);
 254         nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
 255
 256
 257 // cmnd
 258 void::function::do_cmnd:signed32 source
 259         int Reset = EXTRACTED32 (source, 31, 31);
 260         int Halt = EXTRACTED32 (source, 30, 30);
 261         int Unhalt = EXTRACTED32 (source, 29, 29);
 262         /* int ICR = EXTRACTED32 (source, 28, 28); */
 263         /* int DCR = EXTRACTED32 (source, 27, 27); */
 264         int Task = EXTRACTED32 (source, 14, 14);
 265         int Msg = EXTRACTED32 (source, 13, 13);
 266         int VC = EXTRACTED32 (source, 10, 10);
 267         int TC = EXTRACTED32 (source, 9, 9);
 268         int MP = EXTRACTED32 (source, 8, 8);
 269         int PP = EXTRACTED32 (source, 3, 0);
 270         /* what is implemented? */
 271         if (PP != 0)
 272           engine_error (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
 273                         (unsigned long) cia.ip);
 274         if (VC != 0)
 275           engine_error (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
 276                         (unsigned long) cia.ip);
 277         if (TC != 0)
 278           engine_error (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
 279                         (unsigned long) cia.ip);
 280         if (MP)
 281           {
 282             if (Reset || Halt)
 283               engine_halt (SD, CPU, cia, sim_exited, 0);
 284             if (Unhalt)
 285               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
 286                             (unsigned long) cia.ip);
 287             /* if (ICR || DCR); */
 288             if (Task)
 289               engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
 290                             (unsigned long) cia.ip);
 291             if (Msg)
 292               engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
 293                             (unsigned long) cia.ip);
 294           }
 295         TRACE_SINK1 (MY_INDEX, source);
 296 31./,21.0b0000010,14.UI::::cmnd i
 297         do_cmnd (_SD, UI);
 298 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
 299         do_cmnd (_SD, rSource);
 300 31./,21.0b110000010,12.1,11./::::cmnd l
 301         long_immediate (LongUnsignedImmediate);
 302         do_cmnd (_SD, LongUnsignedImmediate);
 303
 304 // cmp
 305 unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
 306         unsigned32 field = 0;
 307         if (s1 == s2) field |= 0x001;
 308         if (s1 != s2) field |= 0x002;
 309         if (s1 >  s2) field |= 0x004;
 310         if (s1 <= s2) field |= 0x008;
 311         if (s1 <  s2) field |= 0x010;
 312         if (s1 >= s2) field |= 0x020;
 313         if (u1 >  u2) field |= 0x040;
 314         if (u1 <= u2) field |= 0x080;
 315         if (u1 <  u2) field |= 0x100;
 316         if (u1 >= u2) field |= 0x200;
 317         return field;
 318 void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 319         unsigned32 field = 0;
 320         field |= cmp_vals (_SD, Source1, Source1, Source2, Source2) << 20;
 321         field |= cmp_vals (_SD, (signed16)Source1, (unsigned16)Source1,
 322                            (signed16)Source2, (unsigned16)Source2) << 10;
 323         field |= cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1,
 324                             (signed8)Source2, (unsigned8)Source2);
 325         TRACE_ALU3 (MY_INDEX, field, Source1, Source2);
 326         *rDest = field;
 327 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
 328         do_cmp (_SD, rDest, vSource1, rSource2);
 329 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
 330         do_cmp (_SD, rDest, rSource1, rSource2);
 331 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
 332         long_immediate (LongSignedImmediate);
 333         do_cmp (_SD, rDest, LongSignedImmediate, rSource2);
 334
 335
 336 // dcache
 337 31./,27.F,26.Source2,21.0b0111,17.M,16.0b00,14.SignedOffset::::dcache i
 338         TRACE_NOP (MY_INDEX);
 339         /* NOP */
 340 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.0,11./,4.Source1::::dcache r
 341         TRACE_NOP (MY_INDEX);
 342         /* NOP */
 343 31./,27.F,26.Source2,21.0b110111,15.M,14.0b00,12.1,11./::::dcache l
 344         long_immediate (LongSignedImmediate);
 345         LongSignedImmediate++;
 346         TRACE_NOP (MY_INDEX);
 347         /* NOP */
 348
 349
 350 // dld[{.b|.h|.d}]
 351 void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 352         do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset);
 353 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
 354         do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
 355 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
 356         long_immediate (LongSignedImmediateOffset);
 357         do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 358
 359
 360 // dld.u[{.b|.h|.d}]
 361 void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 362         do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset);
 363 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
 364         do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
 365 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
 366         long_immediate (LongSignedImmediateOffset);
 367         do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 368
 369
 370 // dst[{.b|.h|.d}]
 371 void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 372         do_st (_SD, Source, Base, rBase, m, sz, S, Offset);
 373 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
 374         do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
 375 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
 376         long_immediate (LongSignedImmediateOffset);
 377         do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 378
 379
 380 // estop
 381 31./,21.0b1111111,14.1,13.0,12.0,11./::::estop
 382
 383 // etrap
 384 31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
 385 31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
 386 31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
 387
 388
 389 // exts - see shift.ds
 390
 391
 392 // extu - see shift.dz
 393
 394
 395 sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
 396         switch (precision)
 397           {
 398           case 0: /* single */
 399             if (reg == 0)
 400               return sim_fpu_32to (0);
 401             else
 402               return sim_fpu_32to (val);
 403           case 1: /* double */
 404             if (reg < 0)
 405               return sim_fpu_32to (val);
 406             if (reg & 1)
 407               engine_error (SD, CPU, cia, "DP FP register must be even");
 408             if (reg <= 1)
 409               engine_error (SD, CPU, cia, "DP FP register must be >= 2");
 410             return sim_fpu_64to (INSERTED64 (GPR(reg + 1), 63, 32)
 411                                  | INSERTED64 (GPR(reg), 31, 0));
 412           case 2: /* 32 bit signed integer */
 413             if (reg == 0)
 414               return sim_fpu_32to (0);
 415             else
 416               return sim_fpu_d2 ((signed32) val);
 417           case 3: /* 32 bit unsigned integer */
 418             if (reg == 0)
 419               return sim_fpu_32to (0);
 420             else
 421               return sim_fpu_d2 ((unsigned32) val);
 422           default:
 423             engine_error (SD, CPU, cia, "Unsupported FP precision");
 424           }
 425         return sim_fpu_32to (0);
 426 void::function::set_fp_reg:int Dest, sim_fpu val, int PD
 427         switch (PD)
 428           {
 429           case 0: /* single */
 430             {
 431               GPR (Dest) = sim_fpu_to32 (val);
 432               break;
 433             }
 434           case 1: /* double */
 435             {
 436               unsigned64 v = *(unsigned64*) &val;
 437               if (Dest & 1)
 438                 engine_error (SD, CPU, cia, "DP FP Dest register must be even");
 439               if (Dest <= 1)
 440                 engine_error (SD, CPU, cia, "DP FP Dest register must be >= 2");
 441               GPR (Dest) = EXTRACTED64 (v, 21, 0);
 442               GPR (Dest + 1) = EXTRACTED64 (v, 63, 32);
 443               break;
 444             }
 445           case 2: /* signed */
 446             /* FIXME - rounding */
 447             GPR (Dest) = sim_fpu_2d (val);
 448             break;
 449           case 3: /* unsigned */
 450             /* FIXME - rounding */
 451             GPR (Dest) = sim_fpu_2d (val);
 452             break;
 453           default:
 454             engine_error (SD, CPU, cia, "Unsupported FP precision");
 455           }
 456
 457 // fadd.{s|d}{s|d}{s|d}
 458 void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
 459         sim_fpu ans = sim_fpu_add (s1, s2);
 460         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 461         set_fp_reg (_SD, Dest, ans, PD);
 462 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
 463         do_fadd (_SD, Dest, PD,
 464                  get_fp_reg (_SD, Source1, rSource1, P1),
 465                  get_fp_reg (_SD, Source2, rSource2, P2));
 466 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
 467         long_immediate (SinglePrecisionFloatingPoint);
 468         do_fadd (_SD, Dest, PD,
 469                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 470                  get_fp_reg (_SD, Source2, rSource2, P2));
 471
 472
 473 // fcmp.{s|d}{s|d}{s|d}
 474 void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
 475         *rDest = 0;
 476         if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
 477           *rDest |= BIT32 (30);
 478         else
 479           {
 480             *rDest |= BIT32 (31);
 481             if (sim_fpu_cmp (s1, s2) == 0) *rDest |= BIT32(20);
 482             if (sim_fpu_cmp (s1, s2) != 0) *rDest |= BIT32(21);
 483             if (sim_fpu_cmp (s1, s2) >  0) *rDest |= BIT32(22);
 484             if (sim_fpu_cmp (s1, s2) <= 0) *rDest |= BIT32(23);
 485             if (sim_fpu_cmp (s1, s2) <  0) *rDest |= BIT32(24);
 486             if (sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(25);
 487             if (sim_fpu_cmp (s1, sim_fpu_32to (0)) < 0
 488                 || sim_fpu_cmp (s1, s2) > 0) *rDest |= BIT32(26);
 489             if (sim_fpu_cmp (sim_fpu_32to (0), s1) < 0
 490                 && sim_fpu_cmp (s1, s2) < 0) *rDest |= BIT32(27);
 491             if (sim_fpu_cmp (sim_fpu_32to (0), s1) <= 0
 492                 && sim_fpu_cmp (s1, s2) <= 0) *rDest |= BIT32(28);
 493             if (sim_fpu_cmp (s1, sim_fpu_32to (0)) <= 0
 494                 || sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(29);
 495           }
 496         TRACE_FPU2I (MY_INDEX, *rDest, s1, s2);
 497 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
 498         do_fcmp (_SD, rDest,
 499                  get_fp_reg (_SD, Source1, rSource1, P1),
 500                  get_fp_reg (_SD, Source2, rSource2, P2));
 501 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
 502         long_immediate (SinglePrecisionFloatingPoint);
 503         do_fcmp (_SD, rDest,
 504                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 505                  get_fp_reg (_SD, Source2, rSource2, P2));
 506
 507
 508
 509 // fdiv.{s|d}{s|d}{s|d}
 510 void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
 511         sim_fpu ans = sim_fpu_div (s1, s2);
 512         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 513         set_fp_reg (_SD, Dest, ans, PD);
 514 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
 515         do_fdiv (_SD, Dest, PD,
 516                  get_fp_reg (_SD, Source1, rSource1, P1),
 517                  get_fp_reg (_SD, Source2, rSource2, P2));
 518 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
 519         long_immediate (SinglePrecisionFloatingPoint);
 520         do_fdiv (_SD, Dest, PD,
 521                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 522                  get_fp_reg (_SD, Source2, rSource2, P2));
 523
 524
 525 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 526 void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
 527         sim_fpu ans = sim_fpu_mul (s1, s2);
 528         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 529         set_fp_reg (_SD, Dest, ans, PD);
 530 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
 531         do_fmpy (_SD, Dest, PD,
 532                  get_fp_reg (_SD, Source1, rSource1, P1),
 533                  get_fp_reg (_SD, Source2, rSource2, P2));
 534 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
 535         long_immediate (SinglePrecisionFloatingPoint);
 536         do_fmpy (_SD, Dest, PD,
 537                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 538                  get_fp_reg (_SD, Source2, rSource2, P2));
 539
 540
 541 // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 542 void::function::do_frnd:int Dest, int PD, sim_fpu s1
 543         set_fp_reg (_SD, Dest, s1, PD);
 544 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
 545         do_frnd (_SD, Dest, PD,
 546                  get_fp_reg (_SD, Source, rSource, P1));
 547 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
 548         long_immediate (SinglePrecisionFloatingPoint);
 549         do_frnd (_SD, Dest, PD,
 550                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 551
 552
 553 // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 554 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
 555         do_frnd (_SD, Dest, PD,
 556                  get_fp_reg (_SD, Source, rSource, P1));
 557 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
 558         long_immediate (SinglePrecisionFloatingPoint);
 559         do_frnd (_SD, Dest, PD,
 560                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 561
 562
 563 // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 564 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
 565         do_frnd (_SD, Dest, PD,
 566                  get_fp_reg (_SD, Source, rSource, P1));
 567 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
 568         long_immediate (SinglePrecisionFloatingPoint);
 569         do_frnd (_SD, Dest, PD,
 570                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 571
 572
 573 // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 574 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
 575         do_frnd (_SD, Dest, PD,
 576                  get_fp_reg (_SD, Source, rSource, P1));
 577 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
 578         long_immediate (SinglePrecisionFloatingPoint);
 579         do_frnd (_SD, Dest, PD,
 580                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
 581
 582
 583 // fsqrt.{s|d}{s|d}{s|d}
 584 #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 585 #       sim_io_error ("fsqrt");
 586 31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
 587 #       do_fsqrt (_SD, rDest, rSource1, rSource2);
 588 31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
 589 #       do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2);
 590
 591
 592 // fsub.{s|d}{s|d}{s|d}
 593 void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
 594         sim_fpu ans = sim_fpu_sub (s1, s2);
 595         TRACE_FPU3 (MY_INDEX, ans, s1, s2);
 596         set_fp_reg (_SD, Dest, ans, PD);
 597 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
 598         do_fsub (_SD, Dest, PD,
 599                  get_fp_reg (_SD, Source1, rSource1, P1),
 600                  get_fp_reg (_SD, Source2, rSource2, P2));
 601 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
 602         long_immediate (SinglePrecisionFloatingPoint);
 603         do_fsub (_SD, Dest, PD,
 604                  get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
 605                  get_fp_reg (_SD, Source2, rSource2, P2));
 606
 607
 608 // illop
 609 31./,21.0b0000000,14./::::illop
 610 31./,21.0b111111111,12./::::illop l
 611
 612
 613 // ins - see sl.im
 614
 615
 616 // jsr[.a]
 617 instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
 618         address_word target = offset + base;
 619         TRACE_UCOND_BR (MY_INDEX, target);
 620         nia = do_branch (_SD, annul, target, 1, rLink);
 621         if (nia.dp & 0x3)
 622           engine_error (SD, CPU, cia,
 623                         "0x%lx: destination address 0x%lx misaligned",
 624                         (unsigned long) cia.ip,
 625                         (unsigned long) nia.dp);
 626         return nia;
 627 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
 628         nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase);
 629 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
 630         nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase);
 631 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
 632         long_immediate (LongSignedImmediate);
 633         nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase);
 634
 635
 636 // ld[{.b.h.d}]
 637 void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 638         unsigned32 addr;
 639         switch (sz)
 640           {
 641           case 0:
 642             addr = Base + (S ? (Offset << 0) : Offset);
 643             if (m)
 644               *rBase = addr;
 645             GPR(Dest) = MEM (signed, addr, 1);
 646             break;
 647           case 1:
 648             addr = Base + (S ? (Offset << 1) : Offset);
 649             if (m)
 650               *rBase = addr;
 651             GPR(Dest) = MEM (signed, addr, 2);
 652             break;
 653           case 2:
 654             addr = Base + (S ? (Offset << 2) : Offset);
 655             if (m)
 656               *rBase = addr;
 657             GPR(Dest) = MEM (signed, addr, 4);
 658             break;
 659           case 3:
 660             {
 661               signed64 val;
 662               if (Dest & 0x1)
 663                 engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
 664                               cia.ip, Dest);
 665               addr = Base + (S ? (Offset << 3) : Offset);
 666               if (m)
 667                 *rBase = addr;
 668               val = MEM (signed, addr, 8);
 669               GPR(Dest + 1) = VH4_8 (val);
 670               GPR(Dest + 0) = VL4_8 (val);
 671             }
 672             break;
 673           default:
 674             addr = -1;
 675             engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
 676           }
 677         TRACE_LD (MY_INDEX, GPR(Dest), m, S, Base, Offset);
 678 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
 679         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 680 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
 681         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
 682 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
 683         long_immediate (LongSignedImmediateOffset);
 684         do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 685
 686
 687 // ld.u[{.b.h.d}]
 688 void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 689         unsigned32 addr;
 690         switch (sz)
 691           {
 692           case 0:
 693             addr = Base + (S ? (Offset << 0) : Offset);
 694             *rDest = MEM (unsigned, addr, 1);
 695             break;
 696           case 1:
 697             addr = Base + (S ? (Offset << 1) : Offset);
 698             *rDest = MEM (unsigned, addr, 2);
 699             break;
 700           default:
 701             addr = -1;
 702             engine_error (SD, CPU, cia, "ld.u - invalid sz %d", sz);
 703           }
 704         if (m)
 705           *rBase = addr;
 706         TRACE_LD (MY_INDEX, m, S, *rDest, Base, Offset);
 707 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
 708         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 709 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
 710         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
 711 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
 712         long_immediate (LongSignedImmediateOffset);
 713         do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 714
 715
 716 // lmo
 717 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
 718         int b;
 719         for (b = 0; b < 32; b++)
 720           if (rSource & BIT32 (31 - b))
 721             break;
 722         TRACE_ALU2 (MY_INDEX, b, rSource);
 723         *rDest = b;
 724
 725
 726 // nop - see rdcr 0, r0
 727
 728
 729 void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 730         unsigned32 result = Source1 | Source2;
 731         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 732         *rDest = result;
 733
 734
 735 // or, or.tt
 736 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
 737         do_or (_SD, rDest, vSource1, rSource2);
 738 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
 739         do_or (_SD, rDest, rSource1, rSource2);
 740 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
 741         long_immediate (LongUnsignedImmediate);
 742         do_or (_SD, rDest, LongUnsignedImmediate, rSource2);
 743
 744
 745 // or.ff
 746 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
 747         do_or (_SD, rDest, ~vSource1, ~rSource2);
 748 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
 749         do_or (_SD, rDest, ~rSource1, ~rSource2);
 750 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
 751         long_immediate (LongUnsignedImmediate);
 752         do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2);
 753
 754
 755 // or.ft
 756 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
 757         do_or (_SD, rDest, ~vSource1, rSource2);
 758 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
 759         do_or (_SD, rDest, ~rSource1, rSource2);
 760 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
 761         long_immediate (LongUnsignedImmediate);
 762         do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2);
 763
 764
 765 // or.tf
 766 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
 767         do_or (_SD, rDest, vSource1, ~rSource2);
 768 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
 769         do_or (_SD, rDest, rSource1, ~rSource2);
 770 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
 771         long_immediate (LongUnsignedImmediate);
 772         do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2);
 773
 774
 775 // rdcr
 776 void::function::do_rdcr:unsigned32 Dest, int cr
 777         TRACE_SINK2 (MY_INDEX, Dest, cr);
 778         GPR (Dest) = CR (cr);
 779 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
 780         do_rdcr (_SD, Dest, UCRN);
 781 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
 782         do_rdcr (_SD, Dest, UCRN);
 783 31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
 784         long_immediate (UnsignedControlRegisterNumber);
 785         do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
 786
 787
 788 // rmo
 789 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
 790         int b;
 791         for (b = 0; b < 32; b++)
 792           if (rSource & BIT32 (b))
 793             break;
 794         if (b < 32)
 795           b = 31 - b;
 796         TRACE_ALU2 (MY_INDEX, b, rSource);
 797         *rDest = b;
 798
 799
 800 // rotl - see sl.dz
 801
 802
 803 // rotr - see sl.dz
 804
 805
 806 // shl - see sl.iz
 807
 808
 809 // sl.{d|e|i}{m|s|z}
 810 void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
 811         /* see 10-30 for a reasonable description */
 812         unsigned32 input = GPR (Source);
 813         unsigned32 rotated;
 814         unsigned32 endmask;
 815         unsigned32 shiftmask;
 816         unsigned32 cm;
 817         int nRotate;
 818         /* rotate the source */
 819         if (n)
 820           {
 821             rotated = ROTR32 (GPR (Source), Rotate);
 822             nRotate = (- Rotate) & 31;
 823           }
 824         else
 825           {
 826             rotated = ROTL32 (GPR (Source), Rotate);
 827             nRotate = Rotate;
 828           }
 829         /* form the end mask */
 830         if (EndMask == 0)
 831           endmask = ~ (unsigned32)0;
 832         else
 833           endmask = (1 << EndMask) - 1;
 834         if (i)
 835           endmask = ~endmask;
 836         /* form the shiftmask */
 837         switch (Merge)
 838           {
 839           case 0: case 1: case 2:
 840             shiftmask = ~ (unsigned32)0;        /* disabled */
 841             break;
 842           case 3: case 4: case 5:
 843             shiftmask = ((1 << nRotate) - 1);   /* enabled */
 844             break;
 845           case 6: case 7:
 846             shiftmask = ~((1 << nRotate) - 1);  /* inverted */
 847             break;
 848           default:
 849             engine_error (SD, CPU, cia,
 850                           "0x%lx: Invalid merge (%d) for shift",
 851                           cia.ip, Source);
 852             shiftmask = 0;
 853           }
 854         /* and the composite mask */
 855         cm = shiftmask & endmask;
 856         /* and merge */
 857         switch (Merge)
 858           {
 859           case 0: case 3: case 6:               /* zero */
 860             GPR (Dest) = rotated & cm;
 861             break;
 862           case 1: case 4: case 7:               /* merge */
 863             GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
 864             break;
 865           case 2: case 5:                       /* sign */
 866             {
 867               int b;
 868               GPR (Dest) = rotated & cm;
 869               for (b = 1; b <= 31; b++)
 870                 if (!MASKED32 (cm, b, b))
 871                   GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
 872                                             b, b);
 873             }
 874             break;
 875           default:
 876             engine_error (SD, CPU, cia,
 877                           "0x%lx: Invalid merge (%d)",
 878                           cia.ip, Source);
 879
 880           }
 881         TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
 882 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
 883         do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate);
 884 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
 885         do_shift (_SD, Dest, Source, Merge, i, n, EndMask, GPR (RotReg) & 31);
 886
 887
 888 // sli.{d|e|i}{m|s|z} - see shift
 889
 890
 891 // sr.{d|e|i}{m|s|z} - see shift
 892
 893
 894 // sra - see sr.es - see shift
 895
 896
 897 // sri.{d|e|i}{m|s|z} - see shift
 898
 899
 900 // srl - see sr.ez
 901
 902
 903 // st[{.b|.h|.d}]
 904 void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 905         unsigned32 addr;
 906         switch (sz)
 907           {
 908           case 0:
 909             addr = Base + (S ? (Offset << 0) : Offset);
 910             STORE (addr, 1, GPR(Source));
 911             break;
 912           case 1:
 913             addr = Base + (S ? (Offset << 1) : Offset);
 914             STORE (addr, 2, GPR(Source));
 915             break;
 916           case 2:
 917             addr = Base + (S ? (Offset << 2) : Offset);
 918             STORE (addr, 4, GPR(Source));
 919             break;
 920           case 3:
 921             {
 922               signed64 val;
 923               if (Source & 0x1)
 924                 engine_error (SD, CPU, cia,
 925                               "0x%lx: st.d with odd source register %d",
 926                               cia.ip, Source);
 927               addr = Base + (S ? (Offset << 3) : Offset);
 928               val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
 929               STORE (addr, 8, val);
 930             }
 931             break;
 932           default:
 933             addr = -1;
 934             engine_error (SD, CPU, cia, "st - invalid sz %d", sz);
 935           }
 936         if (m)
 937           *rBase = addr;
 938         TRACE_ST (MY_INDEX, Source, m, S, Base, Offset);
 939 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
 940         do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
 941 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
 942         do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
 943 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
 944         long_immediate (LongSignedImmediateOffset);
 945         do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
 946
 947
 948 // sub
 949 void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
 950         ALU_BEGIN (Source1);
 951         ALU_SUB (Source2);
 952         ALU_END (*rDest);
 953         TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
 954 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
 955         do_sub (_SD, rDest, vSource1, rSource2);
 956 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
 957         do_sub (_SD, rDest, rSource1, rSource2);
 958 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
 959         long_immediate (LongSignedImmediate);
 960         do_sub (_SD, rDest, LongSignedImmediate, rSource2);
 961
 962
 963 // subu
 964 void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
 965         unsigned32 result = Source1 - Source2;
 966         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
 967         *rDest = result;
 968 // NOTE - the book has 15.1 which conflicts with subu.
 969 31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i
 970         do_subu (_SD, rDest, vSource1, rSource2);
 971 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
 972         do_subu (_SD, rDest, rSource1, rSource2);
 973 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
 974         long_immediate (LongSignedImmediate);
 975         do_subu (_SD, rDest, LongSignedImmediate, rSource2);
 976
 977
 978 // swcr
 979 void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
 980         tic80_control_regs reg = tic80_index2cr (cr);
 981         /* cache the old CR value */
 982         unsigned32 old_cr = CR (cr);
 983         /* Handle the write if allowed */
 984         if (cr >= 0x4000 || !(CPU)->is_user_mode)
 985           switch (reg)
 986             {
 987             case INTPEN_CR:
 988               CR (cr) &= ~rSource;
 989               break;
 990             default:
 991               CR (cr) = rSource;
 992               break;
 993             }
 994         /* Finish off the read */
 995         GPR (Dest) = old_cr;
 996         TRACE_SINK3 (MY_INDEX, rSource, cr, Dest);
 997 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
 998         do_swcr (_SD, Dest, rSource, UCRN);
 999 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
1000         do_swcr (_SD, Dest, rSource, UCRN);
1001 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
1002         long_immediate (LongUnsignedControlRegister);
1003         do_swcr (_SD, Dest, rSource, LongUnsignedControlRegister);
1004
1005
1006 // trap
1007 void::function::do_trap:unsigned32 trap_number
1008         TRACE_SINK1 (MY_INDEX, trap_number);
1009         switch (trap_number)
1010           {
1011           case 72:
1012             switch (GPR(15))
1013               {
1014               case 1: /* EXIT */
1015                 {
1016                   engine_halt (SD, CPU, cia, sim_exited, GPR(2));
1017                   break;
1018                 }
1019               case 4: /* WRITE */
1020                 {
1021                   int i;
1022                   if (GPR(2) == 1)
1023                     for (i = 0; i < GPR(6); i++)
1024                       {
1025                         char c;
1026                         c = MEM (unsigned, GPR(4) + i, 1);
1027                         sim_io_write_stdout (SD, &c, 1);
1028                       }
1029                   else if (GPR(2) == 2)
1030                     for (i = 0; i < GPR(6); i++)
1031                       {
1032                         char c;
1033                         c = MEM (unsigned, GPR(4) + i, 1);
1034                         sim_io_write_stderr (SD, &c, 1);
1035                       }
1036                   else
1037                     engine_error (SD, CPU, cia,
1038                                   "0x%lx: write to invalid fid %d",
1039                                   (unsigned long) cia.ip, GPR(2));
1040                   GPR(2) = GPR(6);
1041                   break;
1042                 }
1043               default:
1044                 engine_error (SD, CPU, cia,
1045                               "0x%lx: unknown syscall %d",
1046                               (unsigned long) cia.ip, GPR(15));
1047               }
1048             break;
1049           case 73:
1050             engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP);
1051           default:
1052             engine_error (SD, CPU, cia,
1053                           "0x%lx: unsupported trap %d",
1054                           (unsigned long) cia.ip, trap_number);
1055           }
1056 31./,27.0,26./,21.0b0000001,14.UTN::::trap i
1057         do_trap (_SD, UTN);
1058 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
1059         do_trap (_SD, UTN);
1060 31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
1061         long_immediate (UTN);
1062         do_trap (_SD, UTN);
1063
1064
1065 // vadd.{s|d}{s|d}
1066 31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r
1067 31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l
1068
1069
1070 // vld{0|1}.{s|d} - see above - same instruction
1071 #31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld
1072
1073
1074 // vmac.ss{s|d}
1075 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra
1076 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr
1077 #31.*,   26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia
1078 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir
1079
1080
1081 // vmpy.{s|d}{s|d}
1082 31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r
1083 31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l
1084
1085
1086 // vmsc.ss{s|d}
1087 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra
1088 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr
1089 #31.*,   26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia
1090 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir
1091
1092
1093 // vmsub.{s|d}{s|d}
1094 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r
1095 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l
1096
1097
1098 // vrnd.{s|d}{s|d}
1099 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r
1100 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l
1101
1102
1103 // vrnd.{i|u}{s|d}
1104 31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r
1105 31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l
1106
1107
1108 // vst.{s|d} - see above - same instruction
1109 #31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst
1110
1111
1112 // vsub.{i|u}{s|d}
1113 31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r
1114 31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l
1115
1116
1117 // wrcr - see swcr, creg, source, r0
1118
1119
1120 // xnor
1121 void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2
1122         unsigned32 result = ~ (Source1 ^ Source2);
1123         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
1124         *rDest = result;
1125 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
1126         do_xnor (_SD, rDest, vSource1, rSource2);
1127 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
1128         do_xnor (_SD, rDest, rSource1, rSource2);
1129 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
1130         long_immediate (LongUnsignedImmediate);
1131         do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2);
1132
1133
1134 // xor
1135 void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2
1136         unsigned32 result = Source1 ^ Source2;
1137         TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
1138         *rDest = result;
1139 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
1140         do_xor (_SD, rDest, vSource1, rSource2);
1141 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
1142         do_xor (_SD, rDest, rSource1, rSource2);
1143 31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l
1144         long_immediate (LongUnsignedImmediate);
1145         do_xor (_SD, rDest, LongUnsignedImmediate, rSource2);