2 cache:Dest:rDest:signed_word *:(&(CPU)->reg[Dest])
5 cache:Source1:vSource1:signed_word:(GPR (Source1) + 0)
6 #cache:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1])
9 cache:Source2:vSource2:signed_word:(GPR (Source2) + 0)
10 #cache:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2])
13 cache:Source:vSource:signed_word:(GPR (Source) + 0)
14 #cache:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source])
17 cache:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0)
18 #cache:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])
21 cache:Base:vBase:signed_word:(GPR (Base) + 0)
22 cache:Base:rBase:signed_word*:(&GPR (Base))
23 #cache:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base])
26 cache:Link:rLink:signed_word*:(&(CPU)->reg[Link])
31 cache:INDTR:UTN:unsigned_word:(INDTR == 0 ? 0 : (CPU)->reg[INDTR])
35 cache:SignedImmediate:SignedImmediate:
36 cache:SignedImmediate:vSource1:signed_word:SEXT (SignedImmediate, 14)
38 cache:UnsignedImmediate:UnsignedImmediate:
39 cache:UnsignedImmediate:vSource1:signed_word:UnsignedImmediate
43 cache:BITNUM:bitnum:int:(~BITNUM) & 0x1f
46 cache:SignedOffset:SignedOffset:
47 cache:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14)
51 cache:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0)
52 #cache:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])