sim/v850/ChangeLog

   1 Thu Oct 24 12:26:35 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c (OP_500): Fix displacement handling for sld.w.
   4         (OP_501): Similarly for sst.w.
   5
   6         * simops.c (trace_input): Remove all references to SEXT7.
   7         (OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
   8         is zero extended for sst/sld instructions.
   9         * v850_sim.h (SEX7): Delete.  It's no longer needed (and it
  10         was incorrect anyway).
  11
  12 Thu Oct 24 10:33:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
  13
  14         * Makefile.in:  Get rid of srcroot.  Set all INSTALL macros via
  15         autoconf.
  16         * gencode.c (write_opcodes):  Pad operands field to account for
  17         MSVC braindamage.
  18         * simops.c:  Include errno.h.  Exclude SYS_chown, since MSVC
  19         doesn't support it.  (Why is this here in the first place?!?)
  20         * v850_sim.h:  Get rid of 64 bit defs.  Also, get rid of #elif's.
  21         Change number of operands in struct simops from 9 to 6.  Define
  22         SIGTRAP and SIGQUIT for MSVC.
  23
  24 Tue Oct 15 16:19:51 1996  Stu Grossman  (grossman@critters.cygnus.com)
  25
  26         * interp.c (MEM_SIZE):  It's now bytes, not a power of 2.
  27         * (map):  Add support for external mem in the 1->2 meg range.
  28         Also, abort() when memory access is way out of bounds.  (Better to
  29         die than to give wrong result.  (This will be fixed later.))
  30         * (sim_size):  MEM_SIZE is now bytes, not shift factor.
  31
  32 Tue Oct  1 15:53:24 1996  Gavin Koch <gavin@cygnus.com>
  33
  34         * simops.c (trace_input): Swapped order of operands for output
  35         output of OP_IMM_REG.  Changed the fetching of the operands for
  36         OP_LOAD32, and OP_STORE32 to work like op-function.
  37
  38 Mon Sep 30 15:46:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
  39
  40         * interp.c:  Move includes of remote-sim.h and callback.h to
  41         v850-sim.h.
  42         * (lookup_hash): Add PC to report of hash failure.
  43         * (map load_mem store_mem):  New memory subsystem.  Models V851
  44         memory system.
  45         * (sim_write sim_read):  Use new memory subsystem.
  46         * (sim_resume):  Don't load and save PC into EIPC anymore.  Needed
  47         to make user-defined traps work right.
  48         * simops.c (OP_*):  Use new memory subsystem.
  49         * (OP_14007E0 (reti)):  Implement reti.
  50         * (OP_14996E0 (trap)):  Implement user-defined traps.  Move I/O to
  51         trap 31.  Use new memory subsystem.
  52         * v850_sim.h:  Prototypes for load_mem, store_mem and map.  Use
  53         load_mem in RLW macro.
  54
  55 Fri Sep 27 18:34:09 1996  Stu Grossman  (grossman@critters.cygnus.com)
  56
  57         * gencode.c (write_opcodes):  Output hex values for opcode mask
  58         and patterns.
  59         * interp.c (sim_resume):  Save and restore PC from the appropriate
  60         register.
  61         * (sim_fetch_register sim_store_register):  Fix byte-order problem
  62         with reading and writing registers.
  63         * simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.
  64
  65 Fri Sep 27 17:42:37 1996  Jeffrey A Law  (law@cygnus.com)
  66
  67         * simops.c (trace_input): Fix thinko.
  68
  69 Wed Sep 18 09:54:12 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  70
  71         * simops.c (exec_bfd): Rename from sim_bfd.
  72         (trace_input): Ditto.
  73
  74 Thu Sep 12 12:03:05 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  75
  76         * simops.c (trace_input): Use find_nearest_line to print line
  77         number, function name or file name of PC.
  78
  79 Wed Sep 11 16:44:37 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  80
  81         * simops.c: Add tracing support.  Use SEXTxx macros instead of
  82         doing hardwired shifts.
  83
  84         * configure.in (--enable-sim-cflags): Add switch to add additional
  85         flags to simulator buld.  If --enable-sim-cflags=trace, turn on
  86         tracing.
  87         * configure: Regenerate.
  88
  89         * Makefile.in: Don't require a VPATH capable make if configuring
  90         in the same directory.  Don't use CFLAGS for configuration flags.
  91         Add flags from --enable-sim-cflags.  Support canadian cross
  92         builds.  Rebuild whole simulator if include files change.
  93
  94         * interp.c (v850_debug): New global for debugging.
  95         (lookup_hash,sim_size,sim_set_profile): Use
  96         printf_filtered callback, instead of calling printf directly.
  97         (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
  98
  99         * v850_sim.h: Use limits.h to set the various sized types.
 100         (SEXT{5,7,16,22}): New macros.
 101
 102 Mon Sep  9 20:50:46 1996  Jeffrey A Law  (law@cygnus.com)
 103
 104         * interp.c (hash): Make this an inline function
 105         when compiling with GCC.  Simplify.
 106         * simpos.c: Explicitly include "sys/syscall.h".  Remove
 107         some #if 0'd code.  Enable more emulated syscalls.
 108
 109 Wed Sep  4 01:48:55 1996  Jeffrey A Law  (law@cygnus.com)
 110
 111         * interp.c: Fix sign bit handling for add and sub instructions.
 112
 113 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
 114
 115         * gencode.c: Fix various indention & style problems.
 116         Remove test code.  Remove #if 0 code.
 117         * interp.c: Provide prototypes for all static functions.
 118         Fix minor indention problems.
 119         (sim_open, sim_resume): Remove unused variables.
 120         (sim_read): Return type is "int".
 121         * simops.c: Remove unused variables.
 122         (divh): Make result of divide-by-zero zero.
 123         (setf): Initialize result to keep compiler quiet.
 124         (sar instructions): These just clear the overflow bit.
 125         * v850_sim.h: Provide prototypes for put_byte, put_half
 126         and put_word.
 127
 128         * interp.c: OP should be an array of 32bit operands!
 129         (v850_callback): Declare.
 130         (do_format_5): Fix extraction of OP[0].
 131         (sim_size): Remove debugging printf.
 132         (sim_set_callbacks): Do something useful.
 133         (sim_stop_reason): Gross hacks to get c-torture running.
 134         * simops.c: Simplify code for computing targets of bCC
 135         insns.   Invert 's' bit if 'ov' bit is set for some
 136         instructions.  Fix 'cy' bit handling for numerous
 137         instructions.  Make the simulator stop when a halt
 138         instruction is encountered.  Very crude support for
 139         emulated syscalls (trap 0).
 140         * v850_sim.h: Include "callback.h" and declare
 141         v850_callback.  Items in the operand array are 32bits.
 142
 143 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
 144
 145         * interp.c (sim_resume): Fix code to check for a format 3
 146         opcode.
 147         * simops.c: bCC insns only argument is a constant, not a
 148         register value (duh...)
 149
 150 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
 151
 152         * simops.c: Fix "not1" and "set1".
 153
 154         * simops.c: Don't forget to initialize temp for
 155         "ld.h" and "ld.w"
 156
 157         * interp.c: Remove various debugging printfs.
 158
 159         * simops.c: Fix satadd, satsub boundary case handling.
 160
 161         * interp.c (hash): Fix.
 162         * interp.c (do_format_8): Get operands correctly and
 163         call the target function.
 164         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
 165
 166 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 167
 168         * interp.c (do_format_4): Get operands correctly and
 169         call the target function.
 170         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
 171         "sst.h", and "sst.w".
 172
 173         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
 174         accordingly.  Remove many unused definitions.
 175         * interp.c: The V850 doesn't have split I&D spaces.  Change
 176         accordingly.
 177         (get_longlong, get_longword, get_word): Deleted.
 178         (write_longlong, write_longword, write_word): Deleted.
 179         (get_operands): Deleted.
 180         (get_byte, get_half, get_word): New functions.
 181         (put_byte, put_half, put_word): New functions.
 182         * simops.c: Remove unused functions.  Rough cut at
 183         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
 184
 185         * v850_sim.h (struct _state): Remove "psw" field.  Add
 186         "sregs" field.
 187         (PSW): Remove bogus definition.
 188         * simops.c: Change condition code handling to use the psw
 189         register within the sregs array.  Handle "ldsr" and "stsr".
 190
 191         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
 192
 193         * interp.c (do_format_5): Get operands correctly and
 194         call the target function.
 195         (sim_resume): Don't do a PC update for format 5 instructions.
 196         * simops.c: Handle "jarl" and "jmp" instructions.
 197
 198         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
 199         "di", and "ei" instructions correctly.
 200
 201         * interp.c (do_format_3): Get operands correctly and call
 202         the target function.
 203         * simops.c: Handle bCC instructions.
 204
 205         * simops.c: Add condition code handling to shift insns.
 206         Fix minor typos in condition code handling for other insns.
 207
 208         * Makefile.in: Fix typo.
 209         * simops.c: Add condition code handling to "sub" "subr" and
 210         "divh" instructions.
 211
 212         * interp.c (hash): Update to be more accurate.
 213         (lookup_hash): Call hash rather than computing the hash
 214         code here.
 215         (do_format_1_2): Handle format 1 and format 2 instructions.
 216         Get operands correctly and call the target function.
 217         (do_format_6): Get operands correctly and call the target
 218         function.
 219         (do_formats_9_10): Rough cut so shift ops will work.
 220         (sim_resume): Tweak to deal with format 1 and format 2
 221         handling in a single funtion.  Don't update the PC
 222         for format 3 insns.  Fix typos.
 223         * simops.c: Slightly reorganize.  Add condition code handling
 224         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 225         and "not" instructions.
 226         * v850_sim.h (reg_t): Registers are 32bits.
 227         (_state): The V850 has 32 general registers.  Add a 32bit
 228         psw and pc register too.  Add accessor macros
 229
 230         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 231         changes from the d10v simulator.
 232
 233         * simops.c: Add shift support.
 234
 235         * simops.c: Add multiply & divide support.  Abort for system
 236         instructions.
 237
 238         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 239         and subr.  No condition codes yet.
 240
 241 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 242
 243         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 244         gencode.c, interp.c, simops.c: Created.
 245