1 Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com)
3 * simops.c: Fix satadd, satsub boundary case handling.
5 * interp.c (hash): Fix.
6 * interp.c (do_format_8): Get operands correctly and
7 call the target function.
8 * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
10 Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
12 * interp.c (do_format_4): Get operands correctly and
13 call the target function.
14 * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
17 * v850_sim.h: The V850 doesn't have split I&D spaces. Change
18 accordingly. Remove many unused definitions.
19 * interp.c: The V850 doesn't have split I&D spaces. Change
21 (get_longlong, get_longword, get_word): Deleted.
22 (write_longlong, write_longword, write_word): Deleted.
23 (get_operands): Deleted.
24 (get_byte, get_half, get_word): New functions.
25 (put_byte, put_half, put_word): New functions.
26 * simops.c: Remove unused functions. Rough cut at
27 "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
29 * v850_sim.h (struct _state): Remove "psw" field. Add
31 (PSW): Remove bogus definition.
32 * simops.c: Change condition code handling to use the psw
33 register within the sregs array. Handle "ldsr" and "stsr".
35 * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
37 * interp.c (do_format_5): Get operands correctly and
38 call the target function.
39 (sim_resume): Don't do a PC update for format 5 instructions.
40 * simops.c: Handle "jarl" and "jmp" instructions.
42 * simops.c: Fix minor typos. Handle "cmp", "setf", "tst"
43 "di", and "ei" instructions correctly.
45 * interp.c (do_format_3): Get operands correctly and call
47 * simops.c: Handle bCC instructions.
49 * simops.c: Add condition code handling to shift insns.
50 Fix minor typos in condition code handling for other insns.
52 * Makefile.in: Fix typo.
53 * simops.c: Add condition code handling to "sub" "subr" and
56 * interp.c (hash): Update to be more accurate.
57 (lookup_hash): Call hash rather than computing the hash
59 (do_format_1_2): Handle format 1 and format 2 instructions.
60 Get operands correctly and call the target function.
61 (do_format_6): Get operands correctly and call the target
63 (do_formats_9_10): Rough cut so shift ops will work.
64 (sim_resume): Tweak to deal with format 1 and format 2
65 handling in a single funtion. Don't update the PC
66 for format 3 insns. Fix typos.
67 * simops.c: Slightly reorganize. Add condition code handling
68 to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
69 and "not" instructions.
70 * v850_sim.h (reg_t): Registers are 32bits.
71 (_state): The V850 has 32 general registers. Add a 32bit
72 psw and pc register too. Add accessor macros
74 * Makefile.in, interp.c, v850_sim.h: Bring over endianness
75 changes from the d10v simulator.
77 * simops.c: Add shift support.
79 * simops.c: Add multiply & divide support. Abort for system
82 * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
83 and subr. No condition codes yet.
85 Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com)
87 * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
88 gencode.c, interp.c, simops.c: Created.