sim/v850/ChangeLog

   1 Thu Sep 12 12:03:05 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
   2
   3         * simops.c (trace_input): Use find_nearest_line to print line
   4         number, function name or file name of PC.
   5
   6 Wed Sep 11 16:44:37 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
   7
   8         * simops.c: Add tracing support.  Use SEXTxx macros instead of
   9         doing hardwired shifts.
  10
  11         * configure.in (--enable-sim-cflags): Add switch to add additional
  12         flags to simulator buld.  If --enable-sim-cflags=trace, turn on
  13         tracing.
  14         * configure: Regenerate.
  15
  16         * Makefile.in: Don't require a VPATH capable make if configuring
  17         in the same directory.  Don't use CFLAGS for configuration flags.
  18         Add flags from --enable-sim-cflags.  Support canadian cross
  19         builds.  Rebuild whole simulator if include files change.
  20
  21         * interp.c (v850_debug): New global for debugging.
  22         (lookup_hash,sim_size,sim_set_profile): Use
  23         printf_filtered callback, instead of calling printf directly.
  24         (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
  25
  26         * v850_sim.h: Use limits.h to set the various sized types.
  27         (SEXT{5,7,16,22}): New macros.
  28
  29 Mon Sep  9 20:50:46 1996  Jeffrey A Law  (law@cygnus.com)
  30
  31         * interp.c (hash): Make this an inline function
  32         when compiling with GCC.  Simplify.
  33         * simpos.c: Explicitly include "sys/syscall.h".  Remove
  34         some #if 0'd code.  Enable more emulated syscalls.
  35
  36 Wed Sep  4 01:48:55 1996  Jeffrey A Law  (law@cygnus.com)
  37
  38         * interp.c: Fix sign bit handling for add and sub instructions.
  39
  40 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
  41
  42         * gencode.c: Fix various indention & style problems.
  43         Remove test code.  Remove #if 0 code.
  44         * interp.c: Provide prototypes for all static functions.
  45         Fix minor indention problems.
  46         (sim_open, sim_resume): Remove unused variables.
  47         (sim_read): Return type is "int".
  48         * simops.c: Remove unused variables.
  49         (divh): Make result of divide-by-zero zero.
  50         (setf): Initialize result to keep compiler quiet.
  51         (sar instructions): These just clear the overflow bit.
  52         * v850_sim.h: Provide prototypes for put_byte, put_half
  53         and put_word.
  54
  55         * interp.c: OP should be an array of 32bit operands!
  56         (v850_callback): Declare.
  57         (do_format_5): Fix extraction of OP[0].
  58         (sim_size): Remove debugging printf.
  59         (sim_set_callbacks): Do something useful.
  60         (sim_stop_reason): Gross hacks to get c-torture running.
  61         * simops.c: Simplify code for computing targets of bCC
  62         insns.   Invert 's' bit if 'ov' bit is set for some
  63         instructions.  Fix 'cy' bit handling for numerous
  64         instructions.  Make the simulator stop when a halt
  65         instruction is encountered.  Very crude support for
  66         emulated syscalls (trap 0).
  67         * v850_sim.h: Include "callback.h" and declare
  68         v850_callback.  Items in the operand array are 32bits.
  69
  70 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
  71
  72         * interp.c (sim_resume): Fix code to check for a format 3
  73         opcode.
  74         * simops.c: bCC insns only argument is a constant, not a
  75         register value (duh...)
  76
  77 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
  78
  79         * simops.c: Fix "not1" and "set1".
  80
  81         * simops.c: Don't forget to initialize temp for
  82         "ld.h" and "ld.w"
  83
  84         * interp.c: Remove various debugging printfs.
  85
  86         * simops.c: Fix satadd, satsub boundary case handling.
  87
  88         * interp.c (hash): Fix.
  89         * interp.c (do_format_8): Get operands correctly and
  90         call the target function.
  91         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
  92
  93 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
  94
  95         * interp.c (do_format_4): Get operands correctly and
  96         call the target function.
  97         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
  98         "sst.h", and "sst.w".
  99
 100         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
 101         accordingly.  Remove many unused definitions.
 102         * interp.c: The V850 doesn't have split I&D spaces.  Change
 103         accordingly.
 104         (get_longlong, get_longword, get_word): Deleted.
 105         (write_longlong, write_longword, write_word): Deleted.
 106         (get_operands): Deleted.
 107         (get_byte, get_half, get_word): New functions.
 108         (put_byte, put_half, put_word): New functions.
 109         * simops.c: Remove unused functions.  Rough cut at
 110         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
 111
 112         * v850_sim.h (struct _state): Remove "psw" field.  Add
 113         "sregs" field.
 114         (PSW): Remove bogus definition.
 115         * simops.c: Change condition code handling to use the psw
 116         register within the sregs array.  Handle "ldsr" and "stsr".
 117
 118         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
 119
 120         * interp.c (do_format_5): Get operands correctly and
 121         call the target function.
 122         (sim_resume): Don't do a PC update for format 5 instructions.
 123         * simops.c: Handle "jarl" and "jmp" instructions.
 124
 125         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
 126         "di", and "ei" instructions correctly.
 127
 128         * interp.c (do_format_3): Get operands correctly and call
 129         the target function.
 130         * simops.c: Handle bCC instructions.
 131
 132         * simops.c: Add condition code handling to shift insns.
 133         Fix minor typos in condition code handling for other insns.
 134
 135         * Makefile.in: Fix typo.
 136         * simops.c: Add condition code handling to "sub" "subr" and
 137         "divh" instructions.
 138
 139         * interp.c (hash): Update to be more accurate.
 140         (lookup_hash): Call hash rather than computing the hash
 141         code here.
 142         (do_format_1_2): Handle format 1 and format 2 instructions.
 143         Get operands correctly and call the target function.
 144         (do_format_6): Get operands correctly and call the target
 145         function.
 146         (do_formats_9_10): Rough cut so shift ops will work.
 147         (sim_resume): Tweak to deal with format 1 and format 2
 148         handling in a single funtion.  Don't update the PC
 149         for format 3 insns.  Fix typos.
 150         * simops.c: Slightly reorganize.  Add condition code handling
 151         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 152         and "not" instructions.
 153         * v850_sim.h (reg_t): Registers are 32bits.
 154         (_state): The V850 has 32 general registers.  Add a 32bit
 155         psw and pc register too.  Add accessor macros
 156
 157         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 158         changes from the d10v simulator.
 159
 160         * simops.c: Add shift support.
 161
 162         * simops.c: Add multiply & divide support.  Abort for system
 163         instructions.
 164
 165         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 166         and subr.  No condition codes yet.
 167
 168 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 169
 170         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 171         gencode.c, interp.c, simops.c: Created.
 172