sim/v850/ChangeLog

   1 Tue Oct 15 16:19:51 1996  Stu Grossman  (grossman@critters.cygnus.com)
   2
   3         * interp.c (MEM_SIZE):  It's now bytes, not a power of 2.
   4         * (map):  Add support for external mem in the 1->2 meg range.
   5         Also, abort() when memory access is way out of bounds.  (Better to
   6         die than to give wrong result.  (This will be fixed later.))
   7         * (sim_size):  MEM_SIZE is now bytes, not shift factor.
   8
   9 Tue Oct  1 15:53:24 1996  Gavin Koch <gavin@cygnus.com>
  10
  11         * simops.c (trace_input): Swapped order of operands for output
  12         output of OP_IMM_REG.  Changed the fetching of the operands for
  13         OP_LOAD32, and OP_STORE32 to work like op-function.
  14
  15 Mon Sep 30 15:46:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
  16
  17         * interp.c:  Move includes of remote-sim.h and callback.h to
  18         v850-sim.h.
  19         * (lookup_hash): Add PC to report of hash failure.
  20         * (map load_mem store_mem):  New memory subsystem.  Models V851
  21         memory system.
  22         * (sim_write sim_read):  Use new memory subsystem.
  23         * (sim_resume):  Don't load and save PC into EIPC anymore.  Needed
  24         to make user-defined traps work right.
  25         * simops.c (OP_*):  Use new memory subsystem.
  26         * (OP_14007E0 (reti)):  Implement reti.
  27         * (OP_14996E0 (trap)):  Implement user-defined traps.  Move I/O to
  28         trap 31.  Use new memory subsystem.
  29         * v850_sim.h:  Prototypes for load_mem, store_mem and map.  Use
  30         load_mem in RLW macro.
  31
  32 Fri Sep 27 18:34:09 1996  Stu Grossman  (grossman@critters.cygnus.com)
  33
  34         * gencode.c (write_opcodes):  Output hex values for opcode mask
  35         and patterns.
  36         * interp.c (sim_resume):  Save and restore PC from the appropriate
  37         register.
  38         * (sim_fetch_register sim_store_register):  Fix byte-order problem
  39         with reading and writing registers.
  40         * simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.
  41
  42 Fri Sep 27 17:42:37 1996  Jeffrey A Law  (law@cygnus.com)
  43
  44         * simops.c (trace_input): Fix thinko.
  45
  46 Wed Sep 18 09:54:12 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  47
  48         * simops.c (exec_bfd): Rename from sim_bfd.
  49         (trace_input): Ditto.
  50
  51 Thu Sep 12 12:03:05 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  52
  53         * simops.c (trace_input): Use find_nearest_line to print line
  54         number, function name or file name of PC.
  55
  56 Wed Sep 11 16:44:37 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  57
  58         * simops.c: Add tracing support.  Use SEXTxx macros instead of
  59         doing hardwired shifts.
  60
  61         * configure.in (--enable-sim-cflags): Add switch to add additional
  62         flags to simulator buld.  If --enable-sim-cflags=trace, turn on
  63         tracing.
  64         * configure: Regenerate.
  65
  66         * Makefile.in: Don't require a VPATH capable make if configuring
  67         in the same directory.  Don't use CFLAGS for configuration flags.
  68         Add flags from --enable-sim-cflags.  Support canadian cross
  69         builds.  Rebuild whole simulator if include files change.
  70
  71         * interp.c (v850_debug): New global for debugging.
  72         (lookup_hash,sim_size,sim_set_profile): Use
  73         printf_filtered callback, instead of calling printf directly.
  74         (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
  75
  76         * v850_sim.h: Use limits.h to set the various sized types.
  77         (SEXT{5,7,16,22}): New macros.
  78
  79 Mon Sep  9 20:50:46 1996  Jeffrey A Law  (law@cygnus.com)
  80
  81         * interp.c (hash): Make this an inline function
  82         when compiling with GCC.  Simplify.
  83         * simpos.c: Explicitly include "sys/syscall.h".  Remove
  84         some #if 0'd code.  Enable more emulated syscalls.
  85
  86 Wed Sep  4 01:48:55 1996  Jeffrey A Law  (law@cygnus.com)
  87
  88         * interp.c: Fix sign bit handling for add and sub instructions.
  89
  90 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
  91
  92         * gencode.c: Fix various indention & style problems.
  93         Remove test code.  Remove #if 0 code.
  94         * interp.c: Provide prototypes for all static functions.
  95         Fix minor indention problems.
  96         (sim_open, sim_resume): Remove unused variables.
  97         (sim_read): Return type is "int".
  98         * simops.c: Remove unused variables.
  99         (divh): Make result of divide-by-zero zero.
 100         (setf): Initialize result to keep compiler quiet.
 101         (sar instructions): These just clear the overflow bit.
 102         * v850_sim.h: Provide prototypes for put_byte, put_half
 103         and put_word.
 104
 105         * interp.c: OP should be an array of 32bit operands!
 106         (v850_callback): Declare.
 107         (do_format_5): Fix extraction of OP[0].
 108         (sim_size): Remove debugging printf.
 109         (sim_set_callbacks): Do something useful.
 110         (sim_stop_reason): Gross hacks to get c-torture running.
 111         * simops.c: Simplify code for computing targets of bCC
 112         insns.   Invert 's' bit if 'ov' bit is set for some
 113         instructions.  Fix 'cy' bit handling for numerous
 114         instructions.  Make the simulator stop when a halt
 115         instruction is encountered.  Very crude support for
 116         emulated syscalls (trap 0).
 117         * v850_sim.h: Include "callback.h" and declare
 118         v850_callback.  Items in the operand array are 32bits.
 119
 120 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
 121
 122         * interp.c (sim_resume): Fix code to check for a format 3
 123         opcode.
 124         * simops.c: bCC insns only argument is a constant, not a
 125         register value (duh...)
 126
 127 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
 128
 129         * simops.c: Fix "not1" and "set1".
 130
 131         * simops.c: Don't forget to initialize temp for
 132         "ld.h" and "ld.w"
 133
 134         * interp.c: Remove various debugging printfs.
 135
 136         * simops.c: Fix satadd, satsub boundary case handling.
 137
 138         * interp.c (hash): Fix.
 139         * interp.c (do_format_8): Get operands correctly and
 140         call the target function.
 141         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
 142
 143 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 144
 145         * interp.c (do_format_4): Get operands correctly and
 146         call the target function.
 147         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
 148         "sst.h", and "sst.w".
 149
 150         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
 151         accordingly.  Remove many unused definitions.
 152         * interp.c: The V850 doesn't have split I&D spaces.  Change
 153         accordingly.
 154         (get_longlong, get_longword, get_word): Deleted.
 155         (write_longlong, write_longword, write_word): Deleted.
 156         (get_operands): Deleted.
 157         (get_byte, get_half, get_word): New functions.
 158         (put_byte, put_half, put_word): New functions.
 159         * simops.c: Remove unused functions.  Rough cut at
 160         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
 161
 162         * v850_sim.h (struct _state): Remove "psw" field.  Add
 163         "sregs" field.
 164         (PSW): Remove bogus definition.
 165         * simops.c: Change condition code handling to use the psw
 166         register within the sregs array.  Handle "ldsr" and "stsr".
 167
 168         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
 169
 170         * interp.c (do_format_5): Get operands correctly and
 171         call the target function.
 172         (sim_resume): Don't do a PC update for format 5 instructions.
 173         * simops.c: Handle "jarl" and "jmp" instructions.
 174
 175         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
 176         "di", and "ei" instructions correctly.
 177
 178         * interp.c (do_format_3): Get operands correctly and call
 179         the target function.
 180         * simops.c: Handle bCC instructions.
 181
 182         * simops.c: Add condition code handling to shift insns.
 183         Fix minor typos in condition code handling for other insns.
 184
 185         * Makefile.in: Fix typo.
 186         * simops.c: Add condition code handling to "sub" "subr" and
 187         "divh" instructions.
 188
 189         * interp.c (hash): Update to be more accurate.
 190         (lookup_hash): Call hash rather than computing the hash
 191         code here.
 192         (do_format_1_2): Handle format 1 and format 2 instructions.
 193         Get operands correctly and call the target function.
 194         (do_format_6): Get operands correctly and call the target
 195         function.
 196         (do_formats_9_10): Rough cut so shift ops will work.
 197         (sim_resume): Tweak to deal with format 1 and format 2
 198         handling in a single funtion.  Don't update the PC
 199         for format 3 insns.  Fix typos.
 200         * simops.c: Slightly reorganize.  Add condition code handling
 201         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 202         and "not" instructions.
 203         * v850_sim.h (reg_t): Registers are 32bits.
 204         (_state): The V850 has 32 general registers.  Add a 32bit
 205         psw and pc register too.  Add accessor macros
 206
 207         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 208         changes from the d10v simulator.
 209
 210         * simops.c: Add shift support.
 211
 212         * simops.c: Add multiply & divide support.  Abort for system
 213         instructions.
 214
 215         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 216         and subr.  No condition codes yet.
 217
 218 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 219
 220         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 221         gencode.c, interp.c, simops.c: Created.
 222