* configure configure.in Makefile.in: Update to new configure
[binutils-gdb.git] / sim / v850 / ChangeLog
1 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2
3 * configure configure.in Makefile.in: Update to new configure
4 scheme which is more compatible with WinGDB builds.
5 * configure.in: Improve comment on how to run autoconf.
6 * configure: Re-run autoconf to get new ../common/aclocal.m4.
7 * Makefile.in: Use autoconf substitution to install common
8 makefile fragment.
9
10 Mon Jan 20 16:05:34 1997 Michael Meissner <meissner@tiktok.cygnus.com>
11
12 * simops.c (OP_{E0,2E0,6E0}): The multiply operations sign extend,
13 not zero extend.
14
15 Tue Jan 14 17:06:03 1997 Stu Grossman (grossman@critters.cygnus.com)
16
17 * simops.c: Put ifdefs around things to make MSVC happy. Get rid
18 of unistd.h. Disable SYS_stat, SYS_chown, SYS_time, SYS_times,
19 SYS_gettimeofday and SYS_utime from MSVC.
20
21 Tue Dec 31 18:11:13 1996 Michael Meissner <meissner@tiktok.cygnus.com>
22
23 * simops.c (OP_10007E0): Know that kill encodes the signal number
24 via: 0xdead0000 | signal and turn it back into a signal.
25
26 Fri Dec 27 14:44:06 1996 Michael Meissner <meissner@tiktok.cygnus.com>
27
28 * v850_sim.h (SIG_V850_EXIT): Define as -1.
29
30 * interp.c (sim_open): Cast calloc function.
31 (sim_stop_reason): If signal is SIG_V850_EXIT, inform gdb the
32 program exited with the appropriate exit code.
33 (sim_set_interrupt): Declare buildargv.
34
35 * simops.c (OP_10007E0): Make exit signal normal exit. Make time
36 type correct and work on big endian systems.
37
38 Wed Nov 20 02:18:44 1996 Doug Evans <dje@canuck.cygnus.com>
39
40 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
41 (SIM_OBJS,SIM_EXTRA_CFLAGS,SIM_EXTRA_CLEAN): Define.
42 * configure.in: Simplify using macros in ../common/aclocal.m4.
43 Call AC_CHECK_HEADERS(unistd.h).
44 * configure: Regenerated.
45 * config.in: New file.
46 * simops.c: #include "config.h". #include <unistd.h> if present.
47
48 Sun Nov 3 23:02:54 1996 Stan Shebs <shebs@andros.cygnus.com>
49
50 * v850_sim.h (State): New slots dummy_mem, pending_nmi.
51 (EIPC, etc): New macros for system registers.
52 * simops.c, interp.c: Use everywhere.
53
54 * interp.c: Add support for interrupts issued by interrupt
55 generators, either PC- or time-based. Controlled by simulator
56 command "sim interrupt".
57
58 * interp.c: Add support for variable-size allocation of memory,
59 via simulator command "sim memory-map".
60 (map): Issue SIGSEGV for references to invalid memory regions.
61
62 Thu Oct 31 14:44:10 1996 Gavin Koch <gavin@cygnus.com>
63
64 * simops.c: Include <sys/time.h> for struct timeval and
65 struct timezone.
66
67 Wed Oct 30 08:49:10 1996 Jeffrey A Law (law@cygnus.com)
68
69 * simops.c (OP_10007E0): Handle SYS_times and SYS_gettimeofday.
70
71 * simops.c (OP_10007E0): Handle SYS_time.
72
73 Tue Oct 29 14:22:55 1996 Jeffrey A Law (law@cygnus.com)
74
75 * simops.c: Include <sys/stat.h>.
76 (OP_10007E0): Handle SYS_stat.
77
78 Thu Oct 24 12:26:35 1996 Jeffrey A Law (law@cygnus.com)
79
80 * simops.c (OP_10007E0): Don't declare errno.
81
82 * simops.c (OP_500): Mask off low bit in displacement
83 for sld.w.
84 (OP_501): Similarly.
85
86 * simops.c (OP_500): Fix displacement handling for sld.w.
87 (OP_501): Similarly for sst.w.
88
89 * simops.c (trace_input): Remove all references to SEXT7.
90 (OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
91 is zero extended for sst/sld instructions.
92 * v850_sim.h (SEX7): Delete. It's no longer needed (and it
93 was incorrect anyway).
94
95 Thu Oct 24 10:33:33 1996 Stu Grossman (grossman@critters.cygnus.com)
96
97 * Makefile.in: Get rid of srcroot. Set all INSTALL macros via
98 autoconf.
99 * gencode.c (write_opcodes): Pad operands field to account for
100 MSVC braindamage.
101 * simops.c: Include errno.h. Exclude SYS_chown, since MSVC
102 doesn't support it. (Why is this here in the first place?!?)
103 * v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's.
104 Change number of operands in struct simops from 9 to 6. Define
105 SIGTRAP and SIGQUIT for MSVC.
106
107 Tue Oct 15 16:19:51 1996 Stu Grossman (grossman@critters.cygnus.com)
108
109 * interp.c (MEM_SIZE): It's now bytes, not a power of 2.
110 * (map): Add support for external mem in the 1->2 meg range.
111 Also, abort() when memory access is way out of bounds. (Better to
112 die than to give wrong result. (This will be fixed later.))
113 * (sim_size): MEM_SIZE is now bytes, not shift factor.
114
115 Tue Oct 1 15:53:24 1996 Gavin Koch <gavin@cygnus.com>
116
117 * simops.c (trace_input): Swapped order of operands for output
118 output of OP_IMM_REG. Changed the fetching of the operands for
119 OP_LOAD32, and OP_STORE32 to work like op-function.
120
121 Mon Sep 30 15:46:33 1996 Stu Grossman (grossman@critters.cygnus.com)
122
123 * interp.c: Move includes of remote-sim.h and callback.h to
124 v850-sim.h.
125 * (lookup_hash): Add PC to report of hash failure.
126 * (map load_mem store_mem): New memory subsystem. Models V851
127 memory system.
128 * (sim_write sim_read): Use new memory subsystem.
129 * (sim_resume): Don't load and save PC into EIPC anymore. Needed
130 to make user-defined traps work right.
131 * simops.c (OP_*): Use new memory subsystem.
132 * (OP_14007E0 (reti)): Implement reti.
133 * (OP_14996E0 (trap)): Implement user-defined traps. Move I/O to
134 trap 31. Use new memory subsystem.
135 * v850_sim.h: Prototypes for load_mem, store_mem and map. Use
136 load_mem in RLW macro.
137
138 Fri Sep 27 18:34:09 1996 Stu Grossman (grossman@critters.cygnus.com)
139
140 * gencode.c (write_opcodes): Output hex values for opcode mask
141 and patterns.
142 * interp.c (sim_resume): Save and restore PC from the appropriate
143 register.
144 * (sim_fetch_register sim_store_register): Fix byte-order problem
145 with reading and writing registers.
146 * simops.c (OP_FFFF): Implement pseudo-breakpoint insn.
147
148 Fri Sep 27 17:42:37 1996 Jeffrey A Law (law@cygnus.com)
149
150 * simops.c (trace_input): Fix thinko.
151
152 Wed Sep 18 09:54:12 1996 Michael Meissner <meissner@tiktok.cygnus.com>
153
154 * simops.c (exec_bfd): Rename from sim_bfd.
155 (trace_input): Ditto.
156
157 Thu Sep 12 12:03:05 1996 Michael Meissner <meissner@tiktok.cygnus.com>
158
159 * simops.c (trace_input): Use find_nearest_line to print line
160 number, function name or file name of PC.
161
162 Wed Sep 11 16:44:37 1996 Michael Meissner <meissner@tiktok.cygnus.com>
163
164 * simops.c: Add tracing support. Use SEXTxx macros instead of
165 doing hardwired shifts.
166
167 * configure.in (--enable-sim-cflags): Add switch to add additional
168 flags to simulator buld. If --enable-sim-cflags=trace, turn on
169 tracing.
170 * configure: Regenerate.
171
172 * Makefile.in: Don't require a VPATH capable make if configuring
173 in the same directory. Don't use CFLAGS for configuration flags.
174 Add flags from --enable-sim-cflags. Support canadian cross
175 builds. Rebuild whole simulator if include files change.
176
177 * interp.c (v850_debug): New global for debugging.
178 (lookup_hash,sim_size,sim_set_profile): Use
179 printf_filtered callback, instead of calling printf directly.
180 (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
181
182 * v850_sim.h: Use limits.h to set the various sized types.
183 (SEXT{5,7,16,22}): New macros.
184
185 Mon Sep 9 20:50:46 1996 Jeffrey A Law (law@cygnus.com)
186
187 * interp.c (hash): Make this an inline function
188 when compiling with GCC. Simplify.
189 * simpos.c: Explicitly include "sys/syscall.h". Remove
190 some #if 0'd code. Enable more emulated syscalls.
191
192 Wed Sep 4 01:48:55 1996 Jeffrey A Law (law@cygnus.com)
193
194 * interp.c: Fix sign bit handling for add and sub instructions.
195
196 Tue Sep 3 10:20:30 1996 Jeffrey A Law (law@cygnus.com)
197
198 * gencode.c: Fix various indention & style problems.
199 Remove test code. Remove #if 0 code.
200 * interp.c: Provide prototypes for all static functions.
201 Fix minor indention problems.
202 (sim_open, sim_resume): Remove unused variables.
203 (sim_read): Return type is "int".
204 * simops.c: Remove unused variables.
205 (divh): Make result of divide-by-zero zero.
206 (setf): Initialize result to keep compiler quiet.
207 (sar instructions): These just clear the overflow bit.
208 * v850_sim.h: Provide prototypes for put_byte, put_half
209 and put_word.
210
211 * interp.c: OP should be an array of 32bit operands!
212 (v850_callback): Declare.
213 (do_format_5): Fix extraction of OP[0].
214 (sim_size): Remove debugging printf.
215 (sim_set_callbacks): Do something useful.
216 (sim_stop_reason): Gross hacks to get c-torture running.
217 * simops.c: Simplify code for computing targets of bCC
218 insns. Invert 's' bit if 'ov' bit is set for some
219 instructions. Fix 'cy' bit handling for numerous
220 instructions. Make the simulator stop when a halt
221 instruction is encountered. Very crude support for
222 emulated syscalls (trap 0).
223 * v850_sim.h: Include "callback.h" and declare
224 v850_callback. Items in the operand array are 32bits.
225
226 Sun Sep 1 22:35:35 1996 Jeffrey A Law (law@cygnus.com)
227
228 * interp.c (sim_resume): Fix code to check for a format 3
229 opcode.
230 * simops.c: bCC insns only argument is a constant, not a
231 register value (duh...)
232
233 Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com)
234
235 * simops.c: Fix "not1" and "set1".
236
237 * simops.c: Don't forget to initialize temp for
238 "ld.h" and "ld.w"
239
240 * interp.c: Remove various debugging printfs.
241
242 * simops.c: Fix satadd, satsub boundary case handling.
243
244 * interp.c (hash): Fix.
245 * interp.c (do_format_8): Get operands correctly and
246 call the target function.
247 * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
248
249 Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
250
251 * interp.c (do_format_4): Get operands correctly and
252 call the target function.
253 * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
254 "sst.h", and "sst.w".
255
256 * v850_sim.h: The V850 doesn't have split I&D spaces. Change
257 accordingly. Remove many unused definitions.
258 * interp.c: The V850 doesn't have split I&D spaces. Change
259 accordingly.
260 (get_longlong, get_longword, get_word): Deleted.
261 (write_longlong, write_longword, write_word): Deleted.
262 (get_operands): Deleted.
263 (get_byte, get_half, get_word): New functions.
264 (put_byte, put_half, put_word): New functions.
265 * simops.c: Remove unused functions. Rough cut at
266 "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
267
268 * v850_sim.h (struct _state): Remove "psw" field. Add
269 "sregs" field.
270 (PSW): Remove bogus definition.
271 * simops.c: Change condition code handling to use the psw
272 register within the sregs array. Handle "ldsr" and "stsr".
273
274 * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
275
276 * interp.c (do_format_5): Get operands correctly and
277 call the target function.
278 (sim_resume): Don't do a PC update for format 5 instructions.
279 * simops.c: Handle "jarl" and "jmp" instructions.
280
281 * simops.c: Fix minor typos. Handle "cmp", "setf", "tst"
282 "di", and "ei" instructions correctly.
283
284 * interp.c (do_format_3): Get operands correctly and call
285 the target function.
286 * simops.c: Handle bCC instructions.
287
288 * simops.c: Add condition code handling to shift insns.
289 Fix minor typos in condition code handling for other insns.
290
291 * Makefile.in: Fix typo.
292 * simops.c: Add condition code handling to "sub" "subr" and
293 "divh" instructions.
294
295 * interp.c (hash): Update to be more accurate.
296 (lookup_hash): Call hash rather than computing the hash
297 code here.
298 (do_format_1_2): Handle format 1 and format 2 instructions.
299 Get operands correctly and call the target function.
300 (do_format_6): Get operands correctly and call the target
301 function.
302 (do_formats_9_10): Rough cut so shift ops will work.
303 (sim_resume): Tweak to deal with format 1 and format 2
304 handling in a single funtion. Don't update the PC
305 for format 3 insns. Fix typos.
306 * simops.c: Slightly reorganize. Add condition code handling
307 to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
308 and "not" instructions.
309 * v850_sim.h (reg_t): Registers are 32bits.
310 (_state): The V850 has 32 general registers. Add a 32bit
311 psw and pc register too. Add accessor macros
312
313 * Makefile.in, interp.c, v850_sim.h: Bring over endianness
314 changes from the d10v simulator.
315
316 * simops.c: Add shift support.
317
318 * simops.c: Add multiply & divide support. Abort for system
319 instructions.
320
321 * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
322 and subr. No condition codes yet.
323
324 Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com)
325
326 * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
327 gencode.c, interp.c, simops.c: Created.
328