sim/v850/ChangeLog

   1 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
   4         "di", and "ei" instructions correctly.
   5
   6         * interp.c (do_format_3): Get operands correctly and call
   7         the target function.
   8         * simops.c: Handle bCC instructions.
   9
  10         * simops.c: Add condition code handling to shift insns.
  11         Fix minor typos in condition code handling for other insns.
  12
  13         * Makefile.in: Fix typo.
  14         * simops.c: Add condition code handling to "sub" "subr" and
  15         "divh" instructions.
  16
  17         * interp.c (hash): Update to be more accurate.
  18         (lookup_hash): Call hash rather than computing the hash
  19         code here.
  20         (do_format_1_2): Handle format 1 and format 2 instructions.
  21         Get operands correctly and call the target function.
  22         (do_format_6): Get operands correctly and call the target
  23         function.
  24         (do_formats_9_10): Rough cut so shift ops will work.
  25         (sim_resume): Tweak to deal with format 1 and format 2
  26         handling in a single funtion.  Don't update the PC
  27         for format 3 insns.  Fix typos.
  28         * simops.c: Slightly reorganize.  Add condition code handling
  29         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  30         and "not" instructions.
  31         * v850_sim.h (reg_t): Registers are 32bits.
  32         (_state): The V850 has 32 general registers.  Add a 32bit
  33         psw and pc register too.  Add accessor macros
  34
  35         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  36         changes from the d10v simulator.
  37
  38         * simops.c: Add shift support.
  39
  40         * simops.c: Add multiply & divide support.  Abort for system
  41         instructions.
  42
  43         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  44         and subr.  No condition codes yet.
  45
  46 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  47
  48         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  49         gencode.c, interp.c, simops.c: Created.
  50