sim/v850/ChangeLog

   1 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Add condition code handling to shift insns.
   4         Fix minor typos in condition code handling for other insns.
   5
   6         * Makefile.in: Fix typo.
   7         * simops.c: Add condition code handling to "sub" "subr" and
   8         "divh" instructions.
   9
  10         * interp.c (hash): Update to be more accurate.
  11         (lookup_hash): Call hash rather than computing the hash
  12         code here.
  13         (do_format_1_2): Handle format 1 and format 2 instructions.
  14         Get operands correctly and call the target function.
  15         (do_format_6): Get operands correctly and call the target
  16         function.
  17         (do_formats_9_10): Rough cut so shift ops will work.
  18         (sim_resume): Tweak to deal with format 1 and format 2
  19         handling in a single funtion.  Don't update the PC
  20         for format 3 insns.  Fix typos.
  21         * simops.c: Slightly reorganize.  Add condition code handling
  22         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  23         and "not" instructions.
  24         * v850_sim.h (reg_t): Registers are 32bits.
  25         (_state): The V850 has 32 general registers.  Add a 32bit
  26         psw and pc register too.  Add accessor macros
  27
  28         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  29         changes from the d10v simulator.
  30
  31         * simops.c: Add shift support.
  32
  33         * simops.c: Add multiply & divide support.  Abort for system
  34         instructions.
  35
  36         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  37         and subr.  No condition codes yet.
  38
  39 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  40
  41         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  42         gencode.c, interp.c, simops.c: Created.
  43