sim/v850/ChangeLog

   1 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (do_format_4): Get operands correctly and
   4         call the target function.
   5         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
   6         "sst.h", and "sst.w".
   7
   8         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
   9         accordingly.  Remove many unused definitions.
  10         * interp.c: The V850 doesn't have split I&D spaces.  Change
  11         accordingly.
  12         (get_longlong, get_longword, get_word): Deleted.
  13         (write_longlong, write_longword, write_word): Deleted.
  14         (get_operands): Deleted.
  15         (get_byte, get_half, get_word): New functions.
  16         (put_byte, put_half, put_word): New functions.
  17         * simops.c: Remove unused functions.  Rough cut at
  18         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
  19
  20         * v850_sim.h (struct _state): Remove "psw" field.  Add
  21         "sregs" field.
  22         (PSW): Remove bogus definition.
  23         * simops.c: Change condition code handling to use the psw
  24         register within the sregs array.  Handle "ldsr" and "stsr".
  25
  26         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
  27
  28         * interp.c (do_format_5): Get operands correctly and
  29         call the target function.
  30         (sim_resume): Don't do a PC update for format 5 instructions.
  31         * simops.c: Handle "jarl" and "jmp" instructions.
  32
  33         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
  34         "di", and "ei" instructions correctly.
  35
  36         * interp.c (do_format_3): Get operands correctly and call
  37         the target function.
  38         * simops.c: Handle bCC instructions.
  39
  40         * simops.c: Add condition code handling to shift insns.
  41         Fix minor typos in condition code handling for other insns.
  42
  43         * Makefile.in: Fix typo.
  44         * simops.c: Add condition code handling to "sub" "subr" and
  45         "divh" instructions.
  46
  47         * interp.c (hash): Update to be more accurate.
  48         (lookup_hash): Call hash rather than computing the hash
  49         code here.
  50         (do_format_1_2): Handle format 1 and format 2 instructions.
  51         Get operands correctly and call the target function.
  52         (do_format_6): Get operands correctly and call the target
  53         function.
  54         (do_formats_9_10): Rough cut so shift ops will work.
  55         (sim_resume): Tweak to deal with format 1 and format 2
  56         handling in a single funtion.  Don't update the PC
  57         for format 3 insns.  Fix typos.
  58         * simops.c: Slightly reorganize.  Add condition code handling
  59         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  60         and "not" instructions.
  61         * v850_sim.h (reg_t): Registers are 32bits.
  62         (_state): The V850 has 32 general registers.  Add a 32bit
  63         psw and pc register too.  Add accessor macros
  64
  65         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  66         changes from the d10v simulator.
  67
  68         * simops.c: Add shift support.
  69
  70         * simops.c: Add multiply & divide support.  Abort for system
  71         instructions.
  72
  73         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  74         and subr.  No condition codes yet.
  75
  76 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  77
  78         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  79         gencode.c, interp.c, simops.c: Created.
  80