sim/v850/ChangeLog

   1 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * v850_sim.h (struct _state): Remove "psw" field.  Add
   4         "sregs" field.
   5         (PSW): Remove bogus definition.
   6         * simops.c: Change condition code handling to use the psw
   7         register within the sregs array.  Handle "ldsr" and "stsr".
   8
   9         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
  10
  11         * interp.c (do_format_5): Get operands correctly and
  12         call the target function.
  13         (sim_resume): Don't do a PC update for format 5 instructions.
  14         * simops.c: Handle "jarl" and "jmp" instructions.
  15
  16         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
  17         "di", and "ei" instructions correctly.
  18
  19         * interp.c (do_format_3): Get operands correctly and call
  20         the target function.
  21         * simops.c: Handle bCC instructions.
  22
  23         * simops.c: Add condition code handling to shift insns.
  24         Fix minor typos in condition code handling for other insns.
  25
  26         * Makefile.in: Fix typo.
  27         * simops.c: Add condition code handling to "sub" "subr" and
  28         "divh" instructions.
  29
  30         * interp.c (hash): Update to be more accurate.
  31         (lookup_hash): Call hash rather than computing the hash
  32         code here.
  33         (do_format_1_2): Handle format 1 and format 2 instructions.
  34         Get operands correctly and call the target function.
  35         (do_format_6): Get operands correctly and call the target
  36         function.
  37         (do_formats_9_10): Rough cut so shift ops will work.
  38         (sim_resume): Tweak to deal with format 1 and format 2
  39         handling in a single funtion.  Don't update the PC
  40         for format 3 insns.  Fix typos.
  41         * simops.c: Slightly reorganize.  Add condition code handling
  42         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  43         and "not" instructions.
  44         * v850_sim.h (reg_t): Registers are 32bits.
  45         (_state): The V850 has 32 general registers.  Add a 32bit
  46         psw and pc register too.  Add accessor macros
  47
  48         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  49         changes from the d10v simulator.
  50
  51         * simops.c: Add shift support.
  52
  53         * simops.c: Add multiply & divide support.  Abort for system
  54         instructions.
  55
  56         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  57         and subr.  No condition codes yet.
  58
  59 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  60
  61         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  62         gencode.c, interp.c, simops.c: Created.
  63