sim/v850/ChangeLog

   1 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Fix "not1" and "set1".
   4
   5         * simops.c: Don't forget to initialize temp for
   6         "ld.h" and "ld.w"
   7
   8         * interp.c: Remove various debugging printfs.
   9
  10         * simops.c: Fix satadd, satsub boundary case handling.
  11
  12         * interp.c (hash): Fix.
  13         * interp.c (do_format_8): Get operands correctly and
  14         call the target function.
  15         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
  16
  17 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
  18
  19         * interp.c (do_format_4): Get operands correctly and
  20         call the target function.
  21         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
  22         "sst.h", and "sst.w".
  23
  24         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
  25         accordingly.  Remove many unused definitions.
  26         * interp.c: The V850 doesn't have split I&D spaces.  Change
  27         accordingly.
  28         (get_longlong, get_longword, get_word): Deleted.
  29         (write_longlong, write_longword, write_word): Deleted.
  30         (get_operands): Deleted.
  31         (get_byte, get_half, get_word): New functions.
  32         (put_byte, put_half, put_word): New functions.
  33         * simops.c: Remove unused functions.  Rough cut at
  34         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
  35
  36         * v850_sim.h (struct _state): Remove "psw" field.  Add
  37         "sregs" field.
  38         (PSW): Remove bogus definition.
  39         * simops.c: Change condition code handling to use the psw
  40         register within the sregs array.  Handle "ldsr" and "stsr".
  41
  42         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
  43
  44         * interp.c (do_format_5): Get operands correctly and
  45         call the target function.
  46         (sim_resume): Don't do a PC update for format 5 instructions.
  47         * simops.c: Handle "jarl" and "jmp" instructions.
  48
  49         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
  50         "di", and "ei" instructions correctly.
  51
  52         * interp.c (do_format_3): Get operands correctly and call
  53         the target function.
  54         * simops.c: Handle bCC instructions.
  55
  56         * simops.c: Add condition code handling to shift insns.
  57         Fix minor typos in condition code handling for other insns.
  58
  59         * Makefile.in: Fix typo.
  60         * simops.c: Add condition code handling to "sub" "subr" and
  61         "divh" instructions.
  62
  63         * interp.c (hash): Update to be more accurate.
  64         (lookup_hash): Call hash rather than computing the hash
  65         code here.
  66         (do_format_1_2): Handle format 1 and format 2 instructions.
  67         Get operands correctly and call the target function.
  68         (do_format_6): Get operands correctly and call the target
  69         function.
  70         (do_formats_9_10): Rough cut so shift ops will work.
  71         (sim_resume): Tweak to deal with format 1 and format 2
  72         handling in a single funtion.  Don't update the PC
  73         for format 3 insns.  Fix typos.
  74         * simops.c: Slightly reorganize.  Add condition code handling
  75         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  76         and "not" instructions.
  77         * v850_sim.h (reg_t): Registers are 32bits.
  78         (_state): The V850 has 32 general registers.  Add a 32bit
  79         psw and pc register too.  Add accessor macros
  80
  81         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  82         changes from the d10v simulator.
  83
  84         * simops.c: Add shift support.
  85
  86         * simops.c: Add multiply & divide support.  Abort for system
  87         instructions.
  88
  89         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  90         and subr.  No condition codes yet.
  91
  92 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  93
  94         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  95         gencode.c, interp.c, simops.c: Created.
  96