sim/v850/ChangeLog

   1 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (hash): Fix.
   4         * interp.c (do_format_8): Get operands correctly and
   5         call the target function.
   6         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
   7
   8 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   9
  10         * interp.c (do_format_4): Get operands correctly and
  11         call the target function.
  12         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
  13         "sst.h", and "sst.w".
  14
  15         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
  16         accordingly.  Remove many unused definitions.
  17         * interp.c: The V850 doesn't have split I&D spaces.  Change
  18         accordingly.
  19         (get_longlong, get_longword, get_word): Deleted.
  20         (write_longlong, write_longword, write_word): Deleted.
  21         (get_operands): Deleted.
  22         (get_byte, get_half, get_word): New functions.
  23         (put_byte, put_half, put_word): New functions.
  24         * simops.c: Remove unused functions.  Rough cut at
  25         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
  26
  27         * v850_sim.h (struct _state): Remove "psw" field.  Add
  28         "sregs" field.
  29         (PSW): Remove bogus definition.
  30         * simops.c: Change condition code handling to use the psw
  31         register within the sregs array.  Handle "ldsr" and "stsr".
  32
  33         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
  34
  35         * interp.c (do_format_5): Get operands correctly and
  36         call the target function.
  37         (sim_resume): Don't do a PC update for format 5 instructions.
  38         * simops.c: Handle "jarl" and "jmp" instructions.
  39
  40         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
  41         "di", and "ei" instructions correctly.
  42
  43         * interp.c (do_format_3): Get operands correctly and call
  44         the target function.
  45         * simops.c: Handle bCC instructions.
  46
  47         * simops.c: Add condition code handling to shift insns.
  48         Fix minor typos in condition code handling for other insns.
  49
  50         * Makefile.in: Fix typo.
  51         * simops.c: Add condition code handling to "sub" "subr" and
  52         "divh" instructions.
  53
  54         * interp.c (hash): Update to be more accurate.
  55         (lookup_hash): Call hash rather than computing the hash
  56         code here.
  57         (do_format_1_2): Handle format 1 and format 2 instructions.
  58         Get operands correctly and call the target function.
  59         (do_format_6): Get operands correctly and call the target
  60         function.
  61         (do_formats_9_10): Rough cut so shift ops will work.
  62         (sim_resume): Tweak to deal with format 1 and format 2
  63         handling in a single funtion.  Don't update the PC
  64         for format 3 insns.  Fix typos.
  65         * simops.c: Slightly reorganize.  Add condition code handling
  66         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  67         and "not" instructions.
  68         * v850_sim.h (reg_t): Registers are 32bits.
  69         (_state): The V850 has 32 general registers.  Add a 32bit
  70         psw and pc register too.  Add accessor macros
  71
  72         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  73         changes from the d10v simulator.
  74
  75         * simops.c: Add shift support.
  76
  77         * simops.c: Add multiply & divide support.  Abort for system
  78         instructions.
  79
  80         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  81         and subr.  No condition codes yet.
  82
  83 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  84
  85         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  86         gencode.c, interp.c, simops.c: Created.
  87