sim/v850/ChangeLog

   1 Fri Sep 27 18:34:09 1996  Stu Grossman  (grossman@critters.cygnus.com)
   2
   3         * gencode.c (write_opcodes):  Output hex values for opcode mask
   4         and patterns.
   5         * interp.c (sim_resume):  Save and restore PC from the appropriate
   6         register.
   7         * (sim_fetch_register sim_store_register):  Fix byte-order problem
   8         with reading and writing registers.
   9         * simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.
  10
  11 Fri Sep 27 17:42:37 1996  Jeffrey A Law  (law@cygnus.com)
  12
  13         * simops.c (trace_input): Fix thinko.
  14
  15 Wed Sep 18 09:54:12 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  16
  17         * simops.c (exec_bfd): Rename from sim_bfd.
  18         (trace_input): Ditto.
  19
  20 Thu Sep 12 12:03:05 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  21
  22         * simops.c (trace_input): Use find_nearest_line to print line
  23         number, function name or file name of PC.
  24
  25 Wed Sep 11 16:44:37 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  26
  27         * simops.c: Add tracing support.  Use SEXTxx macros instead of
  28         doing hardwired shifts.
  29
  30         * configure.in (--enable-sim-cflags): Add switch to add additional
  31         flags to simulator buld.  If --enable-sim-cflags=trace, turn on
  32         tracing.
  33         * configure: Regenerate.
  34
  35         * Makefile.in: Don't require a VPATH capable make if configuring
  36         in the same directory.  Don't use CFLAGS for configuration flags.
  37         Add flags from --enable-sim-cflags.  Support canadian cross
  38         builds.  Rebuild whole simulator if include files change.
  39
  40         * interp.c (v850_debug): New global for debugging.
  41         (lookup_hash,sim_size,sim_set_profile): Use
  42         printf_filtered callback, instead of calling printf directly.
  43         (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
  44
  45         * v850_sim.h: Use limits.h to set the various sized types.
  46         (SEXT{5,7,16,22}): New macros.
  47
  48 Mon Sep  9 20:50:46 1996  Jeffrey A Law  (law@cygnus.com)
  49
  50         * interp.c (hash): Make this an inline function
  51         when compiling with GCC.  Simplify.
  52         * simpos.c: Explicitly include "sys/syscall.h".  Remove
  53         some #if 0'd code.  Enable more emulated syscalls.
  54
  55 Wed Sep  4 01:48:55 1996  Jeffrey A Law  (law@cygnus.com)
  56
  57         * interp.c: Fix sign bit handling for add and sub instructions.
  58
  59 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
  60
  61         * gencode.c: Fix various indention & style problems.
  62         Remove test code.  Remove #if 0 code.
  63         * interp.c: Provide prototypes for all static functions.
  64         Fix minor indention problems.
  65         (sim_open, sim_resume): Remove unused variables.
  66         (sim_read): Return type is "int".
  67         * simops.c: Remove unused variables.
  68         (divh): Make result of divide-by-zero zero.
  69         (setf): Initialize result to keep compiler quiet.
  70         (sar instructions): These just clear the overflow bit.
  71         * v850_sim.h: Provide prototypes for put_byte, put_half
  72         and put_word.
  73
  74         * interp.c: OP should be an array of 32bit operands!
  75         (v850_callback): Declare.
  76         (do_format_5): Fix extraction of OP[0].
  77         (sim_size): Remove debugging printf.
  78         (sim_set_callbacks): Do something useful.
  79         (sim_stop_reason): Gross hacks to get c-torture running.
  80         * simops.c: Simplify code for computing targets of bCC
  81         insns.   Invert 's' bit if 'ov' bit is set for some
  82         instructions.  Fix 'cy' bit handling for numerous
  83         instructions.  Make the simulator stop when a halt
  84         instruction is encountered.  Very crude support for
  85         emulated syscalls (trap 0).
  86         * v850_sim.h: Include "callback.h" and declare
  87         v850_callback.  Items in the operand array are 32bits.
  88
  89 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
  90
  91         * interp.c (sim_resume): Fix code to check for a format 3
  92         opcode.
  93         * simops.c: bCC insns only argument is a constant, not a
  94         register value (duh...)
  95
  96 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
  97
  98         * simops.c: Fix "not1" and "set1".
  99
 100         * simops.c: Don't forget to initialize temp for
 101         "ld.h" and "ld.w"
 102
 103         * interp.c: Remove various debugging printfs.
 104
 105         * simops.c: Fix satadd, satsub boundary case handling.
 106
 107         * interp.c (hash): Fix.
 108         * interp.c (do_format_8): Get operands correctly and
 109         call the target function.
 110         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
 111
 112 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 113
 114         * interp.c (do_format_4): Get operands correctly and
 115         call the target function.
 116         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
 117         "sst.h", and "sst.w".
 118
 119         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
 120         accordingly.  Remove many unused definitions.
 121         * interp.c: The V850 doesn't have split I&D spaces.  Change
 122         accordingly.
 123         (get_longlong, get_longword, get_word): Deleted.
 124         (write_longlong, write_longword, write_word): Deleted.
 125         (get_operands): Deleted.
 126         (get_byte, get_half, get_word): New functions.
 127         (put_byte, put_half, put_word): New functions.
 128         * simops.c: Remove unused functions.  Rough cut at
 129         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
 130
 131         * v850_sim.h (struct _state): Remove "psw" field.  Add
 132         "sregs" field.
 133         (PSW): Remove bogus definition.
 134         * simops.c: Change condition code handling to use the psw
 135         register within the sregs array.  Handle "ldsr" and "stsr".
 136
 137         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
 138
 139         * interp.c (do_format_5): Get operands correctly and
 140         call the target function.
 141         (sim_resume): Don't do a PC update for format 5 instructions.
 142         * simops.c: Handle "jarl" and "jmp" instructions.
 143
 144         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
 145         "di", and "ei" instructions correctly.
 146
 147         * interp.c (do_format_3): Get operands correctly and call
 148         the target function.
 149         * simops.c: Handle bCC instructions.
 150
 151         * simops.c: Add condition code handling to shift insns.
 152         Fix minor typos in condition code handling for other insns.
 153
 154         * Makefile.in: Fix typo.
 155         * simops.c: Add condition code handling to "sub" "subr" and
 156         "divh" instructions.
 157
 158         * interp.c (hash): Update to be more accurate.
 159         (lookup_hash): Call hash rather than computing the hash
 160         code here.
 161         (do_format_1_2): Handle format 1 and format 2 instructions.
 162         Get operands correctly and call the target function.
 163         (do_format_6): Get operands correctly and call the target
 164         function.
 165         (do_formats_9_10): Rough cut so shift ops will work.
 166         (sim_resume): Tweak to deal with format 1 and format 2
 167         handling in a single funtion.  Don't update the PC
 168         for format 3 insns.  Fix typos.
 169         * simops.c: Slightly reorganize.  Add condition code handling
 170         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 171         and "not" instructions.
 172         * v850_sim.h (reg_t): Registers are 32bits.
 173         (_state): The V850 has 32 general registers.  Add a 32bit
 174         psw and pc register too.  Add accessor macros
 175
 176         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 177         changes from the d10v simulator.
 178
 179         * simops.c: Add shift support.
 180
 181         * simops.c: Add multiply & divide support.  Abort for system
 182         instructions.
 183
 184         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 185         and subr.  No condition codes yet.
 186
 187 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 188
 189         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 190         gencode.c, interp.c, simops.c: Created.
 191