sim/v850/ChangeLog

   1 Thu Oct 24 10:33:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
   2
   3         * Makefile.in:  Get rid of srcroot.  Set all INSTALL macros via
   4         autoconf.
   5         * gencode.c (write_opcodes):  Pad operands field to account for
   6         MSVC braindamage.
   7         * simops.c:  Include errno.h.  Exclude SYS_chown, since MSVC
   8         doesn't support it.  (Why is this here in the first place?!?)
   9         * v850_sim.h:  Get rid of 64 bit defs.  Also, get rid of #elif's.
  10         Change number of operands in struct simops from 9 to 6.  Define
  11         SIGTRAP and SIGQUIT for MSVC.
  12
  13 Tue Oct 15 16:19:51 1996  Stu Grossman  (grossman@critters.cygnus.com)
  14
  15         * interp.c (MEM_SIZE):  It's now bytes, not a power of 2.
  16         * (map):  Add support for external mem in the 1->2 meg range.
  17         Also, abort() when memory access is way out of bounds.  (Better to
  18         die than to give wrong result.  (This will be fixed later.))
  19         * (sim_size):  MEM_SIZE is now bytes, not shift factor.
  20
  21 Tue Oct  1 15:53:24 1996  Gavin Koch <gavin@cygnus.com>
  22
  23         * simops.c (trace_input): Swapped order of operands for output
  24         output of OP_IMM_REG.  Changed the fetching of the operands for
  25         OP_LOAD32, and OP_STORE32 to work like op-function.
  26
  27 Mon Sep 30 15:46:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
  28
  29         * interp.c:  Move includes of remote-sim.h and callback.h to
  30         v850-sim.h.
  31         * (lookup_hash): Add PC to report of hash failure.
  32         * (map load_mem store_mem):  New memory subsystem.  Models V851
  33         memory system.
  34         * (sim_write sim_read):  Use new memory subsystem.
  35         * (sim_resume):  Don't load and save PC into EIPC anymore.  Needed
  36         to make user-defined traps work right.
  37         * simops.c (OP_*):  Use new memory subsystem.
  38         * (OP_14007E0 (reti)):  Implement reti.
  39         * (OP_14996E0 (trap)):  Implement user-defined traps.  Move I/O to
  40         trap 31.  Use new memory subsystem.
  41         * v850_sim.h:  Prototypes for load_mem, store_mem and map.  Use
  42         load_mem in RLW macro.
  43
  44 Fri Sep 27 18:34:09 1996  Stu Grossman  (grossman@critters.cygnus.com)
  45
  46         * gencode.c (write_opcodes):  Output hex values for opcode mask
  47         and patterns.
  48         * interp.c (sim_resume):  Save and restore PC from the appropriate
  49         register.
  50         * (sim_fetch_register sim_store_register):  Fix byte-order problem
  51         with reading and writing registers.
  52         * simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.
  53
  54 Fri Sep 27 17:42:37 1996  Jeffrey A Law  (law@cygnus.com)
  55
  56         * simops.c (trace_input): Fix thinko.
  57
  58 Wed Sep 18 09:54:12 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  59
  60         * simops.c (exec_bfd): Rename from sim_bfd.
  61         (trace_input): Ditto.
  62
  63 Thu Sep 12 12:03:05 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  64
  65         * simops.c (trace_input): Use find_nearest_line to print line
  66         number, function name or file name of PC.
  67
  68 Wed Sep 11 16:44:37 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  69
  70         * simops.c: Add tracing support.  Use SEXTxx macros instead of
  71         doing hardwired shifts.
  72
  73         * configure.in (--enable-sim-cflags): Add switch to add additional
  74         flags to simulator buld.  If --enable-sim-cflags=trace, turn on
  75         tracing.
  76         * configure: Regenerate.
  77
  78         * Makefile.in: Don't require a VPATH capable make if configuring
  79         in the same directory.  Don't use CFLAGS for configuration flags.
  80         Add flags from --enable-sim-cflags.  Support canadian cross
  81         builds.  Rebuild whole simulator if include files change.
  82
  83         * interp.c (v850_debug): New global for debugging.
  84         (lookup_hash,sim_size,sim_set_profile): Use
  85         printf_filtered callback, instead of calling printf directly.
  86         (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
  87
  88         * v850_sim.h: Use limits.h to set the various sized types.
  89         (SEXT{5,7,16,22}): New macros.
  90
  91 Mon Sep  9 20:50:46 1996  Jeffrey A Law  (law@cygnus.com)
  92
  93         * interp.c (hash): Make this an inline function
  94         when compiling with GCC.  Simplify.
  95         * simpos.c: Explicitly include "sys/syscall.h".  Remove
  96         some #if 0'd code.  Enable more emulated syscalls.
  97
  98 Wed Sep  4 01:48:55 1996  Jeffrey A Law  (law@cygnus.com)
  99
 100         * interp.c: Fix sign bit handling for add and sub instructions.
 101
 102 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
 103
 104         * gencode.c: Fix various indention & style problems.
 105         Remove test code.  Remove #if 0 code.
 106         * interp.c: Provide prototypes for all static functions.
 107         Fix minor indention problems.
 108         (sim_open, sim_resume): Remove unused variables.
 109         (sim_read): Return type is "int".
 110         * simops.c: Remove unused variables.
 111         (divh): Make result of divide-by-zero zero.
 112         (setf): Initialize result to keep compiler quiet.
 113         (sar instructions): These just clear the overflow bit.
 114         * v850_sim.h: Provide prototypes for put_byte, put_half
 115         and put_word.
 116
 117         * interp.c: OP should be an array of 32bit operands!
 118         (v850_callback): Declare.
 119         (do_format_5): Fix extraction of OP[0].
 120         (sim_size): Remove debugging printf.
 121         (sim_set_callbacks): Do something useful.
 122         (sim_stop_reason): Gross hacks to get c-torture running.
 123         * simops.c: Simplify code for computing targets of bCC
 124         insns.   Invert 's' bit if 'ov' bit is set for some
 125         instructions.  Fix 'cy' bit handling for numerous
 126         instructions.  Make the simulator stop when a halt
 127         instruction is encountered.  Very crude support for
 128         emulated syscalls (trap 0).
 129         * v850_sim.h: Include "callback.h" and declare
 130         v850_callback.  Items in the operand array are 32bits.
 131
 132 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
 133
 134         * interp.c (sim_resume): Fix code to check for a format 3
 135         opcode.
 136         * simops.c: bCC insns only argument is a constant, not a
 137         register value (duh...)
 138
 139 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
 140
 141         * simops.c: Fix "not1" and "set1".
 142
 143         * simops.c: Don't forget to initialize temp for
 144         "ld.h" and "ld.w"
 145
 146         * interp.c: Remove various debugging printfs.
 147
 148         * simops.c: Fix satadd, satsub boundary case handling.
 149
 150         * interp.c (hash): Fix.
 151         * interp.c (do_format_8): Get operands correctly and
 152         call the target function.
 153         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
 154
 155 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 156
 157         * interp.c (do_format_4): Get operands correctly and
 158         call the target function.
 159         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
 160         "sst.h", and "sst.w".
 161
 162         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
 163         accordingly.  Remove many unused definitions.
 164         * interp.c: The V850 doesn't have split I&D spaces.  Change
 165         accordingly.
 166         (get_longlong, get_longword, get_word): Deleted.
 167         (write_longlong, write_longword, write_word): Deleted.
 168         (get_operands): Deleted.
 169         (get_byte, get_half, get_word): New functions.
 170         (put_byte, put_half, put_word): New functions.
 171         * simops.c: Remove unused functions.  Rough cut at
 172         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
 173
 174         * v850_sim.h (struct _state): Remove "psw" field.  Add
 175         "sregs" field.
 176         (PSW): Remove bogus definition.
 177         * simops.c: Change condition code handling to use the psw
 178         register within the sregs array.  Handle "ldsr" and "stsr".
 179
 180         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
 181
 182         * interp.c (do_format_5): Get operands correctly and
 183         call the target function.
 184         (sim_resume): Don't do a PC update for format 5 instructions.
 185         * simops.c: Handle "jarl" and "jmp" instructions.
 186
 187         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
 188         "di", and "ei" instructions correctly.
 189
 190         * interp.c (do_format_3): Get operands correctly and call
 191         the target function.
 192         * simops.c: Handle bCC instructions.
 193
 194         * simops.c: Add condition code handling to shift insns.
 195         Fix minor typos in condition code handling for other insns.
 196
 197         * Makefile.in: Fix typo.
 198         * simops.c: Add condition code handling to "sub" "subr" and
 199         "divh" instructions.
 200
 201         * interp.c (hash): Update to be more accurate.
 202         (lookup_hash): Call hash rather than computing the hash
 203         code here.
 204         (do_format_1_2): Handle format 1 and format 2 instructions.
 205         Get operands correctly and call the target function.
 206         (do_format_6): Get operands correctly and call the target
 207         function.
 208         (do_formats_9_10): Rough cut so shift ops will work.
 209         (sim_resume): Tweak to deal with format 1 and format 2
 210         handling in a single funtion.  Don't update the PC
 211         for format 3 insns.  Fix typos.
 212         * simops.c: Slightly reorganize.  Add condition code handling
 213         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 214         and "not" instructions.
 215         * v850_sim.h (reg_t): Registers are 32bits.
 216         (_state): The V850 has 32 general registers.  Add a 32bit
 217         psw and pc register too.  Add accessor macros
 218
 219         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 220         changes from the d10v simulator.
 221
 222         * simops.c: Add shift support.
 223
 224         * simops.c: Add multiply & divide support.  Abort for system
 225         instructions.
 226
 227         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 228         and subr.  No condition codes yet.
 229
 230 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 231
 232         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 233         gencode.c, interp.c, simops.c: Created.
 234