sim/v850/ChangeLog

   1 Mon Sep  9 20:50:46 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (hash): Make this an inline function
   4         when compiling with GCC.  Simplify.
   5         * simpos.c: Explicitly include "sys/syscall.h".  Remove
   6         some #if 0'd code.  Enable more emulated syscalls.
   7
   8 Wed Sep  4 01:48:55 1996  Jeffrey A Law  (law@cygnus.com)
   9
  10         * interp.c: Fix sign bit handling for add and sub instructions.
  11
  12 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
  13
  14         * gencode.c: Fix various indention & style problems.
  15         Remove test code.  Remove #if 0 code.
  16         * interp.c: Provide prototypes for all static functions.
  17         Fix minor indention problems.
  18         (sim_open, sim_resume): Remove unused variables.
  19         (sim_read): Return type is "int".
  20         * simops.c: Remove unused variables.
  21         (divh): Make result of divide-by-zero zero.
  22         (setf): Initialize result to keep compiler quiet.
  23         (sar instructions): These just clear the overflow bit.
  24         * v850_sim.h: Provide prototypes for put_byte, put_half
  25         and put_word.
  26
  27         * interp.c: OP should be an array of 32bit operands!
  28         (v850_callback): Declare.
  29         (do_format_5): Fix extraction of OP[0].
  30         (sim_size): Remove debugging printf.
  31         (sim_set_callbacks): Do something useful.
  32         (sim_stop_reason): Gross hacks to get c-torture running.
  33         * simops.c: Simplify code for computing targets of bCC
  34         insns.   Invert 's' bit if 'ov' bit is set for some
  35         instructions.  Fix 'cy' bit handling for numerous
  36         instructions.  Make the simulator stop when a halt
  37         instruction is encountered.  Very crude support for
  38         emulated syscalls (trap 0).
  39         * v850_sim.h: Include "callback.h" and declare
  40         v850_callback.  Items in the operand array are 32bits.
  41
  42 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
  43
  44         * interp.c (sim_resume): Fix code to check for a format 3
  45         opcode.
  46         * simops.c: bCC insns only argument is a constant, not a
  47         register value (duh...)
  48
  49 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
  50
  51         * simops.c: Fix "not1" and "set1".
  52
  53         * simops.c: Don't forget to initialize temp for
  54         "ld.h" and "ld.w"
  55
  56         * interp.c: Remove various debugging printfs.
  57
  58         * simops.c: Fix satadd, satsub boundary case handling.
  59
  60         * interp.c (hash): Fix.
  61         * interp.c (do_format_8): Get operands correctly and
  62         call the target function.
  63         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
  64
  65 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
  66
  67         * interp.c (do_format_4): Get operands correctly and
  68         call the target function.
  69         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
  70         "sst.h", and "sst.w".
  71
  72         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
  73         accordingly.  Remove many unused definitions.
  74         * interp.c: The V850 doesn't have split I&D spaces.  Change
  75         accordingly.
  76         (get_longlong, get_longword, get_word): Deleted.
  77         (write_longlong, write_longword, write_word): Deleted.
  78         (get_operands): Deleted.
  79         (get_byte, get_half, get_word): New functions.
  80         (put_byte, put_half, put_word): New functions.
  81         * simops.c: Remove unused functions.  Rough cut at
  82         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
  83
  84         * v850_sim.h (struct _state): Remove "psw" field.  Add
  85         "sregs" field.
  86         (PSW): Remove bogus definition.
  87         * simops.c: Change condition code handling to use the psw
  88         register within the sregs array.  Handle "ldsr" and "stsr".
  89
  90         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
  91
  92         * interp.c (do_format_5): Get operands correctly and
  93         call the target function.
  94         (sim_resume): Don't do a PC update for format 5 instructions.
  95         * simops.c: Handle "jarl" and "jmp" instructions.
  96
  97         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
  98         "di", and "ei" instructions correctly.
  99
 100         * interp.c (do_format_3): Get operands correctly and call
 101         the target function.
 102         * simops.c: Handle bCC instructions.
 103
 104         * simops.c: Add condition code handling to shift insns.
 105         Fix minor typos in condition code handling for other insns.
 106
 107         * Makefile.in: Fix typo.
 108         * simops.c: Add condition code handling to "sub" "subr" and
 109         "divh" instructions.
 110
 111         * interp.c (hash): Update to be more accurate.
 112         (lookup_hash): Call hash rather than computing the hash
 113         code here.
 114         (do_format_1_2): Handle format 1 and format 2 instructions.
 115         Get operands correctly and call the target function.
 116         (do_format_6): Get operands correctly and call the target
 117         function.
 118         (do_formats_9_10): Rough cut so shift ops will work.
 119         (sim_resume): Tweak to deal with format 1 and format 2
 120         handling in a single funtion.  Don't update the PC
 121         for format 3 insns.  Fix typos.
 122         * simops.c: Slightly reorganize.  Add condition code handling
 123         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 124         and "not" instructions.
 125         * v850_sim.h (reg_t): Registers are 32bits.
 126         (_state): The V850 has 32 general registers.  Add a 32bit
 127         psw and pc register too.  Add accessor macros
 128
 129         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 130         changes from the d10v simulator.
 131
 132         * simops.c: Add shift support.
 133
 134         * simops.c: Add multiply & divide support.  Abort for system
 135         instructions.
 136
 137         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 138         and subr.  No condition codes yet.
 139
 140 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 141
 142         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 143         gencode.c, interp.c, simops.c: Created.
 144