sim/v850/ChangeLog

   1 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * gencode.c: Fix various indention & style problems.
   4         Remove test code.  Remove #if 0 code.
   5         * interp.c: Provide prototypes for all static functions.
   6         Fix minor indention problems.
   7         (sim_open, sim_resume): Remove unused variables.
   8         (sim_read): Return type is "int".
   9         * simops.c: Remove unused variables.
  10         (divh): Make result of divide-by-zero zero.
  11         (setf): Initialize result to keep compiler quiet.
  12         (sar instructions): These just clear the overflow bit.
  13         * v850_sim.h: Provide prototypes for put_byte, put_half
  14         and put_word.
  15
  16         * interp.c: OP should be an array of 32bit operands!
  17         (v850_callback): Declare.
  18         (do_format_5): Fix extraction of OP[0].
  19         (sim_size): Remove debugging printf.
  20         (sim_set_callbacks): Do something useful.
  21         (sim_stop_reason): Gross hacks to get c-torture running.
  22         * simops.c: Simplify code for computing targets of bCC
  23         insns.   Invert 's' bit if 'ov' bit is set for some
  24         instructions.  Fix 'cy' bit handling for numerous
  25         instructions.  Make the simulator stop when a halt
  26         instruction is encountered.  Very crude support for
  27         emulated syscalls (trap 0).
  28         * v850_sim.h: Include "callback.h" and declare
  29         v850_callback.  Items in the operand array are 32bits.
  30
  31 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
  32
  33         * interp.c (sim_resume): Fix code to check for a format 3
  34         opcode.
  35         * simops.c: bCC insns only argument is a constant, not a
  36         register value (duh...)
  37
  38 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
  39
  40         * simops.c: Fix "not1" and "set1".
  41
  42         * simops.c: Don't forget to initialize temp for
  43         "ld.h" and "ld.w"
  44
  45         * interp.c: Remove various debugging printfs.
  46
  47         * simops.c: Fix satadd, satsub boundary case handling.
  48
  49         * interp.c (hash): Fix.
  50         * interp.c (do_format_8): Get operands correctly and
  51         call the target function.
  52         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
  53
  54 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
  55
  56         * interp.c (do_format_4): Get operands correctly and
  57         call the target function.
  58         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
  59         "sst.h", and "sst.w".
  60
  61         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
  62         accordingly.  Remove many unused definitions.
  63         * interp.c: The V850 doesn't have split I&D spaces.  Change
  64         accordingly.
  65         (get_longlong, get_longword, get_word): Deleted.
  66         (write_longlong, write_longword, write_word): Deleted.
  67         (get_operands): Deleted.
  68         (get_byte, get_half, get_word): New functions.
  69         (put_byte, put_half, put_word): New functions.
  70         * simops.c: Remove unused functions.  Rough cut at
  71         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
  72
  73         * v850_sim.h (struct _state): Remove "psw" field.  Add
  74         "sregs" field.
  75         (PSW): Remove bogus definition.
  76         * simops.c: Change condition code handling to use the psw
  77         register within the sregs array.  Handle "ldsr" and "stsr".
  78
  79         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
  80
  81         * interp.c (do_format_5): Get operands correctly and
  82         call the target function.
  83         (sim_resume): Don't do a PC update for format 5 instructions.
  84         * simops.c: Handle "jarl" and "jmp" instructions.
  85
  86         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
  87         "di", and "ei" instructions correctly.
  88
  89         * interp.c (do_format_3): Get operands correctly and call
  90         the target function.
  91         * simops.c: Handle bCC instructions.
  92
  93         * simops.c: Add condition code handling to shift insns.
  94         Fix minor typos in condition code handling for other insns.
  95
  96         * Makefile.in: Fix typo.
  97         * simops.c: Add condition code handling to "sub" "subr" and
  98         "divh" instructions.
  99
 100         * interp.c (hash): Update to be more accurate.
 101         (lookup_hash): Call hash rather than computing the hash
 102         code here.
 103         (do_format_1_2): Handle format 1 and format 2 instructions.
 104         Get operands correctly and call the target function.
 105         (do_format_6): Get operands correctly and call the target
 106         function.
 107         (do_formats_9_10): Rough cut so shift ops will work.
 108         (sim_resume): Tweak to deal with format 1 and format 2
 109         handling in a single funtion.  Don't update the PC
 110         for format 3 insns.  Fix typos.
 111         * simops.c: Slightly reorganize.  Add condition code handling
 112         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 113         and "not" instructions.
 114         * v850_sim.h (reg_t): Registers are 32bits.
 115         (_state): The V850 has 32 general registers.  Add a 32bit
 116         psw and pc register too.  Add accessor macros
 117
 118         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 119         changes from the d10v simulator.
 120
 121         * simops.c: Add shift support.
 122
 123         * simops.c: Add multiply & divide support.  Abort for system
 124         instructions.
 125
 126         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 127         and subr.  No condition codes yet.
 128
 129 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 130
 131         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 132         gencode.c, interp.c, simops.c: Created.
 133