sim/v850/ChangeLog

   1 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * Makefile.in: Fix typo.
   4         * simops.c: Add condition code handling to "sub" "subr" and
   5         "divh" instructions.
   6
   7         * interp.c (hash): Update to be more accurate.
   8         (lookup_hash): Call hash rather than computing the hash
   9         code here.
  10         (do_format_1_2): Handle format 1 and format 2 instructions.
  11         Get operands correctly and call the target function.
  12         (do_format_6): Get operands correctly and call the target
  13         function.
  14         (do_formats_9_10): Rough cut so shift ops will work.
  15         (sim_resume): Tweak to deal with format 1 and format 2
  16         handling in a single funtion.  Don't update the PC
  17         for format 3 insns.  Fix typos.
  18         * simops.c: Slightly reorganize.  Add condition code handling
  19         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  20         and "not" instructions.
  21         * v850_sim.h (reg_t): Registers are 32bits.
  22         (_state): The V850 has 32 general registers.  Add a 32bit
  23         psw and pc register too.  Add accessor macros
  24
  25         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  26         changes from the d10v simulator.
  27
  28         * simops.c: Add shift support.
  29
  30         * simops.c: Add multiply & divide support.  Abort for system
  31         instructions.
  32
  33         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  34         and subr.  No condition codes yet.
  35
  36 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  37
  38         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  39         gencode.c, interp.c, simops.c: Created.
  40