sim/v850/ChangeLog

   1 Tue Oct 29 14:22:55 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Include <sys/stat.h>.
   4         (OP_10007E0): Handle SYS_stat.
   5
   6 Thu Oct 24 12:26:35 1996  Jeffrey A Law  (law@cygnus.com)
   7
   8         * simops.c (OP_10007E0): Don't declare errno.
   9
  10         * simops.c (OP_500): Mask off low bit in displacement
  11         for sld.w.
  12         (OP_501): Similarly.
  13
  14         * simops.c (OP_500): Fix displacement handling for sld.w.
  15         (OP_501): Similarly for sst.w.
  16
  17         * simops.c (trace_input): Remove all references to SEXT7.
  18         (OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
  19         is zero extended for sst/sld instructions.
  20         * v850_sim.h (SEX7): Delete.  It's no longer needed (and it
  21         was incorrect anyway).
  22
  23 Thu Oct 24 10:33:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
  24
  25         * Makefile.in:  Get rid of srcroot.  Set all INSTALL macros via
  26         autoconf.
  27         * gencode.c (write_opcodes):  Pad operands field to account for
  28         MSVC braindamage.
  29         * simops.c:  Include errno.h.  Exclude SYS_chown, since MSVC
  30         doesn't support it.  (Why is this here in the first place?!?)
  31         * v850_sim.h:  Get rid of 64 bit defs.  Also, get rid of #elif's.
  32         Change number of operands in struct simops from 9 to 6.  Define
  33         SIGTRAP and SIGQUIT for MSVC.
  34
  35 Tue Oct 15 16:19:51 1996  Stu Grossman  (grossman@critters.cygnus.com)
  36
  37         * interp.c (MEM_SIZE):  It's now bytes, not a power of 2.
  38         * (map):  Add support for external mem in the 1->2 meg range.
  39         Also, abort() when memory access is way out of bounds.  (Better to
  40         die than to give wrong result.  (This will be fixed later.))
  41         * (sim_size):  MEM_SIZE is now bytes, not shift factor.
  42
  43 Tue Oct  1 15:53:24 1996  Gavin Koch <gavin@cygnus.com>
  44
  45         * simops.c (trace_input): Swapped order of operands for output
  46         output of OP_IMM_REG.  Changed the fetching of the operands for
  47         OP_LOAD32, and OP_STORE32 to work like op-function.
  48
  49 Mon Sep 30 15:46:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
  50
  51         * interp.c:  Move includes of remote-sim.h and callback.h to
  52         v850-sim.h.
  53         * (lookup_hash): Add PC to report of hash failure.
  54         * (map load_mem store_mem):  New memory subsystem.  Models V851
  55         memory system.
  56         * (sim_write sim_read):  Use new memory subsystem.
  57         * (sim_resume):  Don't load and save PC into EIPC anymore.  Needed
  58         to make user-defined traps work right.
  59         * simops.c (OP_*):  Use new memory subsystem.
  60         * (OP_14007E0 (reti)):  Implement reti.
  61         * (OP_14996E0 (trap)):  Implement user-defined traps.  Move I/O to
  62         trap 31.  Use new memory subsystem.
  63         * v850_sim.h:  Prototypes for load_mem, store_mem and map.  Use
  64         load_mem in RLW macro.
  65
  66 Fri Sep 27 18:34:09 1996  Stu Grossman  (grossman@critters.cygnus.com)
  67
  68         * gencode.c (write_opcodes):  Output hex values for opcode mask
  69         and patterns.
  70         * interp.c (sim_resume):  Save and restore PC from the appropriate
  71         register.
  72         * (sim_fetch_register sim_store_register):  Fix byte-order problem
  73         with reading and writing registers.
  74         * simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.
  75
  76 Fri Sep 27 17:42:37 1996  Jeffrey A Law  (law@cygnus.com)
  77
  78         * simops.c (trace_input): Fix thinko.
  79
  80 Wed Sep 18 09:54:12 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  81
  82         * simops.c (exec_bfd): Rename from sim_bfd.
  83         (trace_input): Ditto.
  84
  85 Thu Sep 12 12:03:05 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  86
  87         * simops.c (trace_input): Use find_nearest_line to print line
  88         number, function name or file name of PC.
  89
  90 Wed Sep 11 16:44:37 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  91
  92         * simops.c: Add tracing support.  Use SEXTxx macros instead of
  93         doing hardwired shifts.
  94
  95         * configure.in (--enable-sim-cflags): Add switch to add additional
  96         flags to simulator buld.  If --enable-sim-cflags=trace, turn on
  97         tracing.
  98         * configure: Regenerate.
  99
 100         * Makefile.in: Don't require a VPATH capable make if configuring
 101         in the same directory.  Don't use CFLAGS for configuration flags.
 102         Add flags from --enable-sim-cflags.  Support canadian cross
 103         builds.  Rebuild whole simulator if include files change.
 104
 105         * interp.c (v850_debug): New global for debugging.
 106         (lookup_hash,sim_size,sim_set_profile): Use
 107         printf_filtered callback, instead of calling printf directly.
 108         (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
 109
 110         * v850_sim.h: Use limits.h to set the various sized types.
 111         (SEXT{5,7,16,22}): New macros.
 112
 113 Mon Sep  9 20:50:46 1996  Jeffrey A Law  (law@cygnus.com)
 114
 115         * interp.c (hash): Make this an inline function
 116         when compiling with GCC.  Simplify.
 117         * simpos.c: Explicitly include "sys/syscall.h".  Remove
 118         some #if 0'd code.  Enable more emulated syscalls.
 119
 120 Wed Sep  4 01:48:55 1996  Jeffrey A Law  (law@cygnus.com)
 121
 122         * interp.c: Fix sign bit handling for add and sub instructions.
 123
 124 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
 125
 126         * gencode.c: Fix various indention & style problems.
 127         Remove test code.  Remove #if 0 code.
 128         * interp.c: Provide prototypes for all static functions.
 129         Fix minor indention problems.
 130         (sim_open, sim_resume): Remove unused variables.
 131         (sim_read): Return type is "int".
 132         * simops.c: Remove unused variables.
 133         (divh): Make result of divide-by-zero zero.
 134         (setf): Initialize result to keep compiler quiet.
 135         (sar instructions): These just clear the overflow bit.
 136         * v850_sim.h: Provide prototypes for put_byte, put_half
 137         and put_word.
 138
 139         * interp.c: OP should be an array of 32bit operands!
 140         (v850_callback): Declare.
 141         (do_format_5): Fix extraction of OP[0].
 142         (sim_size): Remove debugging printf.
 143         (sim_set_callbacks): Do something useful.
 144         (sim_stop_reason): Gross hacks to get c-torture running.
 145         * simops.c: Simplify code for computing targets of bCC
 146         insns.   Invert 's' bit if 'ov' bit is set for some
 147         instructions.  Fix 'cy' bit handling for numerous
 148         instructions.  Make the simulator stop when a halt
 149         instruction is encountered.  Very crude support for
 150         emulated syscalls (trap 0).
 151         * v850_sim.h: Include "callback.h" and declare
 152         v850_callback.  Items in the operand array are 32bits.
 153
 154 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
 155
 156         * interp.c (sim_resume): Fix code to check for a format 3
 157         opcode.
 158         * simops.c: bCC insns only argument is a constant, not a
 159         register value (duh...)
 160
 161 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
 162
 163         * simops.c: Fix "not1" and "set1".
 164
 165         * simops.c: Don't forget to initialize temp for
 166         "ld.h" and "ld.w"
 167
 168         * interp.c: Remove various debugging printfs.
 169
 170         * simops.c: Fix satadd, satsub boundary case handling.
 171
 172         * interp.c (hash): Fix.
 173         * interp.c (do_format_8): Get operands correctly and
 174         call the target function.
 175         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
 176
 177 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 178
 179         * interp.c (do_format_4): Get operands correctly and
 180         call the target function.
 181         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
 182         "sst.h", and "sst.w".
 183
 184         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
 185         accordingly.  Remove many unused definitions.
 186         * interp.c: The V850 doesn't have split I&D spaces.  Change
 187         accordingly.
 188         (get_longlong, get_longword, get_word): Deleted.
 189         (write_longlong, write_longword, write_word): Deleted.
 190         (get_operands): Deleted.
 191         (get_byte, get_half, get_word): New functions.
 192         (put_byte, put_half, put_word): New functions.
 193         * simops.c: Remove unused functions.  Rough cut at
 194         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
 195
 196         * v850_sim.h (struct _state): Remove "psw" field.  Add
 197         "sregs" field.
 198         (PSW): Remove bogus definition.
 199         * simops.c: Change condition code handling to use the psw
 200         register within the sregs array.  Handle "ldsr" and "stsr".
 201
 202         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
 203
 204         * interp.c (do_format_5): Get operands correctly and
 205         call the target function.
 206         (sim_resume): Don't do a PC update for format 5 instructions.
 207         * simops.c: Handle "jarl" and "jmp" instructions.
 208
 209         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
 210         "di", and "ei" instructions correctly.
 211
 212         * interp.c (do_format_3): Get operands correctly and call
 213         the target function.
 214         * simops.c: Handle bCC instructions.
 215
 216         * simops.c: Add condition code handling to shift insns.
 217         Fix minor typos in condition code handling for other insns.
 218
 219         * Makefile.in: Fix typo.
 220         * simops.c: Add condition code handling to "sub" "subr" and
 221         "divh" instructions.
 222
 223         * interp.c (hash): Update to be more accurate.
 224         (lookup_hash): Call hash rather than computing the hash
 225         code here.
 226         (do_format_1_2): Handle format 1 and format 2 instructions.
 227         Get operands correctly and call the target function.
 228         (do_format_6): Get operands correctly and call the target
 229         function.
 230         (do_formats_9_10): Rough cut so shift ops will work.
 231         (sim_resume): Tweak to deal with format 1 and format 2
 232         handling in a single funtion.  Don't update the PC
 233         for format 3 insns.  Fix typos.
 234         * simops.c: Slightly reorganize.  Add condition code handling
 235         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 236         and "not" instructions.
 237         * v850_sim.h (reg_t): Registers are 32bits.
 238         (_state): The V850 has 32 general registers.  Add a 32bit
 239         psw and pc register too.  Add accessor macros
 240
 241         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 242         changes from the d10v simulator.
 243
 244         * simops.c: Add shift support.
 245
 246         * simops.c: Add multiply & divide support.  Abort for system
 247         instructions.
 248
 249         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 250         and subr.  No condition codes yet.
 251
 252 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 253
 254         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 255         gencode.c, interp.c, simops.c: Created.
 256