sim/v850/ChangeLog

   1 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (do_format_5): Get operands correctly and
   4         call the target function.
   5         (sim_resume): Don't do a PC update for format 5 instructions.
   6         * simops.c: Handle "jarl" and "jmp" instructions.
   7
   8         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
   9         "di", and "ei" instructions correctly.
  10
  11         * interp.c (do_format_3): Get operands correctly and call
  12         the target function.
  13         * simops.c: Handle bCC instructions.
  14
  15         * simops.c: Add condition code handling to shift insns.
  16         Fix minor typos in condition code handling for other insns.
  17
  18         * Makefile.in: Fix typo.
  19         * simops.c: Add condition code handling to "sub" "subr" and
  20         "divh" instructions.
  21
  22         * interp.c (hash): Update to be more accurate.
  23         (lookup_hash): Call hash rather than computing the hash
  24         code here.
  25         (do_format_1_2): Handle format 1 and format 2 instructions.
  26         Get operands correctly and call the target function.
  27         (do_format_6): Get operands correctly and call the target
  28         function.
  29         (do_formats_9_10): Rough cut so shift ops will work.
  30         (sim_resume): Tweak to deal with format 1 and format 2
  31         handling in a single funtion.  Don't update the PC
  32         for format 3 insns.  Fix typos.
  33         * simops.c: Slightly reorganize.  Add condition code handling
  34         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  35         and "not" instructions.
  36         * v850_sim.h (reg_t): Registers are 32bits.
  37         (_state): The V850 has 32 general registers.  Add a 32bit
  38         psw and pc register too.  Add accessor macros
  39
  40         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  41         changes from the d10v simulator.
  42
  43         * simops.c: Add shift support.
  44
  45         * simops.c: Add multiply & divide support.  Abort for system
  46         instructions.
  47
  48         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  49         and subr.  No condition codes yet.
  50
  51 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  52
  53         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  54         gencode.c, interp.c, simops.c: Created.
  55