sim/v850/ChangeLog

   1 Thu Oct 24 12:26:35 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c (OP_500): Mask off low bit in displacement
   4         for sld.w.
   5         (OP_501): Similarly.
   6
   7         * simops.c (OP_500): Fix displacement handling for sld.w.
   8         (OP_501): Similarly for sst.w.
   9
  10         * simops.c (trace_input): Remove all references to SEXT7.
  11         (OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
  12         is zero extended for sst/sld instructions.
  13         * v850_sim.h (SEX7): Delete.  It's no longer needed (and it
  14         was incorrect anyway).
  15
  16 Thu Oct 24 10:33:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
  17
  18         * Makefile.in:  Get rid of srcroot.  Set all INSTALL macros via
  19         autoconf.
  20         * gencode.c (write_opcodes):  Pad operands field to account for
  21         MSVC braindamage.
  22         * simops.c:  Include errno.h.  Exclude SYS_chown, since MSVC
  23         doesn't support it.  (Why is this here in the first place?!?)
  24         * v850_sim.h:  Get rid of 64 bit defs.  Also, get rid of #elif's.
  25         Change number of operands in struct simops from 9 to 6.  Define
  26         SIGTRAP and SIGQUIT for MSVC.
  27
  28 Tue Oct 15 16:19:51 1996  Stu Grossman  (grossman@critters.cygnus.com)
  29
  30         * interp.c (MEM_SIZE):  It's now bytes, not a power of 2.
  31         * (map):  Add support for external mem in the 1->2 meg range.
  32         Also, abort() when memory access is way out of bounds.  (Better to
  33         die than to give wrong result.  (This will be fixed later.))
  34         * (sim_size):  MEM_SIZE is now bytes, not shift factor.
  35
  36 Tue Oct  1 15:53:24 1996  Gavin Koch <gavin@cygnus.com>
  37
  38         * simops.c (trace_input): Swapped order of operands for output
  39         output of OP_IMM_REG.  Changed the fetching of the operands for
  40         OP_LOAD32, and OP_STORE32 to work like op-function.
  41
  42 Mon Sep 30 15:46:33 1996  Stu Grossman  (grossman@critters.cygnus.com)
  43
  44         * interp.c:  Move includes of remote-sim.h and callback.h to
  45         v850-sim.h.
  46         * (lookup_hash): Add PC to report of hash failure.
  47         * (map load_mem store_mem):  New memory subsystem.  Models V851
  48         memory system.
  49         * (sim_write sim_read):  Use new memory subsystem.
  50         * (sim_resume):  Don't load and save PC into EIPC anymore.  Needed
  51         to make user-defined traps work right.
  52         * simops.c (OP_*):  Use new memory subsystem.
  53         * (OP_14007E0 (reti)):  Implement reti.
  54         * (OP_14996E0 (trap)):  Implement user-defined traps.  Move I/O to
  55         trap 31.  Use new memory subsystem.
  56         * v850_sim.h:  Prototypes for load_mem, store_mem and map.  Use
  57         load_mem in RLW macro.
  58
  59 Fri Sep 27 18:34:09 1996  Stu Grossman  (grossman@critters.cygnus.com)
  60
  61         * gencode.c (write_opcodes):  Output hex values for opcode mask
  62         and patterns.
  63         * interp.c (sim_resume):  Save and restore PC from the appropriate
  64         register.
  65         * (sim_fetch_register sim_store_register):  Fix byte-order problem
  66         with reading and writing registers.
  67         * simops.c (OP_FFFF):  Implement pseudo-breakpoint insn.
  68
  69 Fri Sep 27 17:42:37 1996  Jeffrey A Law  (law@cygnus.com)
  70
  71         * simops.c (trace_input): Fix thinko.
  72
  73 Wed Sep 18 09:54:12 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  74
  75         * simops.c (exec_bfd): Rename from sim_bfd.
  76         (trace_input): Ditto.
  77
  78 Thu Sep 12 12:03:05 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  79
  80         * simops.c (trace_input): Use find_nearest_line to print line
  81         number, function name or file name of PC.
  82
  83 Wed Sep 11 16:44:37 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
  84
  85         * simops.c: Add tracing support.  Use SEXTxx macros instead of
  86         doing hardwired shifts.
  87
  88         * configure.in (--enable-sim-cflags): Add switch to add additional
  89         flags to simulator buld.  If --enable-sim-cflags=trace, turn on
  90         tracing.
  91         * configure: Regenerate.
  92
  93         * Makefile.in: Don't require a VPATH capable make if configuring
  94         in the same directory.  Don't use CFLAGS for configuration flags.
  95         Add flags from --enable-sim-cflags.  Support canadian cross
  96         builds.  Rebuild whole simulator if include files change.
  97
  98         * interp.c (v850_debug): New global for debugging.
  99         (lookup_hash,sim_size,sim_set_profile): Use
 100         printf_filtered callback, instead of calling printf directly.
 101         (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
 102
 103         * v850_sim.h: Use limits.h to set the various sized types.
 104         (SEXT{5,7,16,22}): New macros.
 105
 106 Mon Sep  9 20:50:46 1996  Jeffrey A Law  (law@cygnus.com)
 107
 108         * interp.c (hash): Make this an inline function
 109         when compiling with GCC.  Simplify.
 110         * simpos.c: Explicitly include "sys/syscall.h".  Remove
 111         some #if 0'd code.  Enable more emulated syscalls.
 112
 113 Wed Sep  4 01:48:55 1996  Jeffrey A Law  (law@cygnus.com)
 114
 115         * interp.c: Fix sign bit handling for add and sub instructions.
 116
 117 Tue Sep  3 10:20:30 1996  Jeffrey A Law  (law@cygnus.com)
 118
 119         * gencode.c: Fix various indention & style problems.
 120         Remove test code.  Remove #if 0 code.
 121         * interp.c: Provide prototypes for all static functions.
 122         Fix minor indention problems.
 123         (sim_open, sim_resume): Remove unused variables.
 124         (sim_read): Return type is "int".
 125         * simops.c: Remove unused variables.
 126         (divh): Make result of divide-by-zero zero.
 127         (setf): Initialize result to keep compiler quiet.
 128         (sar instructions): These just clear the overflow bit.
 129         * v850_sim.h: Provide prototypes for put_byte, put_half
 130         and put_word.
 131
 132         * interp.c: OP should be an array of 32bit operands!
 133         (v850_callback): Declare.
 134         (do_format_5): Fix extraction of OP[0].
 135         (sim_size): Remove debugging printf.
 136         (sim_set_callbacks): Do something useful.
 137         (sim_stop_reason): Gross hacks to get c-torture running.
 138         * simops.c: Simplify code for computing targets of bCC
 139         insns.   Invert 's' bit if 'ov' bit is set for some
 140         instructions.  Fix 'cy' bit handling for numerous
 141         instructions.  Make the simulator stop when a halt
 142         instruction is encountered.  Very crude support for
 143         emulated syscalls (trap 0).
 144         * v850_sim.h: Include "callback.h" and declare
 145         v850_callback.  Items in the operand array are 32bits.
 146
 147 Sun Sep  1 22:35:35 1996  Jeffrey A Law  (law@cygnus.com)
 148
 149         * interp.c (sim_resume): Fix code to check for a format 3
 150         opcode.
 151         * simops.c: bCC insns only argument is a constant, not a
 152         register value (duh...)
 153
 154 Fri Aug 30 10:33:49 1996  Jeffrey A Law  (law@cygnus.com)
 155
 156         * simops.c: Fix "not1" and "set1".
 157
 158         * simops.c: Don't forget to initialize temp for
 159         "ld.h" and "ld.w"
 160
 161         * interp.c: Remove various debugging printfs.
 162
 163         * simops.c: Fix satadd, satsub boundary case handling.
 164
 165         * interp.c (hash): Fix.
 166         * interp.c (do_format_8): Get operands correctly and
 167         call the target function.
 168         * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
 169
 170 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 171
 172         * interp.c (do_format_4): Get operands correctly and
 173         call the target function.
 174         * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
 175         "sst.h", and "sst.w".
 176
 177         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
 178         accordingly.  Remove many unused definitions.
 179         * interp.c: The V850 doesn't have split I&D spaces.  Change
 180         accordingly.
 181         (get_longlong, get_longword, get_word): Deleted.
 182         (write_longlong, write_longword, write_word): Deleted.
 183         (get_operands): Deleted.
 184         (get_byte, get_half, get_word): New functions.
 185         (put_byte, put_half, put_word): New functions.
 186         * simops.c: Remove unused functions.  Rough cut at
 187         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
 188
 189         * v850_sim.h (struct _state): Remove "psw" field.  Add
 190         "sregs" field.
 191         (PSW): Remove bogus definition.
 192         * simops.c: Change condition code handling to use the psw
 193         register within the sregs array.  Handle "ldsr" and "stsr".
 194
 195         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
 196
 197         * interp.c (do_format_5): Get operands correctly and
 198         call the target function.
 199         (sim_resume): Don't do a PC update for format 5 instructions.
 200         * simops.c: Handle "jarl" and "jmp" instructions.
 201
 202         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
 203         "di", and "ei" instructions correctly.
 204
 205         * interp.c (do_format_3): Get operands correctly and call
 206         the target function.
 207         * simops.c: Handle bCC instructions.
 208
 209         * simops.c: Add condition code handling to shift insns.
 210         Fix minor typos in condition code handling for other insns.
 211
 212         * Makefile.in: Fix typo.
 213         * simops.c: Add condition code handling to "sub" "subr" and
 214         "divh" instructions.
 215
 216         * interp.c (hash): Update to be more accurate.
 217         (lookup_hash): Call hash rather than computing the hash
 218         code here.
 219         (do_format_1_2): Handle format 1 and format 2 instructions.
 220         Get operands correctly and call the target function.
 221         (do_format_6): Get operands correctly and call the target
 222         function.
 223         (do_formats_9_10): Rough cut so shift ops will work.
 224         (sim_resume): Tweak to deal with format 1 and format 2
 225         handling in a single funtion.  Don't update the PC
 226         for format 3 insns.  Fix typos.
 227         * simops.c: Slightly reorganize.  Add condition code handling
 228         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
 229         and "not" instructions.
 230         * v850_sim.h (reg_t): Registers are 32bits.
 231         (_state): The V850 has 32 general registers.  Add a 32bit
 232         psw and pc register too.  Add accessor macros
 233
 234         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
 235         changes from the d10v simulator.
 236
 237         * simops.c: Add shift support.
 238
 239         * simops.c: Add multiply & divide support.  Abort for system
 240         instructions.
 241
 242         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
 243         and subr.  No condition codes yet.
 244
 245 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
 246
 247         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
 248         gencode.c, interp.c, simops.c: Created.
 249