2 #include "sim-options.h"
4 #include "sim-assert.h"
12 static const char * get_insn_name (sim_cpu
*, int);
14 /* For compatibility. */
17 /* V850 interrupt model. */
32 const char *interrupt_names
[] =
46 do_interrupt (SIM_DESC sd
, void *data
)
48 const char **interrupt_name
= (const char**)data
;
49 enum interrupt_type inttype
;
50 inttype
= (interrupt_name
- STATE_WATCHPOINTS (sd
)->interrupt_names
);
52 /* For a hardware reset, drop everything and jump to the start
54 if (inttype
== int_reset
)
59 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
62 /* Deliver an NMI when allowed */
63 if (inttype
== int_nmi
)
67 /* We're already working on an NMI, so this one must wait
68 around until the previous one is done. The processor
69 ignores subsequent NMIs, so we don't need to count them.
70 Just keep re-scheduling a single NMI until it manages to
72 if (STATE_CPU (sd
, 0)->pending_nmi
!= NULL
)
73 sim_events_deschedule (sd
, STATE_CPU (sd
, 0)->pending_nmi
);
74 STATE_CPU (sd
, 0)->pending_nmi
=
75 sim_events_schedule (sd
, 1, do_interrupt
, data
);
80 /* NMI can be delivered. Do not deschedule pending_nmi as
81 that, if still in the event queue, is a second NMI that
82 needs to be delivered later. */
85 /* Set the FECC part of the ECR. */
92 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
96 /* deliver maskable interrupt when allowed */
97 if (inttype
> int_nmi
&& inttype
< num_int_types
)
99 if ((PSW
& PSW_NP
) || (PSW
& PSW_ID
))
101 /* Can't deliver this interrupt, reschedule it for later */
102 sim_events_schedule (sd
, 1, do_interrupt
, data
);
110 /* Disable further interrupts. */
112 /* Indicate that we're doing interrupt not exception processing. */
114 /* Clear the EICC part of the ECR, will set below. */
143 /* Should never be possible. */
144 sim_engine_abort (sd
, NULL
, NULL_CIA
,
145 "do_interrupt - internal error - bad switch");
149 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
152 /* some other interrupt? */
153 sim_engine_abort (sd
, NULL
, NULL_CIA
,
154 "do_interrupt - internal error - interrupt %d unknown",
158 /* Return name of an insn, used by insn profiling. */
161 get_insn_name (sim_cpu
*cpu
, int i
)
163 return itable
[i
].name
;
166 /* These default values correspond to expected usage for the chip. */
171 v850_pc_get (sim_cpu
*cpu
)
177 v850_pc_set (sim_cpu
*cpu
, sim_cia pc
)
182 static int v850_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
183 static int v850_reg_store (SIM_CPU
*, int, unsigned char *, int);
186 sim_open (SIM_OPEN_KIND kind
,
192 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
195 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
197 /* The cpu data is kept in a separately allocated chunk of memory. */
198 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
201 /* for compatibility */
204 /* FIXME: should be better way of setting up interrupts */
205 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
206 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
207 STATE_WATCHPOINTS (sd
)->interrupt_handler
= do_interrupt
;
208 STATE_WATCHPOINTS (sd
)->interrupt_names
= interrupt_names
;
210 /* Initialize the mechanism for doing insn profiling. */
211 CPU_INSN_NAME (STATE_CPU (sd
, 0)) = get_insn_name
;
212 CPU_MAX_INSNS (STATE_CPU (sd
, 0)) = nr_itable_entries
;
214 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
217 /* Allocate core managed memory */
219 /* "Mirror" the ROM addresses below 1MB. */
220 sim_do_commandf (sd
, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE
);
221 /* Chunk of ram adjacent to rom */
222 sim_do_commandf (sd
, "memory region 0x100000,0x%lx", V850_LOW_END
-0x100000);
223 /* peripheral I/O region - mirror 1K across 4k (0x1000) */
224 sim_do_command (sd
, "memory region 0xfff000,0x1000,1024");
225 /* similarly if in the internal RAM region */
226 sim_do_command (sd
, "memory region 0xffe000,0x1000,1024");
228 /* The parser will print an error message for us, so we silently return. */
229 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
231 /* Uninstall the modules to avoid memory leaks,
232 file descriptor leaks, etc. */
233 sim_module_uninstall (sd
);
237 /* check for/establish the a reference program image */
238 if (sim_analyze_program (sd
,
239 (STATE_PROG_ARGV (sd
) != NULL
240 ? *STATE_PROG_ARGV (sd
)
244 sim_module_uninstall (sd
);
248 /* establish any remaining configuration options */
249 if (sim_config (sd
) != SIM_RC_OK
)
251 sim_module_uninstall (sd
);
255 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
257 /* Uninstall the modules to avoid memory leaks,
258 file descriptor leaks, etc. */
259 sim_module_uninstall (sd
);
264 /* determine the machine type */
265 if (STATE_ARCHITECTURE (sd
) != NULL
266 && (STATE_ARCHITECTURE (sd
)->arch
== bfd_arch_v850
267 || STATE_ARCHITECTURE (sd
)->arch
== bfd_arch_v850_rh850
))
268 mach
= STATE_ARCHITECTURE (sd
)->mach
;
270 mach
= bfd_mach_v850
; /* default */
272 /* set machine specific configuration */
277 case bfd_mach_v850e1
:
278 case bfd_mach_v850e2
:
279 case bfd_mach_v850e2v3
:
280 case bfd_mach_v850e3v5
:
281 STATE_CPU (sd
, 0)->psw_mask
= (PSW_NP
| PSW_EP
| PSW_ID
| PSW_SAT
282 | PSW_CY
| PSW_OV
| PSW_S
| PSW_Z
);
286 /* CPU specific initialization. */
287 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
289 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
291 CPU_REG_FETCH (cpu
) = v850_reg_fetch
;
292 CPU_REG_STORE (cpu
) = v850_reg_store
;
293 CPU_PC_FETCH (cpu
) = v850_pc_get
;
294 CPU_PC_STORE (cpu
) = v850_pc_set
;
301 sim_create_inferior (SIM_DESC sd
,
302 struct bfd
* prog_bfd
,
306 memset (&State
, 0, sizeof (State
));
307 if (prog_bfd
!= NULL
)
308 PC
= bfd_get_start_address (prog_bfd
);
313 v850_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
315 *(unsigned32
*)memory
= H2T_4 (State
.regs
[rn
]);
320 v850_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
322 State
.regs
[rn
] = T2H_4 (*(unsigned32
*) memory
);