sim/v850/sim-main.h

   1 #ifndef SIM_MAIN_H
   2 #define SIM_MAIN_H
   3
   4 /* General config options */
   5
   6 #define WITH_WATCHPOINTS 1
   7
   8
   9 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
  10
  11 #define WITH_TARGET_WORD_MSB 31
  12
  13 #include "config.h"
  14 #include "sim-basics.h"
  15 #include "sim-signal.h"
  16 #include "sim-fpu.h"
  17 #include "sim-base.h"
  18
  19 #include "simops.h"
  20 #include "bfd.h"
  21
  22
  23 typedef signed8 int8;
  24 typedef unsigned8 uint8;
  25 typedef signed16 int16;
  26 typedef unsigned16 uint16;
  27 typedef signed32 int32;
  28 typedef unsigned32 uint32;
  29 typedef unsigned32 reg_t;
  30 typedef unsigned64 reg64_t;
  31
  32
  33 /* The current state of the processor; registers, memory, etc.  */
  34
  35 typedef struct _v850_regs {
  36   reg_t regs[32];               /* general-purpose registers */
  37   reg_t sregs[32];              /* system registers, including psw */
  38   reg_t pc;
  39   int dummy_mem;                /* where invalid accesses go */
  40   reg_t mpu0_sregs[28];         /* mpu0 system registers */
  41   reg_t mpu1_sregs[28];         /* mpu1 system registers */
  42   reg_t fpu_sregs[28];          /* fpu system registers */
  43   reg_t selID_sregs[7][32];     /* system registers, selID 1 thru selID 7 */
  44   reg64_t vregs[32];            /* vector registers.  */
  45 } v850_regs;
  46
  47 struct _sim_cpu
  48 {
  49   /* ... simulator specific members ... */
  50   v850_regs reg;
  51   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  52   sim_event *pending_nmi;
  53   /* ... base type ... */
  54   sim_cpu_base base;
  55 };
  56
  57 struct sim_state {
  58   sim_cpu *cpu[MAX_NR_PROCESSORS];
  59 #if 0
  60   SIM_ADDR rom_size;
  61   SIM_ADDR low_end;
  62   SIM_ADDR high_start;
  63   SIM_ADDR high_base;
  64   void *mem;
  65 #endif
  66   sim_state_base base;
  67 };
  68
  69 /* For compatibility, until all functions converted to passing
  70    SIM_DESC as an argument */
  71 extern SIM_DESC simulator;
  72
  73
  74 #define V850_ROM_SIZE 0x8000
  75 #define V850_LOW_END 0x200000
  76 #define V850_HIGH_START 0xffe000
  77
  78
  79 /* Because we are still using the old semantic table, provide compat
  80    macro's that store the instruction where the old simops expects
  81    it. */
  82
  83 extern uint32 OP[4];
  84 #if 0
  85 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  86 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  87 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
  88 OP[3] = inst;
  89 #endif
  90
  91 #define SAVE_1 \
  92 PC = cia; \
  93 OP[0] = instruction_0 & 0x1f; \
  94 OP[1] = (instruction_0 >> 11) & 0x1f; \
  95 OP[2] = 0; \
  96 OP[3] = instruction_0
  97
  98 #define COMPAT_1(CALL) \
  99 SAVE_1; \
 100 PC += (CALL); \
 101 nia = PC
 102
 103 #define SAVE_2 \
 104 PC = cia; \
 105 OP[0] = instruction_0 & 0x1f; \
 106 OP[1] = (instruction_0 >> 11) & 0x1f; \
 107 OP[2] = instruction_1; \
 108 OP[3] = (instruction_1 << 16) | instruction_0
 109
 110 #define COMPAT_2(CALL) \
 111 SAVE_2; \
 112 PC += (CALL); \
 113 nia = PC
 114
 115
 116 /* new */
 117 #define GR  ((CPU)->reg.regs)
 118 #define SR  ((CPU)->reg.sregs)
 119 #define VR  ((CPU)->reg.vregs)
 120 #define MPU0_SR  ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
 121 #define MPU1_SR  ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
 122 #define FPU_SR   ((STATE_CPU (sd, 0))->reg.fpu_sregs)
 123
 124 /* old */
 125 #define State    (STATE_CPU (simulator, 0)->reg)
 126 #define PC      (State.pc)
 127 #define SP_REGNO        3
 128 #define SP      (State.regs[SP_REGNO])
 129 #define EP      (State.regs[30])
 130
 131 #define EIPC  (State.sregs[0])
 132 #define EIPSW (State.sregs[1])
 133 #define FEPC  (State.sregs[2])
 134 #define FEPSW (State.sregs[3])
 135 #define ECR   (State.sregs[4])
 136 #define PSW   (State.sregs[5])
 137 #define PSW_REGNO   5
 138 #define EIIC  (State.sregs[13])
 139 #define FEIC  (State.sregs[14])
 140 #define DBIC  (SR[15])
 141 #define CTPC  (SR[16])
 142 #define CTPSW (SR[17])
 143 #define DBPC  (State.sregs[18])
 144 #define DBPSW (State.sregs[19])
 145 #define CTBP  (State.sregs[20])
 146 #define DIR   (SR[21])
 147 #define EIWR  (SR[28])
 148 #define FEWR  (SR[29])
 149 #define DBWR  (SR[30])
 150 #define BSEL  (SR[31])
 151
 152 #define PSW_US BIT32 (8)
 153 #define PSW_NP 0x80
 154 #define PSW_EP 0x40
 155 #define PSW_ID 0x20
 156 #define PSW_SAT 0x10
 157 #define PSW_CY 0x8
 158 #define PSW_OV 0x4
 159 #define PSW_S 0x2
 160 #define PSW_Z 0x1
 161
 162 #define PSW_NPV (1<<18)
 163 #define PSW_DMP (1<<17)
 164 #define PSW_IMP (1<<16)
 165
 166 #define ECR_EICC 0x0000ffff
 167 #define ECR_FECC 0xffff0000
 168
 169 /* FPU */
 170
 171 #define FPSR  (FPU_SR[6])
 172 #define FPSR_REGNO 6
 173 #define FPEPC (FPU_SR[7])
 174 #define FPST  (FPU_SR[8])
 175 #define FPST_REGNO 8
 176 #define FPCC  (FPU_SR[9])
 177 #define FPCFG (FPU_SR[10])
 178 #define FPCFG_REGNO 10
 179
 180 #define FPSR_DEM  0x00200000
 181 #define FPSR_SEM  0x00100000
 182 #define FPSR_RM   0x000c0000
 183 #define FPSR_RN   0x00000000
 184 #define FPSR_FS   0x00020000
 185 #define FPSR_PR   0x00010000
 186
 187 #define FPSR_XC   0x0000fc00
 188 #define FPSR_XCE  0x00008000
 189 #define FPSR_XCV  0x00004000
 190 #define FPSR_XCZ  0x00002000
 191 #define FPSR_XCO  0x00001000
 192 #define FPSR_XCU  0x00000800
 193 #define FPSR_XCI  0x00000400
 194
 195 #define FPSR_XE   0x000003e0
 196 #define FPSR_XEV  0x00000200
 197 #define FPSR_XEZ  0x00000100
 198 #define FPSR_XEO  0x00000080
 199 #define FPSR_XEU  0x00000040
 200 #define FPSR_XEI  0x00000020
 201
 202 #define FPSR_XP   0x0000001f
 203 #define FPSR_XPV  0x00000010
 204 #define FPSR_XPZ  0x00000008
 205 #define FPSR_XPO  0x00000004
 206 #define FPSR_XPU  0x00000002
 207 #define FPSR_XPI  0x00000001
 208
 209 #define FPST_PR   0x00008000
 210 #define FPST_XCE  0x00002000
 211 #define FPST_XCV  0x00001000
 212 #define FPST_XCZ  0x00000800
 213 #define FPST_XCO  0x00000400
 214 #define FPST_XCU  0x00000200
 215 #define FPST_XCI  0x00000100
 216
 217 #define FPST_XPV  0x00000010
 218 #define FPST_XPZ  0x00000008
 219 #define FPST_XPO  0x00000004
 220 #define FPST_XPU  0x00000002
 221 #define FPST_XPI  0x00000001
 222
 223 #define FPCFG_RM   0x00000180
 224 #define FPCFG_XEV  0x00000010
 225 #define FPCFG_XEZ  0x00000008
 226 #define FPCFG_XEO  0x00000004
 227 #define FPCFG_XEU  0x00000002
 228 #define FPCFG_XEI  0x00000001
 229
 230 #define GET_FPCC()\
 231  ((FPSR >> 24) &0xf)
 232
 233 #define CLEAR_FPCC(bbb)\
 234   (FPSR &= ~(1 << (bbb+24)))
 235
 236 #define SET_FPCC(bbb)\
 237  (FPSR |= 1 << (bbb+24))
 238
 239 #define TEST_FPCC(bbb)\
 240   ((FPSR & (1 << (bbb+24))) != 0)
 241
 242 #define FPSR_GET_ROUND()                                        \
 243   (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near           \
 244    : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up        \
 245    : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down      \
 246    : sim_fpu_round_zero)
 247
 248
 249 enum FPU_COMPARE {
 250   FPU_CMP_F = 0,
 251   FPU_CMP_UN,
 252   FPU_CMP_EQ,
 253   FPU_CMP_UEQ,
 254   FPU_CMP_OLT,
 255   FPU_CMP_ULT,
 256   FPU_CMP_OLE,
 257   FPU_CMP_ULE,
 258   FPU_CMP_SF,
 259   FPU_CMP_NGLE,
 260   FPU_CMP_SEQ,
 261   FPU_CMP_NGL,
 262   FPU_CMP_LT,
 263   FPU_CMP_NGE,
 264   FPU_CMP_LE,
 265   FPU_CMP_NGT
 266 };
 267
 268
 269 /* MPU */
 270 #define MPM     (MPU1_SR[0])
 271 #define MPC     (MPU1_SR[1])
 272 #define MPC_REGNO 1
 273 #define TID     (MPU1_SR[2])
 274 #define PPA     (MPU1_SR[3])
 275 #define PPM     (MPU1_SR[4])
 276 #define PPC     (MPU1_SR[5])
 277 #define DCC     (MPU1_SR[6])
 278 #define DCV0    (MPU1_SR[7])
 279 #define DCV1    (MPU1_SR[8])
 280 #define SPAL    (MPU1_SR[10])
 281 #define SPAU    (MPU1_SR[11])
 282 #define IPA0L   (MPU1_SR[12])
 283 #define IPA0U   (MPU1_SR[13])
 284 #define IPA1L   (MPU1_SR[14])
 285 #define IPA1U   (MPU1_SR[15])
 286 #define IPA2L   (MPU1_SR[16])
 287 #define IPA2U   (MPU1_SR[17])
 288 #define IPA3L   (MPU1_SR[18])
 289 #define IPA3U   (MPU1_SR[19])
 290 #define DPA0L   (MPU1_SR[20])
 291 #define DPA0U   (MPU1_SR[21])
 292 #define DPA1L   (MPU1_SR[22])
 293 #define DPA1U   (MPU1_SR[23])
 294 #define DPA2L   (MPU1_SR[24])
 295 #define DPA2U   (MPU1_SR[25])
 296 #define DPA3L   (MPU1_SR[26])
 297 #define DPA3U   (MPU1_SR[27])
 298
 299 #define PPC_PPE 0x1
 300 #define SPAL_SPE 0x1
 301 #define SPAL_SPS 0x10
 302
 303 #define VIP     (MPU0_SR[0])
 304 #define VMECR   (MPU0_SR[4])
 305 #define VMTID   (MPU0_SR[5])
 306 #define VMADR   (MPU0_SR[6])
 307 #define VPECR   (MPU0_SR[8])
 308 #define VPTID   (MPU0_SR[9])
 309 #define VPADR   (MPU0_SR[10])
 310 #define VDECR   (MPU0_SR[12])
 311 #define VDTID   (MPU0_SR[13])
 312
 313 #define MPM_AUE 0x2
 314 #define MPM_MPE 0x1
 315
 316 #define VMECR_VMX   0x2
 317 #define VMECR_VMR   0x4
 318 #define VMECR_VMW   0x8
 319 #define VMECR_VMS   0x10
 320 #define VMECR_VMRMW 0x20
 321 #define VMECR_VMMS  0x40
 322
 323 #define IPA2ADDR(IPA)   ((IPA) & 0x1fffff80)
 324 #define IPA_IPE 0x1
 325 #define IPA_IPX 0x2
 326 #define IPA_IPR 0x4
 327 #define IPE0    (IPA0L & IPA_IPE)
 328 #define IPE1    (IPA1L & IPA_IPE)
 329 #define IPE2    (IPA2L & IPA_IPE)
 330 #define IPE3    (IPA3L & IPA_IPE)
 331 #define IPX0    (IPA0L & IPA_IPX)
 332 #define IPX1    (IPA1L & IPA_IPX)
 333 #define IPX2    (IPA2L & IPA_IPX)
 334 #define IPX3    (IPA3L & IPA_IPX)
 335 #define IPR0    (IPA0L & IPA_IPR)
 336 #define IPR1    (IPA1L & IPA_IPR)
 337 #define IPR2    (IPA2L & IPA_IPR)
 338 #define IPR3    (IPA3L & IPA_IPR)
 339
 340 #define DPA2ADDR(DPA)   ((DPA) & 0x1fffff80)
 341 #define DPA_DPE 0x1
 342 #define DPA_DPR 0x4
 343 #define DPA_DPW 0x8
 344 #define DPE0    (DPA0L & DPA_DPE)
 345 #define DPE1    (DPA1L & DPA_DPE)
 346 #define DPE2    (DPA2L & DPA_DPE)
 347 #define DPE3    (DPA3L & DPA_DPE)
 348 #define DPR0    (DPA0L & DPA_DPR)
 349 #define DPR1    (DPA1L & DPA_DPR)
 350 #define DPR2    (DPA2L & DPA_DPR)
 351 #define DPR3    (DPA3L & DPA_DPR)
 352 #define DPW0    (DPA0L & DPA_DPW)
 353 #define DPW1    (DPA1L & DPA_DPW)
 354 #define DPW2    (DPA2L & DPA_DPW)
 355 #define DPW3    (DPA3L & DPA_DPW)
 356
 357 #define DCC_DCE0 0x1
 358 #define DCC_DCE1 0x10000
 359
 360 #define PPA2ADDR(PPA)   ((PPA) & 0x1fffff80)
 361 #define PPC_PPC 0xfffffffe
 362 #define PPC_PPE 0x1
 363 #define PPC_PPM 0x0000fff8
 364
 365
 366 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 367
 368 /* sign-extend a 4-bit number */
 369 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 370
 371 /* sign-extend a 5-bit number */
 372 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 373
 374 /* sign-extend a 9-bit number */
 375 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 376
 377 /* sign-extend a 22-bit number */
 378 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 379
 380 /* sign extend a 40 bit number */
 381 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 382                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 383                          + UNSIGNED64 (0x8000000000))
 384
 385 /* sign extend a 44 bit number */
 386 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 387                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 388                          + UNSIGNED64 (0x80000000000))
 389
 390 /* sign extend a 60 bit number */
 391 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 392                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 393                          + UNSIGNED64 (0x800000000000000))
 394
 395 /* No sign extension */
 396 #define NOP(x)          (x)
 397
 398 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 399
 400 #define RLW(x) load_mem (x, 4)
 401
 402 /* Function declarations.  */
 403
 404 #define IMEM16(EA) \
 405 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 406
 407 #define IMEM16_IMMED(EA,N) \
 408 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 409                          PC, exec_map, (EA) + (N) * 2)
 410
 411 #define load_mem(ADDR,LEN) \
 412 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 413                                PC, read_map, (ADDR))
 414
 415 #define store_mem(ADDR,LEN,DATA) \
 416 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 417                                 PC, write_map, (ADDR), (DATA))
 418
 419
 420 /* compare cccc field against PSW */
 421 int condition_met (unsigned code);
 422
 423
 424 /* Debug/tracing calls */
 425
 426 enum op_types
 427 {
 428   OP_UNKNOWN,
 429   OP_NONE,
 430   OP_TRAP,
 431   OP_REG,
 432   OP_REG_REG,
 433   OP_REG_REG_CMP,
 434   OP_REG_REG_MOVE,
 435   OP_IMM_REG,
 436   OP_IMM_REG_CMP,
 437   OP_IMM_REG_MOVE,
 438   OP_COND_BR,
 439   OP_LOAD16,
 440   OP_STORE16,
 441   OP_LOAD32,
 442   OP_STORE32,
 443   OP_JUMP,
 444   OP_IMM_REG_REG,
 445   OP_UIMM_REG_REG,
 446   OP_IMM16_REG_REG,
 447   OP_UIMM16_REG_REG,
 448   OP_BIT,
 449   OP_EX1,
 450   OP_EX2,
 451   OP_LDSR,
 452   OP_STSR,
 453   OP_BIT_CHANGE,
 454   OP_REG_REG_REG,
 455   OP_REG_REG3,
 456   OP_IMM_REG_REG_REG,
 457   OP_PUSHPOP1,
 458   OP_PUSHPOP2,
 459   OP_PUSHPOP3,
 460 };
 461
 462 #ifdef DEBUG
 463 void trace_input (char *name, enum op_types type, int size);
 464 void trace_output (enum op_types result);
 465 void trace_result (int has_result, unsigned32 result);
 466
 467 extern int trace_num_values;
 468 extern unsigned32 trace_values[];
 469 extern unsigned32 trace_pc;
 470 extern const char *trace_name;
 471 extern int trace_module;
 472
 473 #define TRACE_BRANCH0() \
 474 do { \
 475   if (TRACE_BRANCH_P (CPU)) { \
 476     trace_module = TRACE_BRANCH_IDX; \
 477     trace_pc = cia; \
 478     trace_name = itable[MY_INDEX].name; \
 479     trace_num_values = 0; \
 480     trace_result (1, (nia)); \
 481   } \
 482 } while (0)
 483
 484 #define TRACE_BRANCH1(IN1) \
 485 do { \
 486   if (TRACE_BRANCH_P (CPU)) { \
 487     trace_module = TRACE_BRANCH_IDX; \
 488     trace_pc = cia; \
 489     trace_name = itable[MY_INDEX].name; \
 490     trace_values[0] = (IN1); \
 491     trace_num_values = 1; \
 492     trace_result (1, (nia)); \
 493   } \
 494 } while (0)
 495
 496 #define TRACE_BRANCH2(IN1, IN2) \
 497 do { \
 498   if (TRACE_BRANCH_P (CPU)) { \
 499     trace_module = TRACE_BRANCH_IDX; \
 500     trace_pc = cia; \
 501     trace_name = itable[MY_INDEX].name; \
 502     trace_values[0] = (IN1); \
 503     trace_values[1] = (IN2); \
 504     trace_num_values = 2; \
 505     trace_result (1, (nia)); \
 506   } \
 507 } while (0)
 508
 509 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 510 do { \
 511   if (TRACE_BRANCH_P (CPU)) { \
 512     trace_module = TRACE_BRANCH_IDX; \
 513     trace_pc = cia; \
 514     trace_name = itable[MY_INDEX].name; \
 515     trace_values[0] = (IN1); \
 516     trace_values[1] = (IN2); \
 517     trace_values[2] = (IN3); \
 518     trace_num_values = 3; \
 519     trace_result (1, (nia)); \
 520   } \
 521 } while (0)
 522
 523 #define TRACE_LD(ADDR,RESULT) \
 524 do { \
 525   if (TRACE_MEMORY_P (CPU)) { \
 526     trace_module = TRACE_MEMORY_IDX; \
 527     trace_pc = cia; \
 528     trace_name = itable[MY_INDEX].name; \
 529     trace_values[0] = (ADDR); \
 530     trace_num_values = 1; \
 531     trace_result (1, (RESULT)); \
 532   } \
 533 } while (0)
 534
 535 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
 536 do { \
 537   if (TRACE_MEMORY_P (CPU)) { \
 538     trace_module = TRACE_MEMORY_IDX; \
 539     trace_pc = cia; \
 540     trace_name = (NAME); \
 541     trace_values[0] = (ADDR); \
 542     trace_num_values = 1; \
 543     trace_result (1, (RESULT)); \
 544   } \
 545 } while (0)
 546
 547 #define TRACE_ST(ADDR,RESULT) \
 548 do { \
 549   if (TRACE_MEMORY_P (CPU)) { \
 550     trace_module = TRACE_MEMORY_IDX; \
 551     trace_pc = cia; \
 552     trace_name = itable[MY_INDEX].name; \
 553     trace_values[0] = (ADDR); \
 554     trace_num_values = 1; \
 555     trace_result (1, (RESULT)); \
 556   } \
 557 } while (0)
 558
 559 #define TRACE_FP_INPUT_FPU1(V0) \
 560 do { \
 561   if (TRACE_FPU_P (CPU)) \
 562     { \
 563       unsigned64 f0; \
 564       sim_fpu_to64 (&f0, (V0)); \
 565       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 566     } \
 567 } while (0)
 568
 569 #define TRACE_FP_INPUT_FPU2(V0, V1) \
 570 do { \
 571   if (TRACE_FPU_P (CPU)) \
 572     { \
 573       unsigned64 f0, f1; \
 574       sim_fpu_to64 (&f0, (V0)); \
 575       sim_fpu_to64 (&f1, (V1)); \
 576       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
 577     } \
 578 } while (0)
 579
 580 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
 581 do { \
 582   if (TRACE_FPU_P (CPU)) \
 583     { \
 584       unsigned64 f0, f1, f2; \
 585       sim_fpu_to64 (&f0, (V0)); \
 586       sim_fpu_to64 (&f1, (V1)); \
 587       sim_fpu_to64 (&f2, (V2)); \
 588       trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
 589     } \
 590 } while (0)
 591
 592 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
 593 do { \
 594   if (TRACE_FPU_P (CPU)) \
 595     { \
 596       int d0 = (V0); \
 597       unsigned64 f1, f2; \
 598       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
 599       TRACE_IDX (data) = TRACE_FPU_IDX; \
 600       sim_fpu_to64 (&f1, (V1)); \
 601       sim_fpu_to64 (&f2, (V2)); \
 602       save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
 603       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
 604       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
 605     } \
 606 } while (0)
 607
 608 #define TRACE_FP_INPUT_WORD2(V0, V1) \
 609 do { \
 610   if (TRACE_FPU_P (CPU)) \
 611     trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
 612 } while (0)
 613
 614 #define TRACE_FP_RESULT_FPU1(R0) \
 615 do { \
 616   if (TRACE_FPU_P (CPU)) \
 617     { \
 618       unsigned64 f0; \
 619       sim_fpu_to64 (&f0, (R0)); \
 620       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 621     } \
 622 } while (0)
 623
 624 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
 625
 626 #define TRACE_FP_RESULT_WORD2(R0, R1) \
 627 do { \
 628   if (TRACE_FPU_P (CPU)) \
 629     trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
 630 } while (0)
 631
 632 #else
 633 #define trace_input(NAME, IN1, IN2)
 634 #define trace_output(RESULT)
 635 #define trace_result(HAS_RESULT, RESULT)
 636
 637 #define TRACE_ALU_INPUT0()
 638 #define TRACE_ALU_INPUT1(IN0)
 639 #define TRACE_ALU_INPUT2(IN0, IN1)
 640 #define TRACE_ALU_INPUT2(IN0, IN1)
 641 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
 642 #define TRACE_ALU_RESULT(RESULT)
 643
 644 #define TRACE_BRANCH0()
 645 #define TRACE_BRANCH1(IN1)
 646 #define TRACE_BRANCH2(IN1, IN2)
 647 #define TRACE_BRANCH2(IN1, IN2, IN3)
 648
 649 #define TRACE_LD(ADDR,RESULT)
 650 #define TRACE_ST(ADDR,RESULT)
 651
 652 #endif
 653
 654 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
 655 #define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 656
 657 extern void divun ( unsigned int       N,
 658                     unsigned long int  als,
 659                     unsigned long int  sfi,
 660                     unsigned32 /*unsigned long int*/ *  quotient_ptr,
 661                     unsigned32 /*unsigned long int*/ *  remainder_ptr,
 662                     int *overflow_ptr
 663                     );
 664 extern void divn ( unsigned int       N,
 665                    unsigned long int  als,
 666                    unsigned long int  sfi,
 667                    signed32 /*signed long int*/ *  quotient_ptr,
 668                    signed32 /*signed long int*/ *  remainder_ptr,
 669                    int *overflow_ptr
 670                    );
 671 extern int type1_regs[];
 672 extern int type2_regs[];
 673 extern int type3_regs[];
 674
 675 #define SESR_OV   (1 << 0)
 676 #define SESR_SOV  (1 << 1)
 677
 678 #define SESR      (State.sregs[12])
 679
 680 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
 681 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
 682 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
 683 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
 684
 685 #define SAT16(X)                        \
 686   do                                    \
 687     {                                   \
 688       signed64 z = (X);                 \
 689       if (z > 0x7fff)                   \
 690         {                               \
 691           SESR |= SESR_OV | SESR_SOV;   \
 692           z = 0x7fff;                   \
 693         }                               \
 694       else if (z < -0x8000)             \
 695         {                               \
 696           SESR |= SESR_OV | SESR_SOV;   \
 697           z = - 0x8000;                 \
 698         }                               \
 699       (X) = z;                          \
 700     }                                   \
 701   while (0)
 702
 703 #define SAT32(X)                        \
 704   do                                    \
 705     {                                   \
 706       signed64 z = (X);                 \
 707       if (z > 0x7fffffff)               \
 708         {                               \
 709           SESR |= SESR_OV | SESR_SOV;   \
 710           z = 0x7fffffff;               \
 711         }                               \
 712       else if (z < -0x80000000)         \
 713         {                               \
 714           SESR |= SESR_OV | SESR_SOV;   \
 715           z = - 0x80000000;             \
 716         }                               \
 717       (X) = z;                          \
 718     }                                   \
 719   while (0)
 720
 721 #define ABS16(X)                        \
 722   do                                    \
 723     {                                   \
 724       signed64 z = (X) & 0xffff;        \
 725       if (z == 0x8000)                  \
 726         {                               \
 727           SESR |= SESR_OV | SESR_SOV;   \
 728           z = 0x7fff;                   \
 729         }                               \
 730       else if (z & 0x8000)              \
 731         {                               \
 732           z = (- z) & 0xffff;           \
 733         }                               \
 734       (X) = z;                          \
 735     }                                   \
 736   while (0)
 737
 738 #define ABS32(X)                        \
 739   do                                    \
 740     {                                   \
 741       signed64 z = (X) & 0xffffffff;    \
 742       if (z == 0x80000000)              \
 743         {                               \
 744           SESR |= SESR_OV | SESR_SOV;   \
 745           z = 0x7fffffff;               \
 746         }                               \
 747       else if (z & 0x80000000)          \
 748         {                               \
 749           z = (- z) & 0xffffffff;       \
 750         }                               \
 751       (X) = z;                          \
 752     }                                   \
 753   while (0)
 754
 755 #endif