sim/v850/sim-main.h

   1 #ifndef SIM_MAIN_H
   2 #define SIM_MAIN_H
   3
   4 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
   5
   6 #define WITH_TARGET_WORD_MSB 31
   7
   8 #include "sim-basics.h"
   9 #include "sim-signal.h"
  10 #include "sim-fpu.h"
  11 #include "sim-base.h"
  12
  13 #include "simops.h"
  14 #include "bfd.h"
  15
  16
  17 typedef uint32_t reg_t;
  18 typedef uint64_t reg64_t;
  19
  20
  21 /* The current state of the processor; registers, memory, etc.  */
  22
  23 typedef struct _v850_regs {
  24   reg_t regs[32];               /* general-purpose registers */
  25   reg_t sregs[32];              /* system registers, including psw */
  26   reg_t pc;
  27   int dummy_mem;                /* where invalid accesses go */
  28   reg_t mpu0_sregs[28];         /* mpu0 system registers */
  29   reg_t mpu1_sregs[28];         /* mpu1 system registers */
  30   reg_t fpu_sregs[28];          /* fpu system registers */
  31   reg_t selID_sregs[7][32];     /* system registers, selID 1 thru selID 7 */
  32   reg64_t vregs[32];            /* vector registers.  */
  33 } v850_regs;
  34
  35 struct _sim_cpu
  36 {
  37   /* ... simulator specific members ... */
  38   v850_regs reg;
  39   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  40   sim_event *pending_nmi;
  41   /* ... base type ... */
  42   sim_cpu_base base;
  43 };
  44
  45 /* For compatibility, until all functions converted to passing
  46    SIM_DESC as an argument */
  47 extern SIM_DESC simulator;
  48
  49
  50 #define V850_ROM_SIZE 0x8000
  51 #define V850_LOW_END 0x200000
  52 #define V850_HIGH_START 0xffe000
  53
  54
  55 /* Because we are still using the old semantic table, provide compat
  56    macro's that store the instruction where the old simops expects
  57    it. */
  58
  59 extern uint32_t OP[4];
  60 #if 0
  61 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  62 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  63 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
  64 OP[3] = inst;
  65 #endif
  66
  67 #define SAVE_1 \
  68 PC = cia; \
  69 OP[0] = instruction_0 & 0x1f; \
  70 OP[1] = (instruction_0 >> 11) & 0x1f; \
  71 OP[2] = 0; \
  72 OP[3] = instruction_0
  73
  74 #define COMPAT_1(CALL) \
  75 SAVE_1; \
  76 PC += (CALL); \
  77 nia = PC
  78
  79 #define SAVE_2 \
  80 PC = cia; \
  81 OP[0] = instruction_0 & 0x1f; \
  82 OP[1] = (instruction_0 >> 11) & 0x1f; \
  83 OP[2] = instruction_1; \
  84 OP[3] = (instruction_1 << 16) | instruction_0
  85
  86 #define COMPAT_2(CALL) \
  87 SAVE_2; \
  88 PC += (CALL); \
  89 nia = PC
  90
  91
  92 /* new */
  93 #define GR  ((CPU)->reg.regs)
  94 #define SR  ((CPU)->reg.sregs)
  95 #define VR  ((CPU)->reg.vregs)
  96 #define MPU0_SR  ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
  97 #define MPU1_SR  ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
  98 #define FPU_SR   ((STATE_CPU (sd, 0))->reg.fpu_sregs)
  99
 100 /* old */
 101 #define State    (STATE_CPU (simulator, 0)->reg)
 102 #define PC      (State.pc)
 103 #define SP_REGNO        3
 104 #define SP      (State.regs[SP_REGNO])
 105 #define EP      (State.regs[30])
 106
 107 #define EIPC  (State.sregs[0])
 108 #define EIPSW (State.sregs[1])
 109 #define FEPC  (State.sregs[2])
 110 #define FEPSW (State.sregs[3])
 111 #define ECR   (State.sregs[4])
 112 #define PSW   (State.sregs[5])
 113 #define PSW_REGNO   5
 114 #define EIIC  (State.sregs[13])
 115 #define FEIC  (State.sregs[14])
 116 #define DBIC  (SR[15])
 117 #define CTPC  (SR[16])
 118 #define CTPSW (SR[17])
 119 #define DBPC  (State.sregs[18])
 120 #define DBPSW (State.sregs[19])
 121 #define CTBP  (State.sregs[20])
 122 #define DIR   (SR[21])
 123 #define EIWR  (SR[28])
 124 #define FEWR  (SR[29])
 125 #define DBWR  (SR[30])
 126 #define BSEL  (SR[31])
 127
 128 #define PSW_US BIT32 (8)
 129 #define PSW_NP 0x80
 130 #define PSW_EP 0x40
 131 #define PSW_ID 0x20
 132 #define PSW_SAT 0x10
 133 #define PSW_CY 0x8
 134 #define PSW_OV 0x4
 135 #define PSW_S 0x2
 136 #define PSW_Z 0x1
 137
 138 #define PSW_NPV (1<<18)
 139 #define PSW_DMP (1<<17)
 140 #define PSW_IMP (1<<16)
 141
 142 #define ECR_EICC 0x0000ffff
 143 #define ECR_FECC 0xffff0000
 144
 145 /* FPU */
 146
 147 #define FPSR  (FPU_SR[6])
 148 #define FPSR_REGNO 6
 149 #define FPEPC (FPU_SR[7])
 150 #define FPST  (FPU_SR[8])
 151 #define FPST_REGNO 8
 152 #define FPCC  (FPU_SR[9])
 153 #define FPCFG (FPU_SR[10])
 154 #define FPCFG_REGNO 10
 155
 156 #define FPSR_DEM  0x00200000
 157 #define FPSR_SEM  0x00100000
 158 #define FPSR_RM   0x000c0000
 159 #define FPSR_RN   0x00000000
 160 #define FPSR_FS   0x00020000
 161 #define FPSR_PR   0x00010000
 162
 163 #define FPSR_XC   0x0000fc00
 164 #define FPSR_XCE  0x00008000
 165 #define FPSR_XCV  0x00004000
 166 #define FPSR_XCZ  0x00002000
 167 #define FPSR_XCO  0x00001000
 168 #define FPSR_XCU  0x00000800
 169 #define FPSR_XCI  0x00000400
 170
 171 #define FPSR_XE   0x000003e0
 172 #define FPSR_XEV  0x00000200
 173 #define FPSR_XEZ  0x00000100
 174 #define FPSR_XEO  0x00000080
 175 #define FPSR_XEU  0x00000040
 176 #define FPSR_XEI  0x00000020
 177
 178 #define FPSR_XP   0x0000001f
 179 #define FPSR_XPV  0x00000010
 180 #define FPSR_XPZ  0x00000008
 181 #define FPSR_XPO  0x00000004
 182 #define FPSR_XPU  0x00000002
 183 #define FPSR_XPI  0x00000001
 184
 185 #define FPST_PR   0x00008000
 186 #define FPST_XCE  0x00002000
 187 #define FPST_XCV  0x00001000
 188 #define FPST_XCZ  0x00000800
 189 #define FPST_XCO  0x00000400
 190 #define FPST_XCU  0x00000200
 191 #define FPST_XCI  0x00000100
 192
 193 #define FPST_XPV  0x00000010
 194 #define FPST_XPZ  0x00000008
 195 #define FPST_XPO  0x00000004
 196 #define FPST_XPU  0x00000002
 197 #define FPST_XPI  0x00000001
 198
 199 #define FPCFG_RM   0x00000180
 200 #define FPCFG_XEV  0x00000010
 201 #define FPCFG_XEZ  0x00000008
 202 #define FPCFG_XEO  0x00000004
 203 #define FPCFG_XEU  0x00000002
 204 #define FPCFG_XEI  0x00000001
 205
 206 #define GET_FPCC()\
 207  ((FPSR >> 24) &0xf)
 208
 209 #define CLEAR_FPCC(bbb)\
 210   (FPSR &= ~(1 << (bbb+24)))
 211
 212 #define SET_FPCC(bbb)\
 213  (FPSR |= 1 << (bbb+24))
 214
 215 #define TEST_FPCC(bbb)\
 216   ((FPSR & (1 << (bbb+24))) != 0)
 217
 218 #define FPSR_GET_ROUND()                                        \
 219   (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near           \
 220    : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up        \
 221    : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down      \
 222    : sim_fpu_round_zero)
 223
 224
 225 enum FPU_COMPARE {
 226   FPU_CMP_F = 0,
 227   FPU_CMP_UN,
 228   FPU_CMP_EQ,
 229   FPU_CMP_UEQ,
 230   FPU_CMP_OLT,
 231   FPU_CMP_ULT,
 232   FPU_CMP_OLE,
 233   FPU_CMP_ULE,
 234   FPU_CMP_SF,
 235   FPU_CMP_NGLE,
 236   FPU_CMP_SEQ,
 237   FPU_CMP_NGL,
 238   FPU_CMP_LT,
 239   FPU_CMP_NGE,
 240   FPU_CMP_LE,
 241   FPU_CMP_NGT
 242 };
 243
 244
 245 /* MPU */
 246 #define MPM     (MPU1_SR[0])
 247 #define MPC     (MPU1_SR[1])
 248 #define MPC_REGNO 1
 249 #define TID     (MPU1_SR[2])
 250 #define PPA     (MPU1_SR[3])
 251 #define PPM     (MPU1_SR[4])
 252 #define PPC     (MPU1_SR[5])
 253 #define DCC     (MPU1_SR[6])
 254 #define DCV0    (MPU1_SR[7])
 255 #define DCV1    (MPU1_SR[8])
 256 #define SPAL    (MPU1_SR[10])
 257 #define SPAU    (MPU1_SR[11])
 258 #define IPA0L   (MPU1_SR[12])
 259 #define IPA0U   (MPU1_SR[13])
 260 #define IPA1L   (MPU1_SR[14])
 261 #define IPA1U   (MPU1_SR[15])
 262 #define IPA2L   (MPU1_SR[16])
 263 #define IPA2U   (MPU1_SR[17])
 264 #define IPA3L   (MPU1_SR[18])
 265 #define IPA3U   (MPU1_SR[19])
 266 #define DPA0L   (MPU1_SR[20])
 267 #define DPA0U   (MPU1_SR[21])
 268 #define DPA1L   (MPU1_SR[22])
 269 #define DPA1U   (MPU1_SR[23])
 270 #define DPA2L   (MPU1_SR[24])
 271 #define DPA2U   (MPU1_SR[25])
 272 #define DPA3L   (MPU1_SR[26])
 273 #define DPA3U   (MPU1_SR[27])
 274
 275 #define PPC_PPE 0x1
 276 #define SPAL_SPE 0x1
 277 #define SPAL_SPS 0x10
 278
 279 #define VIP     (MPU0_SR[0])
 280 #define VMECR   (MPU0_SR[4])
 281 #define VMTID   (MPU0_SR[5])
 282 #define VMADR   (MPU0_SR[6])
 283 #define VPECR   (MPU0_SR[8])
 284 #define VPTID   (MPU0_SR[9])
 285 #define VPADR   (MPU0_SR[10])
 286 #define VDECR   (MPU0_SR[12])
 287 #define VDTID   (MPU0_SR[13])
 288
 289 #define MPM_AUE 0x2
 290 #define MPM_MPE 0x1
 291
 292 #define VMECR_VMX   0x2
 293 #define VMECR_VMR   0x4
 294 #define VMECR_VMW   0x8
 295 #define VMECR_VMS   0x10
 296 #define VMECR_VMRMW 0x20
 297 #define VMECR_VMMS  0x40
 298
 299 #define IPA2ADDR(IPA)   ((IPA) & 0x1fffff80)
 300 #define IPA_IPE 0x1
 301 #define IPA_IPX 0x2
 302 #define IPA_IPR 0x4
 303 #define IPE0    (IPA0L & IPA_IPE)
 304 #define IPE1    (IPA1L & IPA_IPE)
 305 #define IPE2    (IPA2L & IPA_IPE)
 306 #define IPE3    (IPA3L & IPA_IPE)
 307 #define IPX0    (IPA0L & IPA_IPX)
 308 #define IPX1    (IPA1L & IPA_IPX)
 309 #define IPX2    (IPA2L & IPA_IPX)
 310 #define IPX3    (IPA3L & IPA_IPX)
 311 #define IPR0    (IPA0L & IPA_IPR)
 312 #define IPR1    (IPA1L & IPA_IPR)
 313 #define IPR2    (IPA2L & IPA_IPR)
 314 #define IPR3    (IPA3L & IPA_IPR)
 315
 316 #define DPA2ADDR(DPA)   ((DPA) & 0x1fffff80)
 317 #define DPA_DPE 0x1
 318 #define DPA_DPR 0x4
 319 #define DPA_DPW 0x8
 320 #define DPE0    (DPA0L & DPA_DPE)
 321 #define DPE1    (DPA1L & DPA_DPE)
 322 #define DPE2    (DPA2L & DPA_DPE)
 323 #define DPE3    (DPA3L & DPA_DPE)
 324 #define DPR0    (DPA0L & DPA_DPR)
 325 #define DPR1    (DPA1L & DPA_DPR)
 326 #define DPR2    (DPA2L & DPA_DPR)
 327 #define DPR3    (DPA3L & DPA_DPR)
 328 #define DPW0    (DPA0L & DPA_DPW)
 329 #define DPW1    (DPA1L & DPA_DPW)
 330 #define DPW2    (DPA2L & DPA_DPW)
 331 #define DPW3    (DPA3L & DPA_DPW)
 332
 333 #define DCC_DCE0 0x1
 334 #define DCC_DCE1 0x10000
 335
 336 #define PPA2ADDR(PPA)   ((PPA) & 0x1fffff80)
 337 #define PPC_PPC 0xfffffffe
 338 #define PPC_PPE 0x1
 339 #define PPC_PPM 0x0000fff8
 340
 341
 342 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 343
 344 /* sign-extend a 4-bit number */
 345 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 346
 347 /* sign-extend a 5-bit number */
 348 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 349
 350 /* sign-extend a 9-bit number */
 351 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 352
 353 /* sign-extend a 22-bit number */
 354 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 355
 356 /* sign extend a 40 bit number */
 357 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 358                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 359                          + UNSIGNED64 (0x8000000000))
 360
 361 /* sign extend a 44 bit number */
 362 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 363                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 364                          + UNSIGNED64 (0x80000000000))
 365
 366 /* sign extend a 60 bit number */
 367 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 368                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 369                          + UNSIGNED64 (0x800000000000000))
 370
 371 /* No sign extension */
 372 #define NOP(x)          (x)
 373
 374 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 375
 376 #define RLW(x) load_mem (x, 4)
 377
 378 /* Function declarations.  */
 379
 380 #define IMEM16(EA) \
 381 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 382
 383 #define IMEM16_IMMED(EA,N) \
 384 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 385                          PC, exec_map, (EA) + (N) * 2)
 386
 387 #define load_mem(ADDR,LEN) \
 388 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 389                                PC, read_map, (ADDR))
 390
 391 #define store_mem(ADDR,LEN,DATA) \
 392 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 393                                 PC, write_map, (ADDR), (DATA))
 394
 395
 396 /* compare cccc field against PSW */
 397 int condition_met (unsigned code);
 398
 399
 400 /* Debug/tracing calls */
 401
 402 enum op_types
 403 {
 404   OP_UNKNOWN,
 405   OP_NONE,
 406   OP_TRAP,
 407   OP_REG,
 408   OP_REG_REG,
 409   OP_REG_REG_CMP,
 410   OP_REG_REG_MOVE,
 411   OP_IMM_REG,
 412   OP_IMM_REG_CMP,
 413   OP_IMM_REG_MOVE,
 414   OP_COND_BR,
 415   OP_LOAD16,
 416   OP_STORE16,
 417   OP_LOAD32,
 418   OP_STORE32,
 419   OP_JUMP,
 420   OP_IMM_REG_REG,
 421   OP_UIMM_REG_REG,
 422   OP_IMM16_REG_REG,
 423   OP_UIMM16_REG_REG,
 424   OP_BIT,
 425   OP_EX1,
 426   OP_EX2,
 427   OP_LDSR,
 428   OP_STSR,
 429   OP_BIT_CHANGE,
 430   OP_REG_REG_REG,
 431   OP_REG_REG3,
 432   OP_IMM_REG_REG_REG,
 433   OP_PUSHPOP1,
 434   OP_PUSHPOP2,
 435   OP_PUSHPOP3,
 436 };
 437
 438 #ifdef DEBUG
 439 void trace_input (char *name, enum op_types type, int size);
 440 void trace_output (enum op_types result);
 441 void trace_result (int has_result, uint32_t result);
 442
 443 extern int trace_num_values;
 444 extern uint32_t trace_values[];
 445 extern uint32_t trace_pc;
 446 extern const char *trace_name;
 447 extern int trace_module;
 448
 449 #define TRACE_BRANCH0() \
 450 do { \
 451   if (TRACE_BRANCH_P (CPU)) { \
 452     trace_module = TRACE_BRANCH_IDX; \
 453     trace_pc = cia; \
 454     trace_name = itable[MY_INDEX].name; \
 455     trace_num_values = 0; \
 456     trace_result (1, (nia)); \
 457   } \
 458 } while (0)
 459
 460 #define TRACE_BRANCH1(IN1) \
 461 do { \
 462   if (TRACE_BRANCH_P (CPU)) { \
 463     trace_module = TRACE_BRANCH_IDX; \
 464     trace_pc = cia; \
 465     trace_name = itable[MY_INDEX].name; \
 466     trace_values[0] = (IN1); \
 467     trace_num_values = 1; \
 468     trace_result (1, (nia)); \
 469   } \
 470 } while (0)
 471
 472 #define TRACE_BRANCH2(IN1, IN2) \
 473 do { \
 474   if (TRACE_BRANCH_P (CPU)) { \
 475     trace_module = TRACE_BRANCH_IDX; \
 476     trace_pc = cia; \
 477     trace_name = itable[MY_INDEX].name; \
 478     trace_values[0] = (IN1); \
 479     trace_values[1] = (IN2); \
 480     trace_num_values = 2; \
 481     trace_result (1, (nia)); \
 482   } \
 483 } while (0)
 484
 485 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 486 do { \
 487   if (TRACE_BRANCH_P (CPU)) { \
 488     trace_module = TRACE_BRANCH_IDX; \
 489     trace_pc = cia; \
 490     trace_name = itable[MY_INDEX].name; \
 491     trace_values[0] = (IN1); \
 492     trace_values[1] = (IN2); \
 493     trace_values[2] = (IN3); \
 494     trace_num_values = 3; \
 495     trace_result (1, (nia)); \
 496   } \
 497 } while (0)
 498
 499 #define TRACE_LD(ADDR,RESULT) \
 500 do { \
 501   if (TRACE_MEMORY_P (CPU)) { \
 502     trace_module = TRACE_MEMORY_IDX; \
 503     trace_pc = cia; \
 504     trace_name = itable[MY_INDEX].name; \
 505     trace_values[0] = (ADDR); \
 506     trace_num_values = 1; \
 507     trace_result (1, (RESULT)); \
 508   } \
 509 } while (0)
 510
 511 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
 512 do { \
 513   if (TRACE_MEMORY_P (CPU)) { \
 514     trace_module = TRACE_MEMORY_IDX; \
 515     trace_pc = cia; \
 516     trace_name = (NAME); \
 517     trace_values[0] = (ADDR); \
 518     trace_num_values = 1; \
 519     trace_result (1, (RESULT)); \
 520   } \
 521 } while (0)
 522
 523 #define TRACE_ST(ADDR,RESULT) \
 524 do { \
 525   if (TRACE_MEMORY_P (CPU)) { \
 526     trace_module = TRACE_MEMORY_IDX; \
 527     trace_pc = cia; \
 528     trace_name = itable[MY_INDEX].name; \
 529     trace_values[0] = (ADDR); \
 530     trace_num_values = 1; \
 531     trace_result (1, (RESULT)); \
 532   } \
 533 } while (0)
 534
 535 #define TRACE_FP_INPUT_FPU1(V0) \
 536 do { \
 537   if (TRACE_FPU_P (CPU)) \
 538     { \
 539       uint64_t f0; \
 540       sim_fpu_to64 (&f0, (V0)); \
 541       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 542     } \
 543 } while (0)
 544
 545 #define TRACE_FP_INPUT_FPU2(V0, V1) \
 546 do { \
 547   if (TRACE_FPU_P (CPU)) \
 548     { \
 549       uint64_t f0, f1; \
 550       sim_fpu_to64 (&f0, (V0)); \
 551       sim_fpu_to64 (&f1, (V1)); \
 552       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
 553     } \
 554 } while (0)
 555
 556 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
 557 do { \
 558   if (TRACE_FPU_P (CPU)) \
 559     { \
 560       uint64_t f0, f1, f2; \
 561       sim_fpu_to64 (&f0, (V0)); \
 562       sim_fpu_to64 (&f1, (V1)); \
 563       sim_fpu_to64 (&f2, (V2)); \
 564       trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
 565     } \
 566 } while (0)
 567
 568 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
 569 do { \
 570   if (TRACE_FPU_P (CPU)) \
 571     { \
 572       int d0 = (V0); \
 573       uint64_t f1, f2; \
 574       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
 575       TRACE_IDX (data) = TRACE_FPU_IDX; \
 576       sim_fpu_to64 (&f1, (V1)); \
 577       sim_fpu_to64 (&f2, (V2)); \
 578       save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
 579       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
 580       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
 581     } \
 582 } while (0)
 583
 584 #define TRACE_FP_INPUT_WORD2(V0, V1) \
 585 do { \
 586   if (TRACE_FPU_P (CPU)) \
 587     trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
 588 } while (0)
 589
 590 #define TRACE_FP_RESULT_FPU1(R0) \
 591 do { \
 592   if (TRACE_FPU_P (CPU)) \
 593     { \
 594       uint64_t f0; \
 595       sim_fpu_to64 (&f0, (R0)); \
 596       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 597     } \
 598 } while (0)
 599
 600 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
 601
 602 #define TRACE_FP_RESULT_WORD2(R0, R1) \
 603 do { \
 604   if (TRACE_FPU_P (CPU)) \
 605     trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
 606 } while (0)
 607
 608 #else
 609 #define trace_input(NAME, IN1, IN2)
 610 #define trace_output(RESULT)
 611 #define trace_result(HAS_RESULT, RESULT)
 612
 613 #define TRACE_ALU_INPUT0()
 614 #define TRACE_ALU_INPUT1(IN0)
 615 #define TRACE_ALU_INPUT2(IN0, IN1)
 616 #define TRACE_ALU_INPUT2(IN0, IN1)
 617 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
 618 #define TRACE_ALU_RESULT(RESULT)
 619
 620 #define TRACE_BRANCH0()
 621 #define TRACE_BRANCH1(IN1)
 622 #define TRACE_BRANCH2(IN1, IN2)
 623 #define TRACE_BRANCH2(IN1, IN2, IN3)
 624
 625 #define TRACE_LD(ADDR,RESULT)
 626 #define TRACE_ST(ADDR,RESULT)
 627
 628 #endif
 629
 630 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
 631 #define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 632
 633 extern void divun ( unsigned int       N,
 634                     unsigned long int  als,
 635                     unsigned long int  sfi,
 636                     uint32_t /*unsigned long int*/ *  quotient_ptr,
 637                     uint32_t /*unsigned long int*/ *  remainder_ptr,
 638                     int *overflow_ptr
 639                     );
 640 extern void divn ( unsigned int       N,
 641                    unsigned long int  als,
 642                    unsigned long int  sfi,
 643                    int32_t /*signed long int*/ *  quotient_ptr,
 644                    int32_t /*signed long int*/ *  remainder_ptr,
 645                    int *overflow_ptr
 646                    );
 647 extern int type1_regs[];
 648 extern int type2_regs[];
 649 extern int type3_regs[];
 650
 651 #define SESR_OV   (1 << 0)
 652 #define SESR_SOV  (1 << 1)
 653
 654 #define SESR      (State.sregs[12])
 655
 656 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
 657 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
 658 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
 659 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
 660
 661 #define SAT16(X)                        \
 662   do                                    \
 663     {                                   \
 664       int64_t z = (X);                  \
 665       if (z > 0x7fff)                   \
 666         {                               \
 667           SESR |= SESR_OV | SESR_SOV;   \
 668           z = 0x7fff;                   \
 669         }                               \
 670       else if (z < -0x8000)             \
 671         {                               \
 672           SESR |= SESR_OV | SESR_SOV;   \
 673           z = - 0x8000;                 \
 674         }                               \
 675       (X) = z;                          \
 676     }                                   \
 677   while (0)
 678
 679 #define SAT32(X)                        \
 680   do                                    \
 681     {                                   \
 682       int64_t z = (X);                  \
 683       if (z > 0x7fffffff)               \
 684         {                               \
 685           SESR |= SESR_OV | SESR_SOV;   \
 686           z = 0x7fffffff;               \
 687         }                               \
 688       else if (z < -0x80000000)         \
 689         {                               \
 690           SESR |= SESR_OV | SESR_SOV;   \
 691           z = - 0x80000000;             \
 692         }                               \
 693       (X) = z;                          \
 694     }                                   \
 695   while (0)
 696
 697 #define ABS16(X)                        \
 698   do                                    \
 699     {                                   \
 700       int64_t z = (X) & 0xffff; \
 701       if (z == 0x8000)                  \
 702         {                               \
 703           SESR |= SESR_OV | SESR_SOV;   \
 704           z = 0x7fff;                   \
 705         }                               \
 706       else if (z & 0x8000)              \
 707         {                               \
 708           z = (- z) & 0xffff;           \
 709         }                               \
 710       (X) = z;                          \
 711     }                                   \
 712   while (0)
 713
 714 #define ABS32(X)                        \
 715   do                                    \
 716     {                                   \
 717       int64_t z = (X) & 0xffffffff;     \
 718       if (z == 0x80000000)              \
 719         {                               \
 720           SESR |= SESR_OV | SESR_SOV;   \
 721           z = 0x7fffffff;               \
 722         }                               \
 723       else if (z & 0x80000000)          \
 724         {                               \
 725           z = (- z) & 0xffffffff;       \
 726         }                               \
 727       (X) = z;                          \
 728     }                                   \
 729   while (0)
 730
 731 #endif