2 #define WITH_MODULO_MEMORY 1
3 #define WITH_WATCHPOINTS 1
4 #define WITH_TARGET_WORD_MSB 31
6 #include "sim-basics.h"
9 typedef address_word sim_cia
;
12 /* This simulator doesn't cache state */
13 #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
14 #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
16 /* Get the number of instructions. FIXME: must be a more elegant way
19 #define MAX_INSNS (nr_itable_entries)
20 #define INSN_NAME(i) itable[(i)].name
29 typedef unsigned8 uint8
;
30 typedef signed16 int16
;
31 typedef unsigned16 uint16
;
32 typedef signed32 int32
;
33 typedef unsigned32 uint32
;
34 typedef unsigned32 reg_t
;
37 /* The current state of the processor; registers, memory, etc. */
39 typedef struct _v850_regs
{
40 reg_t regs
[32]; /* general-purpose registers */
41 reg_t sregs
[32]; /* system registers, including psw */
43 int dummy_mem
; /* where invalid accesses go */
49 /* ... simulator specific members ... */
51 reg_t psw_mask
; /* only allow non-reserved bits to be set */
52 /* ... base type ... */
56 #define CPU_CIA(CPU) ((CPU)->reg.pc)
59 sim_cpu cpu
[MAX_NR_PROCESSORS
];
61 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
63 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
75 /* For compatibility, until all functions converted to passing
76 SIM_DESC as an argument */
77 extern SIM_DESC simulator
;
80 #define V850_ROM_SIZE 0x8000
81 #define V850_LOW_END 0x200000
82 #define V850_HIGH_START 0xffe000
85 #define SIG_V850_EXIT -1 /* indication of a normal exit */
89 /* Because we are still using the old semantic table, provide compat
90 macro's that store the instruction where the old simops expects
94 OP
[0] = inst
& 0x1f; /* RRRRR -> reg1 */
95 OP
[1] = (inst
>> 11) & 0x1f; /* rrrrr -> reg2 */
96 OP
[2] = (inst
>> 16) & 0xffff; /* wwwww -> reg3 */
102 OP[0] = instruction_0 & 0x1f; \
103 OP[1] = (instruction_0 >> 11) & 0x1f; \
105 OP[3] = instruction_0
107 #define COMPAT_1(CALL) \
114 OP[0] = instruction_0 & 0x1f; \
115 OP[1] = (instruction_0 >> 11) & 0x1f; \
116 OP[2] = instruction_1; \
117 OP[3] = (instruction_1 << 16) | instruction_0
119 #define COMPAT_2(CALL) \
126 extern struct simops Simops
[];
129 #define State (STATE_CPU (simulator, 0)->reg)
130 #define PC (State.pc)
131 #define SP (State.regs[3])
132 #define EP (State.regs[30])
134 #define EIPC (State.sregs[0])
135 #define EIPSW (State.sregs[1])
136 #define FEPC (State.sregs[2])
137 #define FEPSW (State.sregs[3])
138 #define ECR (State.sregs[4])
139 #define PSW (State.sregs[5])
140 /* start-sanitize-v850e */
141 #define CTPC (State.sregs[16])
142 #define CTPSW (State.sregs[17])
143 /* end-sanitize-v850e */
144 #define DBPC (State.sregs[18])
145 #define DBPSW (State.sregs[19])
146 /* start-sanitize-v850e */
147 #define CTBP (State.sregs[20])
148 /* end-sanitize-v850e */
150 /* start-sanitize-v850eq */
151 #define PSW_US BIT32 (8)
152 /* end-sanitize-v850eq */
162 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
164 /* sign-extend a 4-bit number */
165 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
167 /* sign-extend a 5-bit number */
168 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
170 /* sign-extend a 9-bit number */
171 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
173 /* sign-extend a 22-bit number */
174 #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
176 /* sign extend a 40 bit number */
177 #define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
178 ^ (~UNSIGNED64 (0x7fffffffff))) \
179 + UNSIGNED64 (0x8000000000))
181 /* sign extend a 44 bit number */
182 #define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
183 ^ (~ UNSIGNED64 (0x7ffffffffff))) \
184 + UNSIGNED64 (0x80000000000))
186 /* sign extend a 60 bit number */
187 #define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
188 ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
189 + UNSIGNED64 (0x800000000000000))
191 /* No sign extension */
194 #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
196 #define RLW(x) load_mem (x, 4)
207 /* Function declarations. */
210 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
211 PC, sim_core_execute_map, (EA))
213 #define IMEM_IMMED(EA,N) \
214 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
215 PC, sim_core_execute_map, (EA) + (N) * 2)
217 #define load_mem(ADDR,LEN) \
218 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
219 PC, sim_core_read_map, (ADDR))
221 #define store_mem(ADDR,LEN,DATA) \
222 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
223 PC, sim_core_write_map, (ADDR), (DATA))
226 /* Debug/tracing calls */
253 /* start-sanitize-v850e */
257 /* end-sanitize-v850e */
258 /* start-sanitize-v850eq */
263 /* end-sanitize-v850eq */
267 void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
268 void trace_output
PARAMS ((enum op_types result
));
270 #define trace_input(NAME, IN1, IN2)
271 #define trace_output(RESULT)
275 /* start-sanitize-v850eq */
276 extern void divun ( unsigned int N
,
277 unsigned long int als
,
278 unsigned long int sfi
,
279 unsigned long int * quotient_ptr
,
280 unsigned long int * remainder_ptr
,
281 boolean
* overflow_ptr
283 extern void divn ( unsigned int N
,
284 unsigned long int als
,
285 unsigned long int sfi
,
286 signed long int * quotient_ptr
,
287 signed long int * remainder_ptr
,
288 boolean
* overflow_ptr
290 /* end-sanitize-v850eq */
291 /* start-sanitize-v850e */
292 extern int type1_regs
[];
293 extern int type2_regs
[];
294 /* end-sanitize-v850e */
295 /* start-sanitize-v850eq */
296 extern int type3_regs
[];
297 /* end-sanitize-v850eq */