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29149c648233e6f06f8e30338508e25a17c67f56
[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "sim-main.h"
3 #include "v850_sim.h"
4 #include "simops.h"
5
6 #ifdef HAVE_UTIME_H
7 #include <utime.h>
8 #endif
9
10 #ifdef HAVE_TIME_H
11 #include <time.h>
12 #endif
13
14 /* FIXME - should be including a version of syscall.h that does not
15 pollute the name space */
16 #include "../../libgloss/v850/sys/syscall.h"
17
18 #include "bfd.h"
19 #include <errno.h>
20 #if !defined(__GO32__) && !defined(_WIN32)
21 #include <sys/stat.h>
22 #include <sys/times.h>
23 #include <sys/time.h>
24 #endif
25
26 enum op_types
27 {
28 OP_UNKNOWN,
29 OP_NONE,
30 OP_TRAP,
31 OP_REG,
32 OP_REG_REG,
33 OP_REG_REG_CMP,
34 OP_REG_REG_MOVE,
35 OP_IMM_REG,
36 OP_IMM_REG_CMP,
37 OP_IMM_REG_MOVE,
38 OP_COND_BR,
39 OP_LOAD16,
40 OP_STORE16,
41 OP_LOAD32,
42 OP_STORE32,
43 OP_JUMP,
44 OP_IMM_REG_REG,
45 OP_UIMM_REG_REG,
46 OP_BIT,
47 OP_EX1,
48 OP_EX2,
49 OP_LDSR,
50 OP_STSR,
51 /* start-sanitize-v850e */
52 OP_BIT_CHANGE,
53 OP_REG_REG_REG,
54 OP_REG_REG3,
55 /* end-sanitize-v850e */
56 /* start-sanitize-v850eq */
57 OP_IMM_REG_REG_REG,
58 OP_PUSHPOP1,
59 OP_PUSHPOP2,
60 OP_PUSHPOP3,
61 /* end-sanitize-v850eq */
62 };
63
64 /* start-sanitize-v850e */
65 /* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
66 static int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
67 /* end-sanitize-v850e */
68 /* start-sanitize-v850eq */
69 /* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
70 static int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
71 /* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
72 static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
73 /* end-sanitize-v850eq */
74
75 #ifdef DEBUG
76 static void trace_input PARAMS ((char *name, enum op_types type, int size));
77 static void trace_output PARAMS ((enum op_types result));
78 static int init_text_p = 0;
79 static asection *text;
80 static bfd_vma text_start;
81 static bfd_vma text_end;
82 extern bfd *prog_bfd;
83
84 #ifndef SIZE_INSTRUCTION
85 #define SIZE_INSTRUCTION 6
86 #endif
87
88 #ifndef SIZE_OPERANDS
89 #define SIZE_OPERANDS 16
90 #endif
91
92 #ifndef SIZE_VALUES
93 #define SIZE_VALUES 11
94 #endif
95
96 #ifndef SIZE_LOCATION
97 #define SIZE_LOCATION 40
98 #endif
99
100
101 static void
102 trace_input (name, type, size)
103 char *name;
104 enum op_types type;
105 int size;
106 {
107 char buf[1024];
108 char *p;
109 uint32 values[3];
110 int num_values, i;
111 char *cond;
112 asection *s;
113 const char *filename;
114 const char *functionname;
115 unsigned int linenumber;
116
117 if ((v850_debug & DEBUG_TRACE) == 0)
118 return;
119
120 buf[0] = '\0';
121 if (!init_text_p)
122 {
123 init_text_p = 1;
124 for (s = prog_bfd->sections; s; s = s->next)
125 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
126 {
127 text = s;
128 text_start = bfd_get_section_vma (prog_bfd, s);
129 text_end = text_start + bfd_section_size (prog_bfd, s);
130 break;
131 }
132 }
133
134 if (text && PC >= text_start && PC < text_end)
135 {
136 filename = (const char *)0;
137 functionname = (const char *)0;
138 linenumber = 0;
139 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
140 &filename, &functionname, &linenumber))
141 {
142 p = buf;
143 if (linenumber)
144 {
145 sprintf (p, "Line %5d ", linenumber);
146 p += strlen (p);
147 }
148
149 if (functionname)
150 {
151 sprintf (p, "Func %s ", functionname);
152 p += strlen (p);
153 }
154 else if (filename)
155 {
156 char *q = (char *) strrchr (filename, '/');
157 sprintf (p, "File %s ", (q) ? q+1 : filename);
158 p += strlen (p);
159 }
160
161 if (*p == ' ')
162 *p = '\0';
163 }
164 }
165
166 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
167 (unsigned)PC,
168 SIZE_LOCATION, SIZE_LOCATION, buf,
169 SIZE_INSTRUCTION, name);
170
171 switch (type)
172 {
173 default:
174 case OP_UNKNOWN:
175 case OP_NONE:
176 strcpy (buf, "unknown");
177 break;
178
179 case OP_TRAP:
180 sprintf (buf, "%d", OP[0]);
181 break;
182
183 case OP_REG:
184 sprintf (buf, "r%d", OP[0]);
185 break;
186
187 case OP_REG_REG:
188 case OP_REG_REG_CMP:
189 case OP_REG_REG_MOVE:
190 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
191 break;
192
193 case OP_IMM_REG:
194 case OP_IMM_REG_CMP:
195 case OP_IMM_REG_MOVE:
196 sprintf (buf, "%d,r%d", OP[0], OP[1]);
197 break;
198
199 case OP_COND_BR:
200 sprintf (buf, "%d", SEXT9 (OP[0]));
201 break;
202
203 case OP_LOAD16:
204 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
205 break;
206
207 case OP_STORE16:
208 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
209 break;
210
211 case OP_LOAD32:
212 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
213 break;
214
215 case OP_STORE32:
216 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
217 break;
218
219 case OP_JUMP:
220 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
221 break;
222
223 case OP_IMM_REG_REG:
224 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
225 break;
226
227 case OP_UIMM_REG_REG:
228 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
229 break;
230
231 case OP_BIT:
232 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
233 break;
234
235 case OP_EX1:
236 switch (OP[0] & 0xf)
237 {
238 default: cond = "?"; break;
239 case 0x0: cond = "v"; break;
240 case 0x1: cond = "c"; break;
241 case 0x2: cond = "z"; break;
242 case 0x3: cond = "nh"; break;
243 case 0x4: cond = "s"; break;
244 case 0x5: cond = "t"; break;
245 case 0x6: cond = "lt"; break;
246 case 0x7: cond = "le"; break;
247 case 0x8: cond = "nv"; break;
248 case 0x9: cond = "nc"; break;
249 case 0xa: cond = "nz"; break;
250 case 0xb: cond = "h"; break;
251 case 0xc: cond = "ns"; break;
252 case 0xd: cond = "sa"; break;
253 case 0xe: cond = "ge"; break;
254 case 0xf: cond = "gt"; break;
255 }
256
257 sprintf (buf, "%s,r%d", cond, OP[1]);
258 break;
259
260 case OP_EX2:
261 strcpy (buf, "EX2");
262 break;
263
264 case OP_LDSR:
265 case OP_STSR:
266 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
267 break;
268
269 case OP_PUSHPOP1:
270 for (i = 0; i < 12; i++)
271 if (OP[3] & (1 << type1_regs[i]))
272 strcat (buf, "r%d ", i + 20);
273 break;
274
275 case OP_PUSHPOP2:
276 for (i = 0; i < 16; i++)
277 if (OP[3] & (1 << type2_regs[i]))
278 strcat (buf, "r%d ", i + 16);
279 if (OP[3] & (1 << 19))
280 strcat (buf, "F/EIPC, F/EIPSW " );
281 break;
282
283 case OP_PUSHPOP3:
284 for (i = 0; i < 15; i++)
285 if (OP[3] & (1 << type3_regs[i]))
286 strcat (buf, "r%d ", i + 1);
287 if (OP[3] & (1 << 3))
288 strcat (buf, "PSW " );
289 if (OP[3] & (1 << 19))
290 strcat (buf, "F/EIPC, F/EIPSW " );
291 break;
292
293 case OP_BIT_CHANGE:
294 sprintf (buf, "r%d, [r%d]", OP[1], OP[0] );
295 break;
296 }
297
298 if ((v850_debug & DEBUG_VALUES) == 0)
299 {
300 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
301 }
302 else
303 {
304 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
305 switch (type)
306 {
307 default:
308 case OP_UNKNOWN:
309 case OP_NONE:
310 case OP_TRAP:
311 num_values = 0;
312 break;
313
314 case OP_REG:
315 case OP_REG_REG_MOVE:
316 values[0] = State.regs[OP[0]];
317 num_values = 1;
318 break;
319
320 case OP_BIT_CHANGE:
321 case OP_REG_REG:
322 case OP_REG_REG_CMP:
323 values[0] = State.regs[OP[1]];
324 values[1] = State.regs[OP[0]];
325 num_values = 2;
326 break;
327
328 case OP_IMM_REG:
329 case OP_IMM_REG_CMP:
330 values[0] = SEXT5 (OP[0]);
331 values[1] = OP[1];
332 num_values = 2;
333 break;
334
335 case OP_IMM_REG_MOVE:
336 values[0] = SEXT5 (OP[0]);
337 num_values = 1;
338 break;
339
340 case OP_COND_BR:
341 values[0] = State.pc;
342 values[1] = SEXT9 (OP[0]);
343 values[2] = PSW;
344 num_values = 3;
345 break;
346
347 case OP_LOAD16:
348 values[0] = OP[1] * size;
349 values[1] = State.regs[30];
350 num_values = 2;
351 break;
352
353 case OP_STORE16:
354 values[0] = State.regs[OP[0]];
355 values[1] = OP[1] * size;
356 values[2] = State.regs[30];
357 num_values = 3;
358 break;
359
360 case OP_LOAD32:
361 values[0] = SEXT16 (OP[2]);
362 values[1] = State.regs[OP[0]];
363 num_values = 2;
364 break;
365
366 case OP_STORE32:
367 values[0] = State.regs[OP[1]];
368 values[1] = SEXT16 (OP[2]);
369 values[2] = State.regs[OP[0]];
370 num_values = 3;
371 break;
372
373 case OP_JUMP:
374 values[0] = SEXT22 (OP[0]);
375 values[1] = State.pc;
376 num_values = 2;
377 break;
378
379 case OP_IMM_REG_REG:
380 values[0] = SEXT16 (OP[0]) << size;
381 values[1] = State.regs[OP[1]];
382 num_values = 2;
383 break;
384
385 case OP_UIMM_REG_REG:
386 values[0] = (OP[0] & 0xffff) << size;
387 values[1] = State.regs[OP[1]];
388 num_values = 2;
389 break;
390
391 case OP_BIT:
392 num_values = 0;
393 break;
394
395 case OP_EX1:
396 values[0] = PSW;
397 num_values = 1;
398 break;
399
400 case OP_EX2:
401 num_values = 0;
402 break;
403
404 case OP_LDSR:
405 values[0] = State.regs[OP[0]];
406 num_values = 1;
407 break;
408
409 case OP_STSR:
410 values[0] = State.sregs[OP[1]];
411 num_values = 1;
412 }
413
414 for (i = 0; i < num_values; i++)
415 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
416
417 while (i++ < 3)
418 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
419 }
420 }
421
422 static void
423 trace_output (result)
424 enum op_types result;
425 {
426 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
427 {
428 switch (result)
429 {
430 default:
431 case OP_UNKNOWN:
432 case OP_NONE:
433 case OP_TRAP:
434 case OP_REG:
435 case OP_REG_REG_CMP:
436 case OP_IMM_REG_CMP:
437 case OP_COND_BR:
438 case OP_STORE16:
439 case OP_STORE32:
440 case OP_BIT:
441 case OP_EX2:
442 break;
443
444 case OP_LOAD16:
445 case OP_STSR:
446 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
447 (unsigned long)State.regs[OP[0]]);
448 break;
449
450 case OP_REG_REG:
451 case OP_REG_REG_MOVE:
452 case OP_IMM_REG:
453 case OP_IMM_REG_MOVE:
454 case OP_LOAD32:
455 case OP_EX1:
456 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
457 (unsigned long)State.regs[OP[1]]);
458 break;
459
460 case OP_IMM_REG_REG:
461 case OP_UIMM_REG_REG:
462 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
463 (unsigned long)State.regs[OP[2]]);
464 break;
465
466 case OP_JUMP:
467 if (OP[1] != 0)
468 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
469 (unsigned long)State.regs[OP[1]]);
470 break;
471
472 case OP_LDSR:
473 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
474 (unsigned long)State.sregs[OP[1]]);
475 break;
476 }
477
478 (*v850_callback->printf_filtered) (v850_callback, "\n");
479 }
480 }
481
482 #else
483 #define trace_input(NAME, IN1, IN2)
484 #define trace_output(RESULT)
485
486 //#define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" );
487
488 #endif
489
490 \f
491 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
492 static unsigned int
493 condition_met (unsigned code)
494 {
495 unsigned int psw = PSW;
496
497 switch (code & 0xf)
498 {
499 case 0x0: return ((psw & PSW_OV) != 0);
500 case 0x1: return ((psw & PSW_CY) != 0);
501 case 0x2: return ((psw & PSW_Z) != 0);
502 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
503 case 0x4: return ((psw & PSW_S) != 0);
504 /*case 0x5: return 1;*/
505 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
506 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
507 case 0x8: return ((psw & PSW_OV) == 0);
508 case 0x9: return ((psw & PSW_CY) == 0);
509 case 0xa: return ((psw & PSW_Z) == 0);
510 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
511 case 0xc: return ((psw & PSW_S) == 0);
512 case 0xd: return ((psw & PSW_SAT) != 0);
513 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
514 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
515 }
516
517 return 1;
518 }
519
520 static unsigned long
521 Add32 (unsigned long a1, unsigned long a2, int * carry)
522 {
523 unsigned long result = (a1 + a2);
524
525 * carry = (result < a1);
526
527 return result;
528 }
529
530 static void
531 Multiply64 (boolean sign, unsigned long op0)
532 {
533 unsigned long op1;
534 unsigned long lo;
535 unsigned long mid1;
536 unsigned long mid2;
537 unsigned long hi;
538 unsigned long RdLo;
539 unsigned long RdHi;
540 int carry;
541
542 op1 = State.regs[ OP[1] ];
543
544 if (sign)
545 {
546 /* Compute sign of result and adjust operands if necessary. */
547
548 sign = (op0 ^ op1) & 0x80000000;
549
550 if (((signed long) op0) < 0)
551 op0 = - op0;
552
553 if (((signed long) op1) < 0)
554 op1 = - op1;
555 }
556
557 /* We can split the 32x32 into four 16x16 operations. This ensures
558 that we do not lose precision on 32bit only hosts: */
559 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
560 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
561 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
562 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
563
564 /* We now need to add all of these results together, taking care
565 to propogate the carries from the additions: */
566 RdLo = Add32 (lo, (mid1 << 16), & carry);
567 RdHi = carry;
568 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
569 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
570
571 if (sign)
572 {
573 /* Negate result if necessary. */
574
575 RdLo = ~ RdLo;
576 RdHi = ~ RdHi;
577 if (RdLo == 0xFFFFFFFF)
578 {
579 RdLo = 0;
580 RdHi += 1;
581 }
582 else
583 RdLo += 1;
584 }
585
586 State.regs[ OP[1] ] = RdLo;
587 State.regs[ OP[2] >> 11 ] = RdHi;
588
589 return;
590 }
591
592 \f
593 /* sld.b */
594 int
595 OP_300 ()
596 {
597 unsigned long result;
598
599 result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
600
601 /* start-sanitize-v850eq */
602 #ifdef ARCH_v850eq
603 trace_input ("sld.bu", OP_LOAD16, 1);
604
605 State.regs[ OP[1] ] = result;
606 #else
607 /* end-sanitize-v850eq */
608 trace_input ("sld.b", OP_LOAD16, 1);
609
610 State.regs[ OP[1] ] = SEXT8 (result);
611 /* start-sanitize-v850eq */
612 #endif
613 /* end-sanitize-v850eq */
614
615 trace_output (OP_LOAD16);
616
617 return 2;
618 }
619
620 /* sld.h */
621 int
622 OP_400 ()
623 {
624 unsigned long result;
625
626 result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
627
628 /* start-sanitize-v850eq */
629 #ifdef ARCH_v850eq
630 trace_input ("sld.hu", OP_LOAD16, 2);
631
632 State.regs[ OP[1] ] = result;
633 #else
634 /* end-sanitize-v850eq */
635 trace_input ("sld.h", OP_LOAD16, 2);
636
637 State.regs[ OP[1] ] = SEXT16 (result);
638 /* start-sanitize-v850eq */
639 #endif
640 /* end-sanitize-v850eq */
641
642 trace_output (OP_LOAD16);
643
644 return 2;
645 }
646
647 /* sld.w */
648 int
649 OP_500 ()
650 {
651 trace_input ("sld.w", OP_LOAD16, 4);
652
653 State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
654
655 trace_output (OP_LOAD16);
656
657 return 2;
658 }
659
660 /* sst.b */
661 int
662 OP_380 ()
663 {
664 trace_input ("sst.b", OP_STORE16, 1);
665
666 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
667
668 trace_output (OP_STORE16);
669
670 return 2;
671 }
672
673 /* sst.h */
674 int
675 OP_480 ()
676 {
677 trace_input ("sst.h", OP_STORE16, 2);
678
679 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
680
681 trace_output (OP_STORE16);
682
683 return 2;
684 }
685
686 /* sst.w */
687 int
688 OP_501 ()
689 {
690 trace_input ("sst.w", OP_STORE16, 4);
691
692 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
693
694 trace_output (OP_STORE16);
695
696 return 2;
697 }
698
699 /* ld.b */
700 int
701 OP_700 ()
702 {
703 int adr;
704
705 trace_input ("ld.b", OP_LOAD32, 1);
706
707 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
708
709 State.regs[ OP[1] ] = SEXT8 (load_mem (adr, 1));
710
711 trace_output (OP_LOAD32);
712
713 return 4;
714 }
715
716 /* ld.h */
717 int
718 OP_720 ()
719 {
720 int adr;
721
722 trace_input ("ld.h", OP_LOAD32, 2);
723
724 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
725 adr &= ~0x1;
726
727 State.regs[ OP[1] ] = SEXT16 (load_mem (adr, 2));
728
729 trace_output (OP_LOAD32);
730
731 return 4;
732 }
733
734 /* ld.w */
735 int
736 OP_10720 ()
737 {
738 int adr;
739
740 trace_input ("ld.w", OP_LOAD32, 4);
741
742 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
743 adr &= ~0x3;
744
745 State.regs[ OP[1] ] = load_mem (adr, 4);
746
747 trace_output (OP_LOAD32);
748
749 return 4;
750 }
751
752 /* st.b */
753 int
754 OP_740 ()
755 {
756 trace_input ("st.b", OP_STORE32, 1);
757
758 store_mem (State.regs[ OP[0] ] + SEXT16 (OP[2]), 1, State.regs[ OP[1] ]);
759
760 trace_output (OP_STORE32);
761
762 return 4;
763 }
764
765 /* st.h */
766 int
767 OP_760 ()
768 {
769 int adr;
770
771 trace_input ("st.h", OP_STORE32, 2);
772
773 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
774 adr &= ~1;
775
776 store_mem (adr, 2, State.regs[ OP[1] ]);
777
778 trace_output (OP_STORE32);
779
780 return 4;
781 }
782
783 /* st.w */
784 int
785 OP_10760 ()
786 {
787 int adr;
788
789 trace_input ("st.w", OP_STORE32, 4);
790
791 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
792 adr &= ~3;
793
794 store_mem (adr, 4, State.regs[ OP[1] ]);
795
796 trace_output (OP_STORE32);
797
798 return 4;
799 }
800
801 static int
802 branch (int code)
803 {
804 trace_input ("Bcond", OP_COND_BR, 0);
805 trace_output (OP_COND_BR);
806
807 if (condition_met (code))
808 return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
809 else
810 return 2;
811 }
812
813 /* bv disp9 */
814 int
815 OP_580 ()
816 {
817 return branch (0);
818 }
819
820 /* bl disp9 */
821 int
822 OP_581 ()
823 {
824 return branch (1);
825 }
826
827 /* be disp9 */
828 int
829 OP_582 ()
830 {
831 return branch (2);
832 }
833
834 /* bnh disp 9*/
835 int
836 OP_583 ()
837 {
838 return branch (3);
839 }
840
841 /* bn disp9 */
842 int
843 OP_584 ()
844 {
845 return branch (4);
846 }
847
848 /* br disp9 */
849 int
850 OP_585 ()
851 {
852 return branch (5);
853 }
854
855 /* blt disp9 */
856 int
857 OP_586 ()
858 {
859 return branch (6);
860 }
861
862 /* ble disp9 */
863 int
864 OP_587 ()
865 {
866 return branch (7);
867 }
868
869 /* bnv disp9 */
870 int
871 OP_588 ()
872 {
873 return branch (8);
874 }
875
876 /* bnl disp9 */
877 int
878 OP_589 ()
879 {
880 return branch (9);
881 }
882
883 /* bne disp9 */
884 int
885 OP_58A ()
886 {
887 return branch (10);
888 }
889
890 /* bh disp9 */
891 int
892 OP_58B ()
893 {
894 return branch (11);
895 }
896
897 /* bp disp9 */
898 int
899 OP_58C ()
900 {
901 return branch (12);
902 }
903
904 /* bsa disp9 */
905 int
906 OP_58D ()
907 {
908 return branch (13);
909 }
910
911 /* bge disp9 */
912 int
913 OP_58E ()
914 {
915 return branch (14);
916 }
917
918 /* bgt disp9 */
919 int
920 OP_58F ()
921 {
922 return branch (15);
923 }
924
925 /* jmp [reg1] */
926 /* sld.bu disp4[ep], reg2 */
927 int
928 OP_60 ()
929 {
930 if (OP[1] == 0)
931 {
932 trace_input ("jmp", OP_REG, 0);
933
934 PC = State.regs[ OP[0] ];
935
936 trace_output (OP_REG);
937
938 return 0; /* Add nothing to the PC, we have already done it. */
939 }
940 /* start-sanitize-v850e */
941 else
942 {
943 unsigned long result;
944
945 result = load_mem (State.regs[30] + (OP[3] & 0xf), 1);
946
947 /* start-sanitize-v850eq */
948 #ifdef ARCH_v850eq
949 trace_input ("sld.b", OP_LOAD16, 1);
950
951 State.regs[ OP[1] ] = SEXT8 (result);
952 #else
953 /* end-sanitize-v850eq */
954 trace_input ("sld.bu", OP_LOAD16, 1);
955
956 State.regs[ OP[1] ] = result;
957 /* start-sanitize-v850eq */
958 #endif
959 /* end-sanitize-v850eq */
960
961 trace_output (OP_LOAD16);
962
963 return 2;
964 }
965 /* end-sanitize-v850e */
966 }
967
968 /* jarl/jr disp22, reg */
969 int
970 OP_780 ()
971 {
972 trace_input ("jarl/jr", OP_JUMP, 0);
973
974 if (OP[ 1 ] != 0)
975 State.regs[ OP[1] ] = PC + 4;
976
977 trace_output (OP_JUMP);
978
979 return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
980 }
981
982 /* add reg, reg */
983 int
984 OP_1C0 ()
985 {
986 unsigned int op0, op1, result, z, s, cy, ov;
987
988 trace_input ("add", OP_REG_REG, 0);
989
990 /* Compute the result. */
991
992 op0 = State.regs[ OP[0] ];
993 op1 = State.regs[ OP[1] ];
994
995 result = op0 + op1;
996
997 /* Compute the condition codes. */
998 z = (result == 0);
999 s = (result & 0x80000000);
1000 cy = (result < op0 || result < op1);
1001 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1002 && (op0 & 0x80000000) != (result & 0x80000000));
1003
1004 /* Store the result and condition codes. */
1005 State.regs[OP[1]] = result;
1006 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1007 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1008 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1009 trace_output (OP_REG_REG);
1010
1011 return 2;
1012 }
1013
1014 /* add sign_extend(imm5), reg */
1015 int
1016 OP_240 ()
1017 {
1018 unsigned int op0, op1, result, z, s, cy, ov;
1019 int temp;
1020
1021 trace_input ("add", OP_IMM_REG, 0);
1022
1023 /* Compute the result. */
1024 temp = SEXT5 (OP[0]);
1025 op0 = temp;
1026 op1 = State.regs[OP[1]];
1027 result = op0 + op1;
1028
1029 /* Compute the condition codes. */
1030 z = (result == 0);
1031 s = (result & 0x80000000);
1032 cy = (result < op0 || result < op1);
1033 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1034 && (op0 & 0x80000000) != (result & 0x80000000));
1035
1036 /* Store the result and condition codes. */
1037 State.regs[OP[1]] = result;
1038 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1039 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1040 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1041 trace_output (OP_IMM_REG);
1042
1043 return 2;
1044 }
1045
1046 /* addi sign_extend(imm16), reg, reg */
1047 int
1048 OP_600 ()
1049 {
1050 unsigned int op0, op1, result, z, s, cy, ov;
1051
1052 trace_input ("addi", OP_IMM_REG_REG, 0);
1053
1054 /* Compute the result. */
1055
1056 op0 = SEXT16 (OP[2]);
1057 op1 = State.regs[ OP[0] ];
1058 result = op0 + op1;
1059
1060 /* Compute the condition codes. */
1061 z = (result == 0);
1062 s = (result & 0x80000000);
1063 cy = (result < op0 || result < op1);
1064 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1065 && (op0 & 0x80000000) != (result & 0x80000000));
1066
1067 /* Store the result and condition codes. */
1068 State.regs[OP[1]] = result;
1069 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1070 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1071 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1072 trace_output (OP_IMM_REG_REG);
1073
1074 return 4;
1075 }
1076
1077 /* sub reg1, reg2 */
1078 int
1079 OP_1A0 ()
1080 {
1081 unsigned int op0, op1, result, z, s, cy, ov;
1082
1083 trace_input ("sub", OP_REG_REG, 0);
1084 /* Compute the result. */
1085 op0 = State.regs[ OP[0] ];
1086 op1 = State.regs[ OP[1] ];
1087 result = op1 - op0;
1088
1089 /* Compute the condition codes. */
1090 z = (result == 0);
1091 s = (result & 0x80000000);
1092 cy = (op1 < op0);
1093 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1094 && (op1 & 0x80000000) != (result & 0x80000000));
1095
1096 /* Store the result and condition codes. */
1097 State.regs[OP[1]] = result;
1098 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1099 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1100 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1101 trace_output (OP_REG_REG);
1102
1103 return 2;
1104 }
1105
1106 /* subr reg1, reg2 */
1107 int
1108 OP_180 ()
1109 {
1110 unsigned int op0, op1, result, z, s, cy, ov;
1111
1112 trace_input ("subr", OP_REG_REG, 0);
1113 /* Compute the result. */
1114 op0 = State.regs[ OP[0] ];
1115 op1 = State.regs[ OP[1] ];
1116 result = op0 - op1;
1117
1118 /* Compute the condition codes. */
1119 z = (result == 0);
1120 s = (result & 0x80000000);
1121 cy = (op0 < op1);
1122 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1123 && (op0 & 0x80000000) != (result & 0x80000000));
1124
1125 /* Store the result and condition codes. */
1126 State.regs[OP[1]] = result;
1127 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1128 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1129 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1130 trace_output (OP_REG_REG);
1131
1132 return 2;
1133 }
1134
1135 /* sxh reg1 */
1136 /* mulh reg1, reg2 */
1137 int
1138 OP_E0 ()
1139 {
1140 /* start-sanitize-v850e */
1141 if (OP[1] == 0)
1142 {
1143 trace_input ("sxh", OP_REG, 0);
1144
1145 State.regs[ OP[0] ] = SEXT16 (State.regs[ OP[0] ]);
1146
1147 trace_output (OP_REG);
1148 }
1149 else
1150 /* end-sanitize-v850e */
1151 {
1152 trace_input ("mulh", OP_REG_REG, 0);
1153
1154 State.regs[ OP[1] ] = (SEXT16 (State.regs[ OP[1] ]) * SEXT16 (State.regs[ OP[0] ]));
1155
1156 trace_output (OP_REG_REG);
1157 }
1158
1159 return 2;
1160 }
1161
1162 /* mulh sign_extend(imm5), reg2 */
1163 int
1164 OP_2E0 ()
1165 {
1166 trace_input ("mulh", OP_IMM_REG, 0);
1167
1168 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
1169
1170 trace_output (OP_IMM_REG);
1171
1172 return 2;
1173 }
1174
1175 /* mulhi imm16, reg1, reg2 */
1176 int
1177 OP_6E0 ()
1178 {
1179 if (OP[1] == 0)
1180 {
1181 }
1182 else
1183 {
1184 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1185
1186 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[0] ]) * SEXT16 (OP[2]);
1187
1188 trace_output (OP_IMM_REG_REG);
1189 }
1190
1191 return 4;
1192 }
1193
1194 /* divh reg1, reg2 */
1195 /* switch reg1 */
1196 int
1197 OP_40 ()
1198 {
1199 /* start-sanitize-v850e */
1200 if (OP[1] == 0)
1201 {
1202 unsigned long adr;
1203
1204 trace_input ("switch", OP_REG, 0);
1205
1206 adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
1207 State.pc = State.pc + 2 + (SEXT16 (load_mem (adr, 2)) << 1);
1208
1209 trace_output (OP_REG);
1210 }
1211 else
1212 /* end-sanitize-v850e */
1213 {
1214 unsigned int op0, op1, result, ov, s, z;
1215 int temp;
1216
1217 trace_input ("divh", OP_REG_REG, 0);
1218
1219 /* Compute the result. */
1220 temp = SEXT16 (State.regs[ OP[0] ]);
1221 op0 = temp;
1222 op1 = State.regs[OP[1]];
1223
1224 if (op0 == 0xffffffff && op1 == 0x80000000)
1225 {
1226 result = 0x80000000;
1227 ov = 1;
1228 }
1229 else if (op0 != 0)
1230 {
1231 result = op1 / op0;
1232 ov = 0;
1233 }
1234 else
1235 {
1236 result = 0x0;
1237 ov = 1;
1238 }
1239
1240 /* Compute the condition codes. */
1241 z = (result == 0);
1242 s = (result & 0x80000000);
1243
1244 /* Store the result and condition codes. */
1245 State.regs[OP[1]] = result;
1246 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1247 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1248 | (ov ? PSW_OV : 0));
1249 trace_output (OP_REG_REG);
1250 }
1251
1252 return 2;
1253 }
1254
1255 /* cmp reg, reg */
1256 int
1257 OP_1E0 ()
1258 {
1259 unsigned int op0, op1, result, z, s, cy, ov;
1260
1261 trace_input ("cmp", OP_REG_REG_CMP, 0);
1262 /* Compute the result. */
1263 op0 = State.regs[ OP[0] ];
1264 op1 = State.regs[ OP[1] ];
1265 result = op1 - op0;
1266
1267 /* Compute the condition codes. */
1268 z = (result == 0);
1269 s = (result & 0x80000000);
1270 cy = (op1 < op0);
1271 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1272 && (op1 & 0x80000000) != (result & 0x80000000));
1273
1274 /* Set condition codes. */
1275 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1276 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1277 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1278 trace_output (OP_REG_REG_CMP);
1279
1280 return 2;
1281 }
1282
1283 /* cmp sign_extend(imm5), reg */
1284 int
1285 OP_260 ()
1286 {
1287 unsigned int op0, op1, result, z, s, cy, ov;
1288 int temp;
1289
1290 /* Compute the result. */
1291 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1292 temp = SEXT5 (OP[0]);
1293 op0 = temp;
1294 op1 = State.regs[OP[1]];
1295 result = op1 - op0;
1296
1297 /* Compute the condition codes. */
1298 z = (result == 0);
1299 s = (result & 0x80000000);
1300 cy = (op1 < op0);
1301 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1302 && (op1 & 0x80000000) != (result & 0x80000000));
1303
1304 /* Set condition codes. */
1305 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1306 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1307 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1308 trace_output (OP_IMM_REG_CMP);
1309
1310 return 2;
1311 }
1312
1313 /* setf cccc,reg2 */
1314 int
1315 OP_7E0 ()
1316 {
1317 trace_input ("setf", OP_EX1, 0);
1318
1319 State.regs[ OP[1] ] = condition_met (OP[0]);
1320
1321 trace_output (OP_EX1);
1322
1323 return 4;
1324 }
1325
1326 /* zxh reg1 */
1327 /* satadd reg,reg */
1328 int
1329 OP_C0 ()
1330 {
1331 /* start-sanitize-v850e */
1332 if (OP[1] == 0)
1333 {
1334 trace_input ("zxh", OP_REG, 0);
1335
1336 State.regs[ OP[0] ] &= 0xffff;
1337
1338 trace_output (OP_REG);
1339 }
1340 else
1341 /* end-sanitize-v850e */
1342 {
1343 unsigned int op0, op1, result, z, s, cy, ov, sat;
1344
1345 trace_input ("satadd", OP_REG_REG, 0);
1346 /* Compute the result. */
1347 op0 = State.regs[ OP[0] ];
1348 op1 = State.regs[ OP[1] ];
1349 result = op0 + op1;
1350
1351 /* Compute the condition codes. */
1352 z = (result == 0);
1353 s = (result & 0x80000000);
1354 cy = (result < op0 || result < op1);
1355 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1356 && (op0 & 0x80000000) != (result & 0x80000000));
1357 sat = ov;
1358
1359 /* Store the result and condition codes. */
1360 State.regs[OP[1]] = result;
1361 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1362 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1363 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1364 | (sat ? PSW_SAT : 0));
1365
1366 /* Handle saturated results. */
1367 if (sat && s)
1368 State.regs[OP[1]] = 0x80000000;
1369 else if (sat)
1370 State.regs[OP[1]] = 0x7fffffff;
1371 trace_output (OP_REG_REG);
1372 }
1373
1374 return 2;
1375 }
1376
1377 /* satadd sign_extend(imm5), reg */
1378 int
1379 OP_220 ()
1380 {
1381 unsigned int op0, op1, result, z, s, cy, ov, sat;
1382
1383 int temp;
1384
1385 trace_input ("satadd", OP_IMM_REG, 0);
1386
1387 /* Compute the result. */
1388 temp = SEXT5 (OP[0]);
1389 op0 = temp;
1390 op1 = State.regs[OP[1]];
1391 result = op0 + op1;
1392
1393 /* Compute the condition codes. */
1394 z = (result == 0);
1395 s = (result & 0x80000000);
1396 cy = (result < op0 || result < op1);
1397 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1398 && (op0 & 0x80000000) != (result & 0x80000000));
1399 sat = ov;
1400
1401 /* Store the result and condition codes. */
1402 State.regs[OP[1]] = result;
1403 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1404 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1405 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1406 | (sat ? PSW_SAT : 0));
1407
1408 /* Handle saturated results. */
1409 if (sat && s)
1410 State.regs[OP[1]] = 0x80000000;
1411 else if (sat)
1412 State.regs[OP[1]] = 0x7fffffff;
1413 trace_output (OP_IMM_REG);
1414
1415 return 2;
1416 }
1417
1418 /* satsub reg1, reg2 */
1419 /* sxb reg1 */
1420 int
1421 OP_A0 ()
1422 {
1423 /* start-sanitize-v850e */
1424 if (OP[1] == 0)
1425 {
1426 trace_input ("sxb", OP_REG, 0);
1427
1428 State.regs[ OP[0] ] = SEXT8 (State.regs[ OP[0] ]);
1429
1430 trace_output (OP_REG);
1431 }
1432 else
1433 /* end-sanitize-v850e */
1434 {
1435 unsigned int op0, op1, result, z, s, cy, ov, sat;
1436
1437 trace_input ("satsub", OP_REG_REG, 0);
1438
1439 /* Compute the result. */
1440 op0 = State.regs[ OP[0] ];
1441 op1 = State.regs[ OP[1] ];
1442 result = op1 - op0;
1443
1444 /* Compute the condition codes. */
1445 z = (result == 0);
1446 s = (result & 0x80000000);
1447 cy = (op1 < op0);
1448 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1449 && (op1 & 0x80000000) != (result & 0x80000000));
1450 sat = ov;
1451
1452 /* Store the result and condition codes. */
1453 State.regs[OP[1]] = result;
1454 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1455 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1456 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1457 | (sat ? PSW_SAT : 0));
1458
1459 /* Handle saturated results. */
1460 if (sat && s)
1461 State.regs[OP[1]] = 0x80000000;
1462 else if (sat)
1463 State.regs[OP[1]] = 0x7fffffff;
1464 trace_output (OP_REG_REG);
1465 }
1466
1467 return 2;
1468 }
1469
1470 /* satsubi sign_extend(imm16), reg */
1471 int
1472 OP_660 ()
1473 {
1474 unsigned int op0, op1, result, z, s, cy, ov, sat;
1475 int temp;
1476
1477 trace_input ("satsubi", OP_IMM_REG, 0);
1478
1479 /* Compute the result. */
1480 temp = SEXT16 (OP[2]);
1481 op0 = temp;
1482 op1 = State.regs[ OP[0] ];
1483 result = op1 - op0;
1484
1485 /* Compute the condition codes. */
1486 z = (result == 0);
1487 s = (result & 0x80000000);
1488 cy = (op1 < op0);
1489 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1490 && (op1 & 0x80000000) != (result & 0x80000000));
1491 sat = ov;
1492
1493 /* Store the result and condition codes. */
1494 State.regs[OP[1]] = result;
1495 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1496 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1497 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1498 | (sat ? PSW_SAT : 0));
1499
1500 /* Handle saturated results. */
1501 if (sat && s)
1502 State.regs[OP[1]] = 0x80000000;
1503 else if (sat)
1504 State.regs[OP[1]] = 0x7fffffff;
1505 trace_output (OP_IMM_REG);
1506
1507 return 4;
1508 }
1509
1510 /* satsubr reg,reg */
1511 /* zxb reg1 */
1512 int
1513 OP_80 ()
1514 {
1515 /* start-sanitize-v850e */
1516 if (OP[1] == 0)
1517 {
1518 trace_input ("zxb", OP_REG, 0);
1519
1520 State.regs[ OP[0] ] &= 0xff;
1521
1522 trace_output (OP_REG);
1523 }
1524 else
1525 /* end-sanitize-v850e */
1526 {
1527 unsigned int op0, op1, result, z, s, cy, ov, sat;
1528
1529 trace_input ("satsubr", OP_REG_REG, 0);
1530
1531 /* Compute the result. */
1532 op0 = State.regs[ OP[0] ];
1533 op1 = State.regs[ OP[1] ];
1534 result = op0 - op1;
1535
1536 /* Compute the condition codes. */
1537 z = (result == 0);
1538 s = (result & 0x80000000);
1539 cy = (result < op0);
1540 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1541 && (op1 & 0x80000000) != (result & 0x80000000));
1542 sat = ov;
1543
1544 /* Store the result and condition codes. */
1545 State.regs[OP[1]] = result;
1546 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1547 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1548 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1549 | (sat ? PSW_SAT : 0));
1550
1551 /* Handle saturated results. */
1552 if (sat && s)
1553 State.regs[OP[1]] = 0x80000000;
1554 else if (sat)
1555 State.regs[OP[1]] = 0x7fffffff;
1556 trace_output (OP_REG_REG);
1557 }
1558
1559 return 2;
1560 }
1561
1562 /* tst reg,reg */
1563 int
1564 OP_160 ()
1565 {
1566 unsigned int op0, op1, result, z, s;
1567
1568 trace_input ("tst", OP_REG_REG_CMP, 0);
1569
1570 /* Compute the result. */
1571 op0 = State.regs[ OP[0] ];
1572 op1 = State.regs[ OP[1] ];
1573 result = op0 & op1;
1574
1575 /* Compute the condition codes. */
1576 z = (result == 0);
1577 s = (result & 0x80000000);
1578
1579 /* Store the condition codes. */
1580 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1581 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1582 trace_output (OP_REG_REG_CMP);
1583
1584 return 2;
1585 }
1586
1587 /* mov reg, reg */
1588 int
1589 OP_0 ()
1590 {
1591 trace_input ("mov", OP_REG_REG_MOVE, 0);
1592
1593 State.regs[ OP[1] ] = State.regs[ OP[0] ];
1594
1595 trace_output (OP_REG_REG_MOVE);
1596
1597 return 2;
1598 }
1599
1600 /* mov sign_extend(imm5), reg */
1601 /* callt imm6 */
1602 int
1603 OP_200 ()
1604 {
1605 /* start-sanitize-v850e */
1606 if (OP[1] == 0)
1607 {
1608 unsigned long adr;
1609
1610 trace_input ("callt", OP_LOAD16, 1);
1611
1612 CTPC = PC + 2;
1613 CTPSW = PSW;
1614
1615 adr = CTBP + ((OP[3] & 0x3f) << 1);
1616
1617 PC = CTBP + load_mem (adr, 1);
1618
1619 trace_output (OP_LOAD16);
1620
1621 return 0;
1622 }
1623 else
1624 /* end-sanitize-v850e */
1625 {
1626 int value = SEXT5 (OP[0]);
1627
1628 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1629
1630 State.regs[ OP[1] ] = value;
1631
1632 trace_output (OP_IMM_REG_MOVE);
1633
1634 return 2;
1635 }
1636 }
1637
1638 /* mov imm32, reg1 */
1639 /* movea sign_extend(imm16), reg, reg */
1640 int
1641 OP_620 ()
1642 {
1643 /* start-sanitize-v850e */
1644 if (OP[1] == 0)
1645 {
1646 trace_input ("mov", OP_IMM32_REG, 4);
1647
1648 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1649
1650 trace_output (OP_IMM32_REG);
1651
1652 return 6;
1653 }
1654 else
1655 /* end-sanitize-v850e */
1656 {
1657 trace_input ("movea", OP_IMM_REG_REG, 0);
1658
1659 State.regs[ OP[1] ] = State.regs[ OP[0] ] + SEXT16 (OP[2]);
1660
1661 trace_output (OP_IMM_REG_REG);
1662
1663 return 4;
1664 }
1665 }
1666
1667 /* dispose imm5, list12 [, reg1] */
1668 /* movhi imm16, reg, reg */
1669 int
1670 OP_640 ()
1671 {
1672 /* start-sanitize-v850e */
1673
1674 if (OP[1] == 0)
1675 {
1676 int i;
1677
1678 trace_input ("dispose", OP_PUSHPOP1, 0);
1679
1680 SP += (OP[3] & 0x3e) << 1;
1681
1682 /* Load the registers with lower number registers being retrieved from higher addresses. */
1683 for (i = 12; i--;)
1684 if ((OP[3] & (1 << type1_regs[ i ])))
1685 {
1686 State.regs[ 20 + i ] = load_mem (SP, 4);
1687 SP += 4;
1688 }
1689
1690 if ((OP[3] & 0x1f0000) != 0)
1691 {
1692 PC = State.regs[ (OP[3] >> 16) & 0x1f];
1693 return 0;
1694 }
1695
1696 trace_output (OP_PUSHPOP1);
1697 }
1698 else
1699 /* end-sanitize-v850e */
1700 {
1701 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1702
1703 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1704
1705 trace_output (OP_UIMM_REG_REG);
1706 }
1707
1708 return 4;
1709 }
1710
1711 /* sar zero_extend(imm5),reg1 */
1712 int
1713 OP_2A0 ()
1714 {
1715 unsigned int op0, op1, result, z, s, cy;
1716
1717 trace_input ("sar", OP_IMM_REG, 0);
1718 op0 = OP[0];
1719 op1 = State.regs[ OP[1] ];
1720 result = (signed)op1 >> op0;
1721
1722 /* Compute the condition codes. */
1723 z = (result == 0);
1724 s = (result & 0x80000000);
1725 cy = (op1 & (1 << (op0 - 1)));
1726
1727 /* Store the result and condition codes. */
1728 State.regs[ OP[1] ] = result;
1729 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1730 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1731 | (cy ? PSW_CY : 0));
1732 trace_output (OP_IMM_REG);
1733
1734 return 2;
1735 }
1736
1737 /* sar reg1, reg2 */
1738 int
1739 OP_A007E0 ()
1740 {
1741 unsigned int op0, op1, result, z, s, cy;
1742
1743 trace_input ("sar", OP_REG_REG, 0);
1744
1745 op0 = State.regs[ OP[0] ] & 0x1f;
1746 op1 = State.regs[ OP[1] ];
1747 result = (signed)op1 >> op0;
1748
1749 /* Compute the condition codes. */
1750 z = (result == 0);
1751 s = (result & 0x80000000);
1752 cy = (op1 & (1 << (op0 - 1)));
1753
1754 /* Store the result and condition codes. */
1755 State.regs[OP[1]] = result;
1756 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1757 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1758 | (cy ? PSW_CY : 0));
1759 trace_output (OP_REG_REG);
1760
1761 return 4;
1762 }
1763
1764 /* shl zero_extend(imm5),reg1 */
1765 int
1766 OP_2C0 ()
1767 {
1768 unsigned int op0, op1, result, z, s, cy;
1769
1770 trace_input ("shl", OP_IMM_REG, 0);
1771 op0 = OP[0];
1772 op1 = State.regs[ OP[1] ];
1773 result = op1 << op0;
1774
1775 /* Compute the condition codes. */
1776 z = (result == 0);
1777 s = (result & 0x80000000);
1778 cy = (op1 & (1 << (32 - op0)));
1779
1780 /* Store the result and condition codes. */
1781 State.regs[OP[1]] = result;
1782 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1783 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1784 | (cy ? PSW_CY : 0));
1785 trace_output (OP_IMM_REG);
1786
1787 return 2;
1788 }
1789
1790 /* shl reg1, reg2 */
1791 int
1792 OP_C007E0 ()
1793 {
1794 unsigned int op0, op1, result, z, s, cy;
1795
1796 trace_input ("shl", OP_REG_REG, 0);
1797 op0 = State.regs[ OP[0] ] & 0x1f;
1798 op1 = State.regs[ OP[1] ];
1799 result = op1 << op0;
1800
1801 /* Compute the condition codes. */
1802 z = (result == 0);
1803 s = (result & 0x80000000);
1804 cy = (op1 & (1 << (32 - op0)));
1805
1806 /* Store the result and condition codes. */
1807 State.regs[OP[1]] = result;
1808 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1809 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1810 | (cy ? PSW_CY : 0));
1811 trace_output (OP_REG_REG);
1812
1813 return 4;
1814 }
1815
1816 /* shr zero_extend(imm5),reg1 */
1817 int
1818 OP_280 ()
1819 {
1820 unsigned int op0, op1, result, z, s, cy;
1821
1822 trace_input ("shr", OP_IMM_REG, 0);
1823 op0 = OP[0];
1824 op1 = State.regs[ OP[1] ];
1825 result = op1 >> op0;
1826
1827 /* Compute the condition codes. */
1828 z = (result == 0);
1829 s = (result & 0x80000000);
1830 cy = (op1 & (1 << (op0 - 1)));
1831
1832 /* Store the result and condition codes. */
1833 State.regs[OP[1]] = result;
1834 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1835 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1836 | (cy ? PSW_CY : 0));
1837 trace_output (OP_IMM_REG);
1838
1839 return 2;
1840 }
1841
1842 /* shr reg1, reg2 */
1843 int
1844 OP_8007E0 ()
1845 {
1846 unsigned int op0, op1, result, z, s, cy;
1847
1848 trace_input ("shr", OP_REG_REG, 0);
1849 op0 = State.regs[ OP[0] ] & 0x1f;
1850 op1 = State.regs[ OP[1] ];
1851 result = op1 >> op0;
1852
1853 /* Compute the condition codes. */
1854 z = (result == 0);
1855 s = (result & 0x80000000);
1856 cy = (op1 & (1 << (op0 - 1)));
1857
1858 /* Store the result and condition codes. */
1859 State.regs[OP[1]] = result;
1860 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1861 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1862 | (cy ? PSW_CY : 0));
1863 trace_output (OP_REG_REG);
1864
1865 return 4;
1866 }
1867
1868 /* or reg, reg */
1869 int
1870 OP_100 ()
1871 {
1872 unsigned int op0, op1, result, z, s;
1873
1874 trace_input ("or", OP_REG_REG, 0);
1875
1876 /* Compute the result. */
1877 op0 = State.regs[ OP[0] ];
1878 op1 = State.regs[ OP[1] ];
1879 result = op0 | op1;
1880
1881 /* Compute the condition codes. */
1882 z = (result == 0);
1883 s = (result & 0x80000000);
1884
1885 /* Store the result and condition codes. */
1886 State.regs[OP[1]] = result;
1887 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1888 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1889 trace_output (OP_REG_REG);
1890
1891 return 2;
1892 }
1893
1894 /* ori zero_extend(imm16), reg, reg */
1895 int
1896 OP_680 ()
1897 {
1898 unsigned int op0, op1, result, z, s;
1899
1900 trace_input ("ori", OP_UIMM_REG_REG, 0);
1901 op0 = OP[2];
1902 op1 = State.regs[ OP[0] ];
1903 result = op0 | op1;
1904
1905 /* Compute the condition codes. */
1906 z = (result == 0);
1907 s = (result & 0x80000000);
1908
1909 /* Store the result and condition codes. */
1910 State.regs[OP[1]] = result;
1911 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1912 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1913 trace_output (OP_UIMM_REG_REG);
1914
1915 return 4;
1916 }
1917
1918 /* and reg, reg */
1919 int
1920 OP_140 ()
1921 {
1922 unsigned int op0, op1, result, z, s;
1923
1924 trace_input ("and", OP_REG_REG, 0);
1925
1926 /* Compute the result. */
1927 op0 = State.regs[ OP[0] ];
1928 op1 = State.regs[ OP[1] ];
1929 result = op0 & op1;
1930
1931 /* Compute the condition codes. */
1932 z = (result == 0);
1933 s = (result & 0x80000000);
1934
1935 /* Store the result and condition codes. */
1936 State.regs[OP[1]] = result;
1937 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1938 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1939 trace_output (OP_REG_REG);
1940
1941 return 2;
1942 }
1943
1944 /* andi zero_extend(imm16), reg, reg */
1945 int
1946 OP_6C0 ()
1947 {
1948 unsigned int result, z;
1949
1950 trace_input ("andi", OP_UIMM_REG_REG, 0);
1951
1952 result = OP[2] & State.regs[ OP[0] ];
1953
1954 /* Compute the condition codes. */
1955 z = (result == 0);
1956
1957 /* Store the result and condition codes. */
1958 State.regs[ OP[1] ] = result;
1959
1960 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1961 PSW |= (z ? PSW_Z : 0);
1962
1963 trace_output (OP_UIMM_REG_REG);
1964
1965 return 4;
1966 }
1967
1968 /* xor reg, reg */
1969 int
1970 OP_120 ()
1971 {
1972 unsigned int op0, op1, result, z, s;
1973
1974 trace_input ("xor", OP_REG_REG, 0);
1975
1976 /* Compute the result. */
1977 op0 = State.regs[ OP[0] ];
1978 op1 = State.regs[ OP[1] ];
1979 result = op0 ^ op1;
1980
1981 /* Compute the condition codes. */
1982 z = (result == 0);
1983 s = (result & 0x80000000);
1984
1985 /* Store the result and condition codes. */
1986 State.regs[OP[1]] = result;
1987 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1988 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1989 trace_output (OP_REG_REG);
1990
1991 return 2;
1992 }
1993
1994 /* xori zero_extend(imm16), reg, reg */
1995 int
1996 OP_6A0 ()
1997 {
1998 unsigned int op0, op1, result, z, s;
1999
2000 trace_input ("xori", OP_UIMM_REG_REG, 0);
2001 op0 = OP[2];
2002 op1 = State.regs[ OP[0] ];
2003 result = op0 ^ op1;
2004
2005 /* Compute the condition codes. */
2006 z = (result == 0);
2007 s = (result & 0x80000000);
2008
2009 /* Store the result and condition codes. */
2010 State.regs[OP[1]] = result;
2011 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2012 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2013 trace_output (OP_UIMM_REG_REG);
2014
2015 return 4;
2016 }
2017
2018 /* not reg1, reg2 */
2019 int
2020 OP_20 ()
2021 {
2022 unsigned int op0, result, z, s;
2023
2024 trace_input ("not", OP_REG_REG_MOVE, 0);
2025 /* Compute the result. */
2026 op0 = State.regs[ OP[0] ];
2027 result = ~op0;
2028
2029 /* Compute the condition codes. */
2030 z = (result == 0);
2031 s = (result & 0x80000000);
2032
2033 /* Store the result and condition codes. */
2034 State.regs[OP[1]] = result;
2035 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2036 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2037 trace_output (OP_REG_REG_MOVE);
2038
2039 return 2;
2040 }
2041
2042 /* set1 */
2043 int
2044 OP_7C0 ()
2045 {
2046 unsigned int op0, op1, op2;
2047 int temp;
2048
2049 trace_input ("set1", OP_BIT, 0);
2050 op0 = State.regs[ OP[0] ];
2051 op1 = OP[1] & 0x7;
2052 temp = SEXT16 (OP[2]);
2053 op2 = temp;
2054 temp = load_mem (op0 + op2, 1);
2055 PSW &= ~PSW_Z;
2056 if ((temp & (1 << op1)) == 0)
2057 PSW |= PSW_Z;
2058 temp |= (1 << op1);
2059 store_mem (op0 + op2, 1, temp);
2060 trace_output (OP_BIT);
2061
2062 return 4;
2063 }
2064
2065 /* not1 */
2066 int
2067 OP_47C0 ()
2068 {
2069 unsigned int op0, op1, op2;
2070 int temp;
2071
2072 trace_input ("not1", OP_BIT, 0);
2073 op0 = State.regs[ OP[0] ];
2074 op1 = OP[1] & 0x7;
2075 temp = SEXT16 (OP[2]);
2076 op2 = temp;
2077 temp = load_mem (op0 + op2, 1);
2078 PSW &= ~PSW_Z;
2079 if ((temp & (1 << op1)) == 0)
2080 PSW |= PSW_Z;
2081 temp ^= (1 << op1);
2082 store_mem (op0 + op2, 1, temp);
2083 trace_output (OP_BIT);
2084
2085 return 4;
2086 }
2087
2088 /* clr1 */
2089 int
2090 OP_87C0 ()
2091 {
2092 unsigned int op0, op1, op2;
2093 int temp;
2094
2095 trace_input ("clr1", OP_BIT, 0);
2096 op0 = State.regs[ OP[0] ];
2097 op1 = OP[1] & 0x7;
2098 temp = SEXT16 (OP[2]);
2099 op2 = temp;
2100 temp = load_mem (op0 + op2, 1);
2101 PSW &= ~PSW_Z;
2102 if ((temp & (1 << op1)) == 0)
2103 PSW |= PSW_Z;
2104 temp &= ~(1 << op1);
2105 store_mem (op0 + op2, 1, temp);
2106 trace_output (OP_BIT);
2107
2108 return 4;
2109 }
2110
2111 /* tst1 */
2112 int
2113 OP_C7C0 ()
2114 {
2115 unsigned int op0, op1, op2;
2116 int temp;
2117
2118 trace_input ("tst1", OP_BIT, 0);
2119 op0 = State.regs[ OP[0] ];
2120 op1 = OP[1] & 0x7;
2121 temp = SEXT16 (OP[2]);
2122 op2 = temp;
2123 temp = load_mem (op0 + op2, 1);
2124 PSW &= ~PSW_Z;
2125 if ((temp & (1 << op1)) == 0)
2126 PSW |= PSW_Z;
2127 trace_output (OP_BIT);
2128
2129 return 4;
2130 }
2131
2132 /* breakpoint */
2133 int
2134 OP_FFFF ()
2135 {
2136 State.exception = SIGTRAP;
2137 return -4;
2138 }
2139
2140 /* di */
2141 int
2142 OP_16007E0 ()
2143 {
2144 trace_input ("di", OP_NONE, 0);
2145 PSW |= PSW_ID;
2146 trace_output (OP_NONE);
2147
2148 return 4;
2149 }
2150
2151 /* ei */
2152 int
2153 OP_16087E0 ()
2154 {
2155 trace_input ("ei", OP_NONE, 0);
2156 PSW &= ~PSW_ID;
2157 trace_output (OP_NONE);
2158
2159 return 4;
2160 }
2161
2162 /* halt */
2163 int
2164 OP_12007E0 ()
2165 {
2166 trace_input ("halt", OP_NONE, 0);
2167 /* FIXME this should put processor into a mode where NMI still handled */
2168 State.exception = SIGQUIT;
2169 trace_output (OP_NONE);
2170
2171 return 4;
2172 }
2173
2174 /* reti */
2175 int
2176 OP_14007E0 ()
2177 {
2178 trace_input ("reti", OP_NONE, 0);
2179 trace_output (OP_NONE);
2180
2181 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
2182 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
2183 {
2184 PC = FEPC - 4;
2185 PSW = FEPSW;
2186 }
2187 else
2188 {
2189 PC = EIPC - 4;
2190 PSW = EIPSW;
2191 }
2192
2193 return 0;
2194 }
2195
2196 /* trap */
2197 int
2198 OP_10007E0 ()
2199 {
2200 trace_input ("trap", OP_TRAP, 0);
2201 trace_output (OP_TRAP);
2202
2203 /* Trap 31 is used for simulating OS I/O functions */
2204
2205 if (OP[0] == 31)
2206 {
2207 int save_errno = errno;
2208 errno = 0;
2209
2210 /* Registers passed to trap 0 */
2211
2212 #define FUNC State.regs[6] /* function number, return value */
2213 #define PARM1 State.regs[7] /* optional parm 1 */
2214 #define PARM2 State.regs[8] /* optional parm 2 */
2215 #define PARM3 State.regs[9] /* optional parm 3 */
2216
2217 /* Registers set by trap 0 */
2218
2219 #define RETVAL State.regs[10] /* return value */
2220 #define RETERR State.regs[11] /* return error code */
2221
2222 /* Turn a pointer in a register into a pointer into real memory. */
2223
2224 #define MEMPTR(x) (map (x))
2225
2226 switch (FUNC)
2227 {
2228
2229 #if !defined(__GO32__) && !defined(_WIN32)
2230 #ifdef SYS_fork
2231 case SYS_fork:
2232 RETVAL = fork ();
2233 break;
2234 #endif
2235 #endif
2236
2237 #if !defined(__GO32__) && !defined(_WIN32)
2238 #ifdef SYS_execv
2239 case SYS_execve:
2240 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2241 (char **)MEMPTR (PARM3));
2242 break;
2243 #endif
2244 #endif
2245
2246 #if !defined(__GO32__) && !defined(_WIN32)
2247 #ifdef SYS_execv
2248 case SYS_execv:
2249 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2250 break;
2251 #endif
2252 #endif
2253
2254 #if 0
2255 #ifdef SYS_pipe
2256 case SYS_pipe:
2257 {
2258 reg_t buf;
2259 int host_fd[2];
2260
2261 buf = PARM1;
2262 RETVAL = pipe (host_fd);
2263 SW (buf, host_fd[0]);
2264 buf += sizeof(uint16);
2265 SW (buf, host_fd[1]);
2266 }
2267 break;
2268 #endif
2269 #endif
2270
2271 #if 0
2272 #ifdef SYS_wait
2273 case SYS_wait:
2274 {
2275 int status;
2276
2277 RETVAL = wait (&status);
2278 SW (PARM1, status);
2279 }
2280 break;
2281 #endif
2282 #endif
2283
2284 #ifdef SYS_read
2285 case SYS_read:
2286 RETVAL = sim_io_read (simulator, PARM1, MEMPTR (PARM2), PARM3);
2287 break;
2288 #endif
2289
2290 #ifdef SYS_write
2291 case SYS_write:
2292 if (PARM1 == 1)
2293 RETVAL = sim_io_write_stdout (simulator, MEMPTR (PARM2), PARM3);
2294 else
2295 RETVAL = sim_io_write (simulator, PARM1, MEMPTR (PARM2), PARM3);
2296 break;
2297 #endif
2298
2299 #ifdef SYS_lseek
2300 case SYS_lseek:
2301 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
2302 break;
2303 #endif
2304
2305 #ifdef SYS_close
2306 case SYS_close:
2307 RETVAL = sim_io_close (simulator, PARM1);
2308 break;
2309 #endif
2310
2311 #ifdef SYS_open
2312 case SYS_open:
2313 RETVAL = sim_io_open (simulator, MEMPTR (PARM1), PARM2);
2314 break;
2315 #endif
2316
2317 #ifdef SYS_exit
2318 case SYS_exit:
2319 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2320 State.exception = PARM1 & 0xffff; /* get signal encoded by kill */
2321 else if (PARM1 == 0xdead)
2322 State.exception = SIGABRT; /* old libraries */
2323 else
2324 State.exception = SIG_V850_EXIT; /* PARM1 has exit status encoded */
2325 break;
2326 #endif
2327
2328 #if !defined(__GO32__) && !defined(_WIN32)
2329 #ifdef SYS_stat
2330 case SYS_stat: /* added at hmsi */
2331 /* stat system call */
2332 {
2333 struct stat host_stat;
2334 reg_t buf;
2335
2336 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2337
2338 buf = PARM2;
2339
2340 /* Just wild-assed guesses. */
2341 store_mem (buf, 2, host_stat.st_dev);
2342 store_mem (buf + 2, 2, host_stat.st_ino);
2343 store_mem (buf + 4, 4, host_stat.st_mode);
2344 store_mem (buf + 8, 2, host_stat.st_nlink);
2345 store_mem (buf + 10, 2, host_stat.st_uid);
2346 store_mem (buf + 12, 2, host_stat.st_gid);
2347 store_mem (buf + 14, 2, host_stat.st_rdev);
2348 store_mem (buf + 16, 4, host_stat.st_size);
2349 store_mem (buf + 20, 4, host_stat.st_atime);
2350 store_mem (buf + 28, 4, host_stat.st_mtime);
2351 store_mem (buf + 36, 4, host_stat.st_ctime);
2352 }
2353 break;
2354 #endif
2355 #endif
2356
2357 #if !defined(__GO32__) && !defined(_WIN32)
2358 #ifdef SYS_chown
2359 case SYS_chown:
2360 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2361 break;
2362 #endif
2363 #endif
2364
2365 #ifdef SYS_chmod
2366 #if HAVE_CHMOD
2367 case SYS_chmod:
2368 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2369 break;
2370 #endif
2371 #endif
2372
2373 #ifdef SYS_time
2374 #if HAVE_TIME
2375 case SYS_time:
2376 {
2377 time_t now;
2378 RETVAL = time (&now);
2379 store_mem (PARM1, 4, now);
2380 }
2381 break;
2382 #endif
2383 #endif
2384
2385 #if !defined(__GO32__) && !defined(_WIN32)
2386 #ifdef SYS_times
2387 case SYS_times:
2388 {
2389 struct tms tms;
2390 RETVAL = times (&tms);
2391 store_mem (PARM1, 4, tms.tms_utime);
2392 store_mem (PARM1 + 4, 4, tms.tms_stime);
2393 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2394 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2395 break;
2396 }
2397 #endif
2398 #endif
2399
2400 #ifdef SYS_gettimeofday
2401 #if !defined(__GO32__) && !defined(_WIN32)
2402 case SYS_gettimeofday:
2403 {
2404 struct timeval t;
2405 struct timezone tz;
2406 RETVAL = gettimeofday (&t, &tz);
2407 store_mem (PARM1, 4, t.tv_sec);
2408 store_mem (PARM1 + 4, 4, t.tv_usec);
2409 store_mem (PARM2, 4, tz.tz_minuteswest);
2410 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2411 break;
2412 }
2413 #endif
2414 #endif
2415
2416 #ifdef SYS_utime
2417 #if HAVE_UTIME
2418 case SYS_utime:
2419 /* Cast the second argument to void *, to avoid type mismatch
2420 if a prototype is present. */
2421 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2422 break;
2423 #endif
2424 #endif
2425
2426 default:
2427 abort ();
2428 }
2429 RETERR = errno;
2430 errno = save_errno;
2431
2432 return 4;
2433 }
2434 else
2435 { /* Trap 0 -> 30 */
2436 EIPC = PC + 4;
2437 EIPSW = PSW;
2438 /* Mask out EICC */
2439 ECR &= 0xffff0000;
2440 ECR |= 0x40 + OP[0];
2441 /* Flag that we are now doing exception processing. */
2442 PSW |= PSW_EP | PSW_ID;
2443 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2444
2445 return 0;
2446 }
2447 }
2448
2449 /* ldsr, reg,reg */
2450 int
2451 OP_2007E0 ()
2452 {
2453 trace_input ("ldsr", OP_LDSR, 0);
2454
2455 State.sregs[ OP[1] ] = State.regs[ OP[0] ];
2456
2457 trace_output (OP_LDSR);
2458
2459 return 4;
2460 }
2461
2462 /* stsr */
2463 int
2464 OP_4007E0 ()
2465 {
2466 trace_input ("stsr", OP_STSR, 0);
2467
2468 State.regs[ OP[1] ] = State.sregs[ OP[0] ];
2469
2470 trace_output (OP_STSR);
2471
2472 return 4;
2473 }
2474
2475 /* tst1 reg2, [reg1] */
2476 int
2477 OP_E607E0 (void)
2478 {
2479 int temp;
2480
2481 trace_input ("tst1", OP_BIT_LOAD, 1);
2482
2483 temp = load_mem (State.regs[ OP[0] ], 1);
2484
2485 PSW &= ~PSW_Z;
2486 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
2487 PSW |= PSW_Z;
2488
2489 trace_output (OP_BIT_LOAD);
2490
2491 return 4;
2492 }
2493
2494 /* mulu reg1, reg2, reg3 */
2495 int
2496 OP_22207E0 (void)
2497 {
2498 trace_input ("mulu", OP_REG_REG_REG, 0);
2499
2500 Multiply64 (false, State.regs[ OP[0] ]);
2501
2502 trace_output (OP_REG_REG_REG);
2503
2504 return 4;
2505 }
2506
2507 /* start-sanitize-v850e */
2508
2509 #define BIT_CHANGE_OP( name, binop ) \
2510 unsigned int bit; \
2511 unsigned int temp; \
2512 \
2513 trace_input (name, OP_BIT_CHANGE, 0); \
2514 \
2515 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2516 temp = load_mem (State.regs[ OP[0] ], 1); \
2517 \
2518 PSW &= ~PSW_Z; \
2519 if ((temp & bit) == 0) \
2520 PSW |= PSW_Z; \
2521 temp binop bit; \
2522 \
2523 store_mem (State.regs[ OP[0] ], 1, temp); \
2524 \
2525 trace_output (OP_BIT_CHANGE); \
2526 \
2527 return 4;
2528
2529 /* clr1 reg2, [reg1] */
2530 int
2531 OP_E407E0 (void)
2532 {
2533 BIT_CHANGE_OP ("clr1", &= ~ );
2534 }
2535
2536 /* not1 reg2, [reg1] */
2537 int
2538 OP_E207E0 (void)
2539 {
2540 BIT_CHANGE_OP ("not1", ^= );
2541 }
2542
2543 /* set1 */
2544 int
2545 OP_E007E0 (void)
2546 {
2547 BIT_CHANGE_OP ("set1", |= );
2548 }
2549
2550 /* sasf */
2551 int
2552 OP_20007E0 (void)
2553 {
2554 trace_input ("sasf", OP_EX1, 0);
2555
2556 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2557
2558 trace_output (OP_EX1);
2559
2560 return 4;
2561 }
2562 /* end-sanitize-v850e */
2563
2564 /* start-sanitize-v850eq */
2565 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2566 static void
2567 divun
2568 (
2569 unsigned int N,
2570 unsigned long int als,
2571 unsigned long int sfi,
2572 unsigned long int * quotient_ptr,
2573 unsigned long int * remainder_ptr,
2574 boolean * overflow_ptr
2575 )
2576 {
2577 unsigned long ald = sfi >> (N - 1);
2578 unsigned long alo = als;
2579 unsigned int Q = 1;
2580 unsigned int C;
2581 unsigned int S = 0;
2582 unsigned int i;
2583 unsigned int R1 = 1;
2584 unsigned int DBZ = (als == 0) ? 1 : 0;
2585 unsigned long alt = Q ? ~als : als;
2586
2587 /* 1st Loop */
2588 alo = ald + alt + Q;
2589 C = (((alt >> 31) & (ald >> 31))
2590 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2591 C = C ^ Q;
2592 Q = ~(C ^ S) & 1;
2593 R1 = (alo == 0) ? 0 : (R1 & Q);
2594 if ((S ^ (alo>>31)) && !C)
2595 {
2596 DBZ = 1;
2597 }
2598 S = alo >> 31;
2599 sfi = (sfi << (32-N+1)) | Q;
2600 ald = (alo << 1) | (sfi >> 31);
2601
2602 /* 2nd - N-1th Loop */
2603 for (i = 2; i < N; i++)
2604 {
2605 alt = Q ? ~als : als;
2606 alo = ald + alt + Q;
2607 C = (((alt >> 31) & (ald >> 31))
2608 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2609 C = C ^ Q;
2610 Q = ~(C ^ S) & 1;
2611 R1 = (alo == 0) ? 0 : (R1 & Q);
2612 if ((S ^ (alo>>31)) && !C && !DBZ)
2613 {
2614 DBZ = 1;
2615 }
2616 S = alo >> 31;
2617 sfi = (sfi << 1) | Q;
2618 ald = (alo << 1) | (sfi >> 31);
2619 }
2620
2621 /* Nth Loop */
2622 alt = Q ? ~als : als;
2623 alo = ald + alt + Q;
2624 C = (((alt >> 31) & (ald >> 31))
2625 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2626 C = C ^ Q;
2627 Q = ~(C ^ S) & 1;
2628 R1 = (alo == 0) ? 0 : (R1 & Q);
2629 if ((S ^ (alo>>31)) && !C)
2630 {
2631 DBZ = 1;
2632 }
2633
2634 * quotient_ptr = (sfi << 1) | Q;
2635 * remainder_ptr = Q ? alo : (alo + als);
2636 * overflow_ptr = DBZ | R1;
2637 }
2638
2639 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2640 static void
2641 divn
2642 (
2643 unsigned int N,
2644 unsigned long int als,
2645 unsigned long int sfi,
2646 signed long int * quotient_ptr,
2647 signed long int * remainder_ptr,
2648 boolean * overflow_ptr
2649 )
2650 {
2651 unsigned long ald = (signed long) sfi >> (N - 1);
2652 unsigned long alo = als;
2653 unsigned int SS = als >> 31;
2654 unsigned int SD = sfi >> 31;
2655 unsigned int R1 = 1;
2656 unsigned int OV;
2657 unsigned int DBZ = als == 0 ? 1 : 0;
2658 unsigned int Q = ~(SS ^ SD) & 1;
2659 unsigned int C;
2660 unsigned int S;
2661 unsigned int i;
2662 unsigned long alt = Q ? ~als : als;
2663
2664
2665 /* 1st Loop */
2666
2667 alo = ald + alt + Q;
2668 C = (((alt >> 31) & (ald >> 31))
2669 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2670 Q = C ^ SS;
2671 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2672 S = alo >> 31;
2673 sfi = (sfi << (32-N+1)) | Q;
2674 ald = (alo << 1) | (sfi >> 31);
2675 if ((alo >> 31) ^ (ald >> 31))
2676 {
2677 DBZ = 1;
2678 }
2679
2680 /* 2nd - N-1th Loop */
2681
2682 for (i = 2; i < N; i++)
2683 {
2684 alt = Q ? ~als : als;
2685 alo = ald + alt + Q;
2686 C = (((alt >> 31) & (ald >> 31))
2687 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2688 Q = C ^ SS;
2689 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2690 S = alo >> 31;
2691 sfi = (sfi << 1) | Q;
2692 ald = (alo << 1) | (sfi >> 31);
2693 if ((alo >> 31) ^ (ald >> 31))
2694 {
2695 DBZ = 1;
2696 }
2697 }
2698
2699 /* Nth Loop */
2700 alt = Q ? ~als : als;
2701 alo = ald + alt + Q;
2702 C = (((alt >> 31) & (ald >> 31))
2703 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2704 Q = C ^ SS;
2705 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2706 sfi = (sfi << (32-N+1));
2707 ald = alo;
2708
2709 /* End */
2710 if (alo != 0)
2711 {
2712 alt = Q ? ~als : als;
2713 alo = ald + alt + Q;
2714 }
2715 R1 = R1 & ((~alo >> 31) ^ SD);
2716 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2717 if (N != 32)
2718 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2719 else
2720 ald = sfi = sfi | Q;
2721
2722 OV = DBZ | ((alo == 0) ? 0 : R1);
2723
2724 * remainder_ptr = alo;
2725
2726 /* Adj */
2727 if (((alo != 0) && ((SS ^ SD) ^ R1))
2728 || ((alo == 0) && (SS ^ R1)))
2729 alo = ald + 1;
2730 else
2731 alo = ald;
2732
2733 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2734
2735 * quotient_ptr = alo;
2736 * overflow_ptr = OV;
2737 }
2738
2739 /* sdivun imm5, reg1, reg2, reg3 */
2740 int
2741 OP_1C207E0 (void)
2742 {
2743 unsigned long int quotient;
2744 unsigned long int remainder;
2745 unsigned long int divide_by;
2746 unsigned long int divide_this;
2747 boolean overflow = false;
2748 unsigned int imm5;
2749
2750 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2751
2752 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2753
2754 divide_by = State.regs[ OP[0] ];
2755 divide_this = State.regs[ OP[1] ] << imm5;
2756
2757 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2758
2759 State.regs[ OP[1] ] = quotient;
2760 State.regs[ OP[2] >> 11 ] = remainder;
2761
2762 /* Set condition codes. */
2763 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2764
2765 if (overflow) PSW |= PSW_OV;
2766 if (quotient == 0) PSW |= PSW_Z;
2767 if (quotient & 0x80000000) PSW |= PSW_S;
2768
2769 trace_output (OP_IMM_REG_REG_REG);
2770
2771 return 4;
2772 }
2773
2774 /* sdivn imm5, reg1, reg2, reg3 */
2775 int
2776 OP_1C007E0 (void)
2777 {
2778 signed long int quotient;
2779 signed long int remainder;
2780 signed long int divide_by;
2781 signed long int divide_this;
2782 boolean overflow = false;
2783 unsigned int imm5;
2784
2785 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2786
2787 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2788
2789 divide_by = State.regs[ OP[0] ];
2790 divide_this = State.regs[ OP[1] ] << imm5;
2791
2792 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2793
2794 State.regs[ OP[1] ] = quotient;
2795 State.regs[ OP[2] >> 11 ] = remainder;
2796
2797 /* Set condition codes. */
2798 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2799
2800 if (overflow) PSW |= PSW_OV;
2801 if (quotient == 0) PSW |= PSW_Z;
2802 if (quotient < 0) PSW |= PSW_S;
2803
2804 trace_output (OP_IMM_REG_REG_REG);
2805
2806 return 4;
2807 }
2808
2809 /* sdivhun imm5, reg1, reg2, reg3 */
2810 int
2811 OP_18207E0 (void)
2812 {
2813 unsigned long int quotient;
2814 unsigned long int remainder;
2815 unsigned long int divide_by;
2816 unsigned long int divide_this;
2817 boolean overflow = false;
2818 unsigned int imm5;
2819
2820 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2821
2822 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2823
2824 divide_by = State.regs[ OP[0] ] & 0xffff;
2825 divide_this = State.regs[ OP[1] ] << imm5;
2826
2827 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2828
2829 State.regs[ OP[1] ] = quotient;
2830 State.regs[ OP[2] >> 11 ] = remainder;
2831
2832 /* Set condition codes. */
2833 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2834
2835 if (overflow) PSW |= PSW_OV;
2836 if (quotient == 0) PSW |= PSW_Z;
2837 if (quotient & 0x80000000) PSW |= PSW_S;
2838
2839 trace_output (OP_IMM_REG_REG_REG);
2840
2841 return 4;
2842 }
2843
2844 /* sdivhn imm5, reg1, reg2, reg3 */
2845 int
2846 OP_18007E0 (void)
2847 {
2848 signed long int quotient;
2849 signed long int remainder;
2850 signed long int divide_by;
2851 signed long int divide_this;
2852 boolean overflow = false;
2853 unsigned int imm5;
2854
2855 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2856
2857 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2858
2859 divide_by = SEXT16 (State.regs[ OP[0] ]);
2860 divide_this = State.regs[ OP[1] ] << imm5;
2861
2862 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2863
2864 State.regs[ OP[1] ] = quotient;
2865 State.regs[ OP[2] >> 11 ] = remainder;
2866
2867 /* Set condition codes. */
2868 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2869
2870 if (overflow) PSW |= PSW_OV;
2871 if (quotient == 0) PSW |= PSW_Z;
2872 if (quotient < 0) PSW |= PSW_S;
2873
2874 trace_output (OP_IMM_REG_REG_REG);
2875
2876 return 4;
2877 }
2878 /* end-sanitize-v850eq */
2879
2880 /* start-sanitize-v850e */
2881 /* divu reg1, reg2, reg3 */
2882 int
2883 OP_2C207E0 (void)
2884 {
2885 unsigned long int quotient;
2886 unsigned long int remainder;
2887 unsigned long int divide_by;
2888 unsigned long int divide_this;
2889 boolean overflow = false;
2890
2891 if ((OP[3] & 0x3c0000) == 0)
2892 {
2893 trace_input ("divu", OP_REG_REG_REG, 0);
2894
2895 /* Compute the result. */
2896
2897 divide_by = State.regs[ OP[0] ];
2898 divide_this = State.regs[ OP[1] ];
2899
2900 if (divide_by == 0)
2901 {
2902 overflow = true;
2903 divide_by = 1;
2904 }
2905
2906 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2907 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2908
2909 /* Set condition codes. */
2910 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2911
2912 if (overflow) PSW |= PSW_OV;
2913 if (quotient == 0) PSW |= PSW_Z;
2914 if (quotient & 0x80000000) PSW |= PSW_S;
2915
2916 trace_output (OP_REG_REG_REG);
2917 }
2918 /* start-sanitize-v850eq */
2919 /* divun imm5, reg1, reg2, reg3 */
2920 else
2921 {
2922 unsigned int imm5;
2923
2924 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
2925
2926 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2927
2928 divide_by = State.regs[ OP[0] ];
2929 divide_this = State.regs[ OP[1] ];
2930
2931 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2932
2933 State.regs[ OP[1] ] = quotient;
2934 State.regs[ OP[2] >> 11 ] = remainder;
2935
2936 /* Set condition codes. */
2937 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2938
2939 if (overflow) PSW |= PSW_OV;
2940 if (quotient == 0) PSW |= PSW_Z;
2941 if (quotient & 0x80000000) PSW |= PSW_S;
2942
2943 trace_output (OP_IMM_REG_REG_REG);
2944 }
2945 /* end-sanitize-v850eq */
2946
2947 return 4;
2948 }
2949
2950 /* div reg1, reg2, reg3 */
2951 int
2952 OP_2C007E0 (void)
2953 {
2954 signed long int quotient;
2955 signed long int remainder;
2956 signed long int divide_by;
2957 signed long int divide_this;
2958 boolean overflow = false;
2959
2960 if ((OP[3] & 0x3c0000) == 0)
2961 {
2962 trace_input ("div", OP_REG_REG_REG, 0);
2963
2964 /* Compute the result. */
2965
2966 divide_by = State.regs[ OP[0] ];
2967 divide_this = State.regs[ OP[1] ];
2968
2969 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2970 {
2971 overflow = true;
2972 divide_by = 1;
2973 }
2974
2975 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2976 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2977
2978 /* Set condition codes. */
2979 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2980
2981 if (overflow) PSW |= PSW_OV;
2982 if (quotient == 0) PSW |= PSW_Z;
2983 if (quotient < 0) PSW |= PSW_S;
2984
2985 trace_output (OP_REG_REG_REG);
2986 }
2987 /* start-sanitize-v850eq */
2988 /* divn imm5, reg1, reg2, reg3 */
2989 else
2990 {
2991 unsigned int imm5;
2992
2993 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
2994
2995 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2996
2997 divide_by = State.regs[ OP[0] ];
2998 divide_this = State.regs[ OP[1] ];
2999
3000 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3001
3002 State.regs[ OP[1] ] = quotient;
3003 State.regs[ OP[2] >> 11 ] = remainder;
3004
3005 /* Set condition codes. */
3006 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3007
3008 if (overflow) PSW |= PSW_OV;
3009 if (quotient == 0) PSW |= PSW_Z;
3010 if (quotient < 0) PSW |= PSW_S;
3011
3012 trace_output (OP_IMM_REG_REG_REG);
3013 }
3014 /* end-sanitize-v850eq */
3015
3016 return 4;
3017 }
3018
3019 /* divhu reg1, reg2, reg3 */
3020 int
3021 OP_28207E0 (void)
3022 {
3023 unsigned long int quotient;
3024 unsigned long int remainder;
3025 unsigned long int divide_by;
3026 unsigned long int divide_this;
3027 boolean overflow = false;
3028
3029 if ((OP[3] & 0x3c0000) == 0)
3030 {
3031 trace_input ("divhu", OP_REG_REG_REG, 0);
3032
3033 /* Compute the result. */
3034
3035 divide_by = State.regs[ OP[0] ] & 0xffff;
3036 divide_this = State.regs[ OP[1] ];
3037
3038 if (divide_by == 0)
3039 {
3040 overflow = true;
3041 divide_by = 1;
3042 }
3043
3044 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3045 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3046
3047 /* Set condition codes. */
3048 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3049
3050 if (overflow) PSW |= PSW_OV;
3051 if (quotient == 0) PSW |= PSW_Z;
3052 if (quotient & 0x80000000) PSW |= PSW_S;
3053
3054 trace_output (OP_REG_REG_REG);
3055 }
3056 /* start-sanitize-v850eq */
3057 /* divhun imm5, reg1, reg2, reg3 */
3058 else
3059 {
3060 unsigned int imm5;
3061
3062 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
3063
3064 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3065
3066 divide_by = State.regs[ OP[0] ] & 0xffff;
3067 divide_this = State.regs[ OP[1] ];
3068
3069 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3070
3071 State.regs[ OP[1] ] = quotient;
3072 State.regs[ OP[2] >> 11 ] = remainder;
3073
3074 /* Set condition codes. */
3075 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3076
3077 if (overflow) PSW |= PSW_OV;
3078 if (quotient == 0) PSW |= PSW_Z;
3079 if (quotient & 0x80000000) PSW |= PSW_S;
3080
3081 trace_output (OP_IMM_REG_REG_REG);
3082 }
3083 /* end-sanitize-v850eq */
3084
3085 return 4;
3086 }
3087
3088 /* divh reg1, reg2, reg3 */
3089 int
3090 OP_28007E0 (void)
3091 {
3092 signed long int quotient;
3093 signed long int remainder;
3094 signed long int divide_by;
3095 signed long int divide_this;
3096 boolean overflow = false;
3097
3098 if ((OP[3] & 0x3c0000) == 0)
3099 {
3100 trace_input ("divh", OP_REG_REG_REG, 0);
3101
3102 /* Compute the result. */
3103
3104 divide_by = State.regs[ OP[0] ];
3105 divide_this = SEXT16 (State.regs[ OP[1] ]);
3106
3107 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3108 {
3109 overflow = true;
3110 divide_by = 1;
3111 }
3112
3113 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3114 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3115
3116 /* Set condition codes. */
3117 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3118
3119 if (overflow) PSW |= PSW_OV;
3120 if (quotient == 0) PSW |= PSW_Z;
3121 if (quotient < 0) PSW |= PSW_S;
3122
3123 trace_output (OP_REG_REG_REG);
3124 }
3125 /* start-sanitize-v850eq */
3126 /* divhn imm5, reg1, reg2, reg3 */
3127 else
3128 {
3129 unsigned int imm5;
3130
3131 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
3132
3133 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3134
3135 divide_by = SEXT16 (State.regs[ OP[0] ]);
3136 divide_this = State.regs[ OP[1] ];
3137
3138 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3139
3140 State.regs[ OP[1] ] = quotient;
3141 State.regs[ OP[2] >> 11 ] = remainder;
3142
3143 /* Set condition codes. */
3144 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3145
3146 if (overflow) PSW |= PSW_OV;
3147 if (quotient == 0) PSW |= PSW_Z;
3148 if (quotient < 0) PSW |= PSW_S;
3149
3150 trace_output (OP_IMM_REG_REG_REG);
3151 }
3152 /* end-sanitize-v850eq */
3153
3154 return 4;
3155 }
3156
3157 /* mulu imm9, reg2, reg3 */
3158 int
3159 OP_24207E0 (void)
3160 {
3161 trace_input ("mulu", OP_IMM_REG_REG, 0);
3162
3163 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3164
3165 trace_output (OP_IMM_REG_REG);
3166
3167 return 4;
3168 }
3169
3170 /* mul imm9, reg2, reg3 */
3171 int
3172 OP_24007E0 (void)
3173 {
3174 trace_input ("mul", OP_IMM_REG_REG, 0);
3175
3176 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3177
3178 trace_output (OP_IMM_REG_REG);
3179
3180 return 4;
3181 }
3182
3183 /* cmov imm5, reg2, reg3 */
3184 int
3185 OP_30007E0 (void)
3186 {
3187 trace_input ("cmov", OP_IMM_REG_REG, 0);
3188
3189 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
3190
3191 trace_output (OP_IMM_REG_REG);
3192
3193 return 4;
3194
3195 }
3196
3197 /* ctret */
3198 int
3199 OP_14407E0 (void)
3200 {
3201 trace_input ("ctret", OP_NONE, 0);
3202
3203 PC = CTPC;
3204 PSW = CTPSW;
3205
3206 trace_output (OP_NONE);
3207
3208 return 0;
3209 }
3210
3211 /* hsw */
3212 int
3213 OP_34407E0 (void)
3214 {
3215 unsigned long value;
3216
3217 trace_input ("hsw", OP_REG_REG3, 0);
3218
3219 value = State.regs[ OP[ 1 ] ];
3220 value >>= 16;
3221 value |= (State.regs[ OP[ 1 ] ] << 16);
3222
3223 State.regs[ OP[2] >> 11 ] = value;
3224
3225 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3226
3227 if (value == 0) PSW |= PSW_Z;
3228 if (value & 0x80000000) PSW |= PSW_S;
3229 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3230
3231 trace_output (OP_REG_REG3);
3232
3233 return 4;
3234 }
3235
3236 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
3237
3238 /* bsw */
3239 int
3240 OP_34007E0 (void)
3241 {
3242 unsigned long value;
3243
3244 trace_input ("bsw", OP_REG_REG3, 0);
3245
3246 value = State.regs[ OP[ 1 ] ];
3247 value >>= 24;
3248 value |= (State.regs[ OP[ 1 ] ] << 24);
3249 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
3250 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
3251
3252 State.regs[ OP[2] >> 11 ] = value;
3253
3254 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3255
3256 if (value == 0) PSW |= PSW_Z;
3257 if (value & 0x80000000) PSW |= PSW_S;
3258 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
3259
3260 trace_output (OP_REG_REG3);
3261
3262 return 4;
3263 }
3264
3265 /* bsh */
3266 int
3267 OP_34207E0 (void)
3268 {
3269 unsigned long value;
3270
3271 trace_input ("bsh", OP_REG_REG3, 0);
3272
3273 value = State.regs[ OP[ 1 ] ];
3274 value >>= 8;
3275 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
3276 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
3277
3278 State.regs[ OP[2] >> 11 ] = value;
3279
3280 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3281
3282 if (value == 0) PSW |= PSW_Z;
3283 if (value & 0x80000000) PSW |= PSW_S;
3284 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
3285
3286 trace_output (OP_REG_REG3);
3287
3288 return 4;
3289 }
3290
3291 /* pushml list18 */
3292 /* ld.hu */
3293 int
3294 OP_107E0 (void)
3295 {
3296 if (OP[ 1 ] == 0)
3297 {
3298 int i;
3299
3300 trace_input ("pushml", OP_PUSHPOP3, 0);
3301
3302 /* Store the registers with lower number registers being placed at higher addresses. */
3303 for (i = 0; i < 15; i++)
3304 if ((OP[3] & (1 << type3_regs[ i ])))
3305 {
3306 SP -= 4;
3307 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
3308 }
3309
3310 if (OP[3] & (1 << 3))
3311 {
3312 SP -= 4;
3313
3314 store_mem (SP & ~ 3, 4, PSW);
3315 }
3316
3317 if (OP[3] & (1 << 19))
3318 {
3319 SP -= 8;
3320
3321 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3322 {
3323 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3324 store_mem ( SP & ~ 3, 4, FEPSW);
3325 }
3326 else
3327 {
3328 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3329 store_mem ( SP & ~ 3, 4, EIPSW);
3330 }
3331 }
3332
3333 trace_output (OP_PUSHPOP2);
3334 }
3335 else
3336 {
3337 int adr;
3338
3339 trace_input ("ld.hu", OP_LOAD32, 2);
3340
3341 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
3342 adr &= ~0x1;
3343
3344 State.regs[ OP[1] ] = load_mem (adr, 2);
3345
3346 trace_output (OP_LOAD32);
3347 }
3348
3349 return 4;
3350 }
3351
3352 /* prepare list12, imm5 */
3353 /* ld.bu */
3354 int
3355 OP_10780 (void)
3356 {
3357 if (OP[ 1 ] == 0)
3358 {
3359 int i;
3360
3361 trace_input ("prepare", OP_PUSHPOP1, 0);
3362
3363 /* Store the registers with lower number registers being placed at higher addresses. */
3364 for (i = 0; i < 12; i++)
3365 if ((OP[3] & (1 << type1_regs[ i ])))
3366 {
3367 SP -= 4;
3368 store_mem (SP, 4, State.regs[ 20 + i ]);
3369 }
3370
3371 SP -= (OP[3] & 0x3e) << 1;
3372
3373 trace_output (OP_PUSHPOP1);
3374 }
3375 else
3376 {
3377 int adr;
3378
3379 trace_input ("ld.bu", OP_LOAD32, 1);
3380
3381 adr = (State.regs[ OP[0] ]
3382 + (SEXT16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
3383
3384 State.regs[ OP[1] ] = load_mem (adr, 1);
3385
3386 trace_output (OP_LOAD32);
3387 }
3388
3389 return 4;
3390 }
3391
3392 /* prepare list12, imm5, imm32 */
3393 int
3394 OP_1B0780 (void)
3395 {
3396 int i;
3397
3398 trace_input ("prepare", OP_PUSHPOP1, 0);
3399
3400 /* Store the registers with lower number registers being placed at higher addresses. */
3401 for (i = 0; i < 12; i++)
3402 if ((OP[3] & (1 << type1_regs[ i ])))
3403 {
3404 SP -= 4;
3405 store_mem (SP, 4, State.regs[ 20 + i ]);
3406 }
3407
3408 SP -= (OP[3] & 0x3e) << 1;
3409
3410 EP = load_mem (PC + 4, 4);
3411
3412 trace_output (OP_PUSHPOP1);
3413
3414 return 8;
3415 }
3416
3417 /* prepare list12, imm5, imm16-32 */
3418 int
3419 OP_130780 (void)
3420 {
3421 int i;
3422
3423 trace_input ("prepare", OP_PUSHPOP1, 0);
3424
3425 /* Store the registers with lower number registers being placed at higher addresses. */
3426 for (i = 0; i < 12; i++)
3427 if ((OP[3] & (1 << type1_regs[ i ])))
3428 {
3429 SP -= 4;
3430 store_mem (SP, 4, State.regs[ 20 + i ]);
3431 }
3432
3433 SP -= (OP[3] & 0x3e) << 1;
3434
3435 EP = load_mem (PC + 4, 2) << 16;
3436
3437 trace_output (OP_PUSHPOP1);
3438
3439 return 6;
3440 }
3441
3442 /* prepare list12, imm5, imm16 */
3443 int
3444 OP_B0780 (void)
3445 {
3446 int i;
3447
3448 trace_input ("prepare", OP_PUSHPOP1, 0);
3449
3450 /* Store the registers with lower number registers being placed at higher addresses. */
3451 for (i = 0; i < 12; i++)
3452 if ((OP[3] & (1 << type1_regs[ i ])))
3453 {
3454 SP -= 4;
3455 store_mem (SP, 4, State.regs[ 20 + i ]);
3456 }
3457
3458 SP -= (OP[3] & 0x3e) << 1;
3459
3460 EP = SEXT16 (load_mem (PC + 4, 2));
3461
3462 trace_output (OP_PUSHPOP1);
3463
3464 return 6;
3465 }
3466
3467 /* prepare list12, imm5, sp */
3468 int
3469 OP_30780 (void)
3470 {
3471 int i;
3472
3473 trace_input ("prepare", OP_PUSHPOP1, 0);
3474
3475 /* Store the registers with lower number registers being placed at higher addresses. */
3476 for (i = 0; i < 12; i++)
3477 if ((OP[3] & (1 << type1_regs[ i ])))
3478 {
3479 SP -= 4;
3480 store_mem (SP, 4, State.regs[ 20 + i ]);
3481 }
3482
3483 SP -= (OP[3] & 0x3e) << 1;
3484
3485 EP = SP;
3486
3487 trace_output (OP_PUSHPOP1);
3488
3489 return 4;
3490 }
3491
3492 /* sld.hu */
3493 int
3494 OP_70 (void)
3495 {
3496 unsigned long result;
3497
3498 result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
3499
3500 /* start-sanitize-v850eq */
3501 #ifdef ARCH_v850eq
3502 trace_input ("sld.h", OP_LOAD16, 2);
3503
3504 State.regs[ OP[1] ] = SEXT16 (result);
3505 #else
3506 /* end-sanitize-v850eq */
3507 trace_input ("sld.hu", OP_LOAD16, 2);
3508
3509 State.regs[ OP[1] ] = result;
3510 /* start-sanitize-v850eq */
3511 #endif
3512 /* end-sanitize-v850eq */
3513
3514 trace_output (OP_LOAD16);
3515
3516 return 2;
3517 }
3518
3519 /* cmov reg1, reg2, reg3 */
3520 int
3521 OP_32007E0 (void)
3522 {
3523 trace_input ("cmov", OP_REG_REG_REG, 0);
3524
3525 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
3526
3527 trace_output (OP_REG_REG_REG);
3528
3529 return 4;
3530 }
3531
3532 /* mul reg1, reg2, reg3 */
3533 int
3534 OP_22007E0 (void)
3535 {
3536 trace_input ("mul", OP_REG_REG_REG, 0);
3537
3538 Multiply64 (true, State.regs[ OP[0] ]);
3539
3540 trace_output (OP_REG_REG_REG);
3541
3542 return 4;
3543 }
3544
3545 /* end-sanitize-v850e */
3546 /* start-sanitize-v850eq */
3547
3548 /* popmh list18 */
3549 int
3550 OP_307F0 (void)
3551 {
3552 int i;
3553
3554 trace_input ("popmh", OP_PUSHPOP2, 0);
3555
3556 if (OP[3] & (1 << 19))
3557 {
3558 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3559 {
3560 FEPSW = load_mem ( SP & ~ 3, 4);
3561 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3562 }
3563 else
3564 {
3565 EIPSW = load_mem ( SP & ~ 3, 4);
3566 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3567 }
3568
3569 SP += 8;
3570 }
3571
3572 /* Load the registers with lower number registers being retrieved from higher addresses. */
3573 for (i = 16; i--;)
3574 if ((OP[3] & (1 << type2_regs[ i ])))
3575 {
3576 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
3577 SP += 4;
3578 }
3579
3580 trace_output (OP_PUSHPOP2);
3581
3582 return 4;
3583 }
3584
3585 /* popml lsit18 */
3586 int
3587 OP_107F0 (void)
3588 {
3589 int i;
3590
3591 trace_input ("popml", OP_PUSHPOP3, 0);
3592
3593 if (OP[3] & (1 << 19))
3594 {
3595 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3596 {
3597 FEPSW = load_mem ( SP & ~ 3, 4);
3598 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3599 }
3600 else
3601 {
3602 EIPSW = load_mem ( SP & ~ 3, 4);
3603 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3604 }
3605
3606 SP += 8;
3607 }
3608
3609 if (OP[3] & (1 << 3))
3610 {
3611 PSW = load_mem (SP & ~ 3, 4);
3612 SP += 4;
3613 }
3614
3615 /* Load the registers with lower number registers being retrieved from higher addresses. */
3616 for (i = 15; i--;)
3617 if ((OP[3] & (1 << type3_regs[ i ])))
3618 {
3619 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
3620 SP += 4;
3621 }
3622
3623 trace_output (OP_PUSHPOP2);
3624
3625 return 4;
3626 }
3627
3628 /* pushmh list18 */
3629 int
3630 OP_307E0 (void)
3631 {
3632 int i;
3633
3634 trace_input ("pushmh", OP_PUSHPOP2, 0);
3635
3636 /* Store the registers with lower number registers being placed at higher addresses. */
3637 for (i = 0; i < 16; i++)
3638 if ((OP[3] & (1 << type2_regs[ i ])))
3639 {
3640 SP -= 4;
3641 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
3642 }
3643
3644 if (OP[3] & (1 << 19))
3645 {
3646 SP -= 8;
3647
3648 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3649 {
3650 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3651 store_mem ( SP & ~ 3, 4, FEPSW);
3652 }
3653 else
3654 {
3655 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3656 store_mem ( SP & ~ 3, 4, EIPSW);
3657 }
3658 }
3659
3660 trace_output (OP_PUSHPOP2);
3661
3662 return 4;
3663 }
3664
3665 /* end-sanitize-v850eq */