4 #include "sys/syscall.h"
38 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
39 static void trace_output
PARAMS ((enum op_types result
));
40 static int init_text_p
= 0;
41 static asection
*text
;
42 static bfd_vma text_start
;
43 static bfd_vma text_end
;
46 #ifndef SIZE_INSTRUCTION
47 #define SIZE_INSTRUCTION 6
51 #define SIZE_OPERANDS 16
55 #define SIZE_VALUES 11
59 #define SIZE_LOCATION 40
63 trace_input (name
, type
, size
)
75 const char *functionname
;
76 unsigned int linenumber
;
78 if ((v850_debug
& DEBUG_TRACE
) == 0)
85 for (s
= exec_bfd
->sections
; s
; s
= s
->next
)
86 if (strcmp (bfd_get_section_name (exec_bfd
, s
), ".text") == 0)
89 text_start
= bfd_get_section_vma (exec_bfd
, s
);
90 text_end
= text_start
+ bfd_section_size (exec_bfd
, s
);
95 if (text
&& PC
>= text_start
&& PC
< text_end
)
97 filename
= (const char *)0;
98 functionname
= (const char *)0;
100 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, PC
- text_start
,
101 &filename
, &functionname
, &linenumber
))
106 sprintf (p
, "Line %5d ", linenumber
);
112 sprintf (p
, "Func %s ", functionname
);
117 char *q
= (char *) strrchr (filename
, '/');
118 sprintf (p
, "File %s ", (q
) ? q
+1 : filename
);
127 (*v850_callback
->printf_filtered
) (v850_callback
, "0x%.8x: %-*.*s %-*s",
129 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
130 SIZE_INSTRUCTION
, name
);
137 strcpy (buf
, "unknown");
141 sprintf (buf
, "%d", OP
[0]);
145 sprintf (buf
, "r%d", OP
[0]);
150 case OP_REG_REG_MOVE
:
151 sprintf (buf
, "r%d,r%d", OP
[0], OP
[1]);
156 case OP_IMM_REG_MOVE
:
157 sprintf (buf
, "%d,r%d", OP
[0], OP
[1]);
161 sprintf (buf
, "%d", SEXT9 (OP
[0]));
165 sprintf (buf
, "%d[r30],r%d", OP
[1] * size
, OP
[0]);
169 sprintf (buf
, "r%d,%d[r30]", OP
[0], OP
[1] * size
);
173 sprintf (buf
, "%d[r%d],r%d", SEXT16 (OP
[2]) & ~0x1, OP
[0], OP
[1]);
177 sprintf (buf
, "r%d,%d[r%d]", OP
[1], SEXT16 (OP
[2] & ~0x1), OP
[0]);
181 sprintf (buf
, "%d,r%d", SEXT22 (OP
[0]), OP
[1]);
185 sprintf (buf
, "%d,r%d,r%d", SEXT16 (OP
[0]), OP
[1], OP
[2]);
188 case OP_UIMM_REG_REG
:
189 sprintf (buf
, "%d,r%d,r%d", OP
[0] & 0xffff, OP
[1], OP
[2]);
193 sprintf (buf
, "%d,%d[r%d]", OP
[1] & 0x7, SEXT16 (OP
[2]), OP
[0]);
199 default: cond
= "?"; break;
200 case 0x0: cond
= "v"; break;
201 case 0x1: cond
= "c"; break;
202 case 0x2: cond
= "z"; break;
203 case 0x3: cond
= "nh"; break;
204 case 0x4: cond
= "s"; break;
205 case 0x5: cond
= "t"; break;
206 case 0x6: cond
= "lt"; break;
207 case 0x7: cond
= "le"; break;
208 case 0x8: cond
= "nv"; break;
209 case 0x9: cond
= "nc"; break;
210 case 0xa: cond
= "nz"; break;
211 case 0xb: cond
= "h"; break;
212 case 0xc: cond
= "ns"; break;
213 case 0xd: cond
= "sa"; break;
214 case 0xe: cond
= "ge"; break;
215 case 0xf: cond
= "gt"; break;
218 sprintf (buf
, "%s,r%d", cond
, OP
[1]);
227 sprintf (buf
, "r%d,s%d", OP
[0], OP
[1]);
231 if ((v850_debug
& DEBUG_VALUES
) == 0)
233 (*v850_callback
->printf_filtered
) (v850_callback
, "%s\n", buf
);
237 (*v850_callback
->printf_filtered
) (v850_callback
, "%-*s", SIZE_OPERANDS
, buf
);
248 case OP_REG_REG_MOVE
:
249 values
[0] = State
.regs
[OP
[0]];
255 values
[0] = State
.regs
[OP
[1]];
256 values
[1] = State
.regs
[OP
[0]];
262 values
[0] = SEXT5 (OP
[0]);
267 case OP_IMM_REG_MOVE
:
268 values
[0] = SEXT5 (OP
[0]);
273 values
[0] = State
.pc
;
274 values
[1] = SEXT9 (OP
[0]);
275 values
[2] = State
.sregs
[5];
280 values
[0] = OP
[1] * size
;
281 values
[1] = State
.regs
[30];
286 values
[0] = State
.regs
[OP
[0]];
287 values
[1] = OP
[1] * size
;
288 values
[2] = State
.regs
[30];
293 values
[0] = SEXT16 (OP
[2]);
294 values
[1] = State
.regs
[OP
[0]];
299 values
[0] = State
.regs
[OP
[1]];
300 values
[1] = SEXT16 (OP
[2]);
301 values
[2] = State
.regs
[OP
[0]];
306 values
[0] = SEXT22 (OP
[0]);
307 values
[1] = State
.pc
;
312 values
[0] = SEXT16 (OP
[0]) << size
;
313 values
[1] = State
.regs
[OP
[1]];
317 case OP_UIMM_REG_REG
:
318 values
[0] = (OP
[0] & 0xffff) << size
;
319 values
[1] = State
.regs
[OP
[1]];
328 values
[0] = State
.sregs
[5];
337 values
[0] = State
.regs
[OP
[0]];
342 values
[0] = State
.sregs
[OP
[1]];
346 for (i
= 0; i
< num_values
; i
++)
347 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s0x%.8lx", SIZE_VALUES
- 10, "", values
[i
]);
350 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s", SIZE_VALUES
, "");
355 trace_output (result
)
356 enum op_types result
;
358 if ((v850_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
378 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
379 (unsigned long)State
.regs
[OP
[0]]);
383 case OP_REG_REG_MOVE
:
385 case OP_IMM_REG_MOVE
:
388 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
389 (unsigned long)State
.regs
[OP
[1]]);
393 case OP_UIMM_REG_REG
:
394 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
395 (unsigned long)State
.regs
[OP
[2]]);
400 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
401 (unsigned long)State
.regs
[OP
[1]]);
405 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
406 (unsigned long)State
.sregs
[OP
[1]]);
410 (*v850_callback
->printf_filtered
) (v850_callback
, "\n");
415 #define trace_input(NAME, IN1, IN2)
416 #define trace_output(RESULT)
427 trace_input ("sld.b", OP_LOAD16
, 1);
431 result
= load_mem (State
.regs
[30] + op2
, 1);
432 State
.regs
[OP
[0]] = SEXT8 (result
);
433 trace_output (OP_LOAD16
);
443 trace_input ("sld.h", OP_LOAD16
, 2);
447 result
= load_mem (State
.regs
[30] + op2
, 2);
448 State
.regs
[OP
[0]] = SEXT16 (result
);
449 trace_output (OP_LOAD16
);
459 trace_input ("sld.w", OP_LOAD16
, 4);
463 result
= load_mem (State
.regs
[30] + op2
, 4);
464 State
.regs
[OP
[0]] = result
;
465 trace_output (OP_LOAD16
);
472 unsigned int op0
, op1
;
475 trace_input ("sst.b", OP_STORE16
, 1);
476 op0
= State
.regs
[OP
[0]];
480 store_mem (State
.regs
[30] + op1
, 1, op0
);
481 trace_output (OP_STORE16
);
488 unsigned int op0
, op1
;
491 trace_input ("sst.h", OP_STORE16
, 2);
492 op0
= State
.regs
[OP
[0]];
496 store_mem (State
.regs
[30] + op1
, 2, op0
);
497 trace_output (OP_STORE16
);
504 unsigned int op0
, op1
;
507 trace_input ("sst.w", OP_STORE16
, 4);
508 op0
= State
.regs
[OP
[0]];
512 store_mem (State
.regs
[30] + op1
, 4, op0
);
513 trace_output (OP_STORE16
);
520 unsigned int op0
, op2
;
523 trace_input ("ld.b", OP_LOAD32
, 1);
524 op0
= State
.regs
[OP
[0]];
525 temp
= SEXT16 (OP
[2]);
527 result
= load_mem (op0
+ op2
, 1);
528 State
.regs
[OP
[1]] = SEXT8 (result
);
529 trace_output (OP_LOAD32
);
536 unsigned int op0
, op2
;
539 trace_input ("ld.h", OP_LOAD32
, 2);
540 op0
= State
.regs
[OP
[0]];
541 temp
= SEXT16 (OP
[2]);
544 result
= load_mem (op0
+ op2
, 2);
545 State
.regs
[OP
[1]] = SEXT16 (result
);
546 trace_output (OP_LOAD32
);
553 unsigned int op0
, op2
;
556 trace_input ("ld.w", OP_LOAD32
, 4);
557 op0
= State
.regs
[OP
[0]];
558 temp
= SEXT16 (OP
[2]);
561 result
= load_mem (op0
+ op2
, 4);
562 State
.regs
[OP
[1]] = result
;
563 trace_output (OP_LOAD32
);
570 unsigned int op0
, op1
, op2
;
573 trace_input ("st.b", OP_STORE32
, 1);
574 op0
= State
.regs
[OP
[0]];
575 op1
= State
.regs
[OP
[1]];
576 temp
= SEXT16 (OP
[2]);
578 store_mem (op0
+ op2
, 1, op1
);
579 trace_output (OP_STORE32
);
586 unsigned int op0
, op1
, op2
;
589 trace_input ("st.h", OP_STORE32
, 2);
590 op0
= State
.regs
[OP
[0]];
591 op1
= State
.regs
[OP
[1]];
592 temp
= SEXT16 (OP
[2] & ~0x1);
594 store_mem (op0
+ op2
, 2, op1
);
595 trace_output (OP_STORE32
);
602 unsigned int op0
, op1
, op2
;
605 trace_input ("st.w", OP_STORE32
, 4);
606 op0
= State
.regs
[OP
[0]];
607 op1
= State
.regs
[OP
[1]];
608 temp
= SEXT16 (OP
[2] & ~0x1);
610 store_mem (op0
+ op2
, 4, op1
);
611 trace_output (OP_STORE32
);
621 trace_input ("bv", OP_COND_BR
, 0);
623 psw
= State
.sregs
[5];
625 if ((psw
& PSW_OV
) != 0)
629 trace_output (OP_COND_BR
);
639 trace_input ("bl", OP_COND_BR
, 0);
641 psw
= State
.sregs
[5];
643 if ((psw
& PSW_CY
) != 0)
647 trace_output (OP_COND_BR
);
657 trace_input ("be", OP_COND_BR
, 0);
659 psw
= State
.sregs
[5];
661 if ((psw
& PSW_Z
) != 0)
665 trace_output (OP_COND_BR
);
675 trace_input ("bnh", OP_COND_BR
, 0);
677 psw
= State
.sregs
[5];
679 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0)
683 trace_output (OP_COND_BR
);
693 trace_input ("bn", OP_COND_BR
, 0);
695 psw
= State
.sregs
[5];
697 if ((psw
& PSW_S
) != 0)
701 trace_output (OP_COND_BR
);
711 trace_input ("br", OP_COND_BR
, 0);
714 trace_output (OP_COND_BR
);
724 trace_input ("blt", OP_COND_BR
, 0);
726 psw
= State
.sregs
[5];
728 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0)
732 trace_output (OP_COND_BR
);
742 trace_input ("ble", OP_COND_BR
, 0);
744 psw
= State
.sregs
[5];
746 if ((((psw
& PSW_Z
) != 0)
747 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) != 0)
751 trace_output (OP_COND_BR
);
761 trace_input ("bnv", OP_COND_BR
, 0);
763 psw
= State
.sregs
[5];
765 if ((psw
& PSW_OV
) == 0)
769 trace_output (OP_COND_BR
);
779 trace_input ("bnl", OP_COND_BR
, 0);
781 psw
= State
.sregs
[5];
783 if ((psw
& PSW_CY
) == 0)
787 trace_output (OP_COND_BR
);
797 trace_input ("bne", OP_COND_BR
, 0);
799 psw
= State
.sregs
[5];
801 if ((psw
& PSW_Z
) == 0)
805 trace_output (OP_COND_BR
);
815 trace_input ("bh", OP_COND_BR
, 0);
817 psw
= State
.sregs
[5];
819 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0)
823 trace_output (OP_COND_BR
);
833 trace_input ("bp", OP_COND_BR
, 0);
835 psw
= State
.sregs
[5];
837 if ((psw
& PSW_S
) == 0)
841 trace_output (OP_COND_BR
);
851 trace_input ("bsa", OP_COND_BR
, 0);
853 psw
= State
.sregs
[5];
855 if ((psw
& PSW_SAT
) != 0)
859 trace_output (OP_COND_BR
);
869 trace_input ("bge", OP_COND_BR
, 0);
871 psw
= State
.sregs
[5];
873 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0)
877 trace_output (OP_COND_BR
);
887 trace_input ("bgt", OP_COND_BR
, 0);
889 psw
= State
.sregs
[5];
891 if ((((psw
& PSW_Z
) != 0)
892 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) == 0)
896 trace_output (OP_COND_BR
);
903 /* interp.c will bump this by +2, so correct for it here. */
904 trace_input ("jmp", OP_REG
, 0);
905 State
.pc
= State
.regs
[OP
[0]] - 2;
906 trace_output (OP_REG
);
909 /* jarl disp22, reg */
913 unsigned int op0
, opc
;
916 trace_input ("jarl", OP_JUMP
, 0);
917 temp
= SEXT22 (OP
[0]);
923 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
925 State
.regs
[OP
[1]] = opc
+ 4;
926 trace_output (OP_JUMP
);
933 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
935 trace_input ("add", OP_REG_REG
, 0);
936 /* Compute the result. */
937 op0
= State
.regs
[OP
[0]];
938 op1
= State
.regs
[OP
[1]];
941 /* Compute the condition codes. */
943 s
= (result
& 0x80000000);
944 cy
= (result
< op0
|| result
< op1
);
945 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
946 && (op0
& 0x80000000) != (result
& 0x80000000));
948 /* Store the result and condition codes. */
949 State
.regs
[OP
[1]] = result
;
950 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
951 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
952 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
953 trace_output (OP_REG_REG
);
956 /* add sign_extend(imm5), reg */
960 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
963 trace_input ("add", OP_IMM_REG
, 0);
965 /* Compute the result. */
966 temp
= SEXT5 (OP
[0]);
968 op1
= State
.regs
[OP
[1]];
971 /* Compute the condition codes. */
973 s
= (result
& 0x80000000);
974 cy
= (result
< op0
|| result
< op1
);
975 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
976 && (op0
& 0x80000000) != (result
& 0x80000000));
978 /* Store the result and condition codes. */
979 State
.regs
[OP
[1]] = result
;
980 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
981 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
982 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
983 trace_output (OP_IMM_REG
);
986 /* addi sign_extend(imm16), reg, reg */
990 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
993 trace_input ("addi", OP_IMM_REG_REG
, 0);
995 /* Compute the result. */
996 temp
= SEXT16 (OP
[0]);
998 op1
= State
.regs
[OP
[1]];
1001 /* Compute the condition codes. */
1003 s
= (result
& 0x80000000);
1004 cy
= (result
< op0
|| result
< op1
);
1005 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1006 && (op0
& 0x80000000) != (result
& 0x80000000));
1008 /* Store the result and condition codes. */
1009 State
.regs
[OP
[2]] = result
;
1010 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1011 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1012 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1013 trace_output (OP_IMM_REG_REG
);
1016 /* sub reg1, reg2 */
1020 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1022 trace_input ("sub", OP_REG_REG
, 0);
1023 /* Compute the result. */
1024 op0
= State
.regs
[OP
[0]];
1025 op1
= State
.regs
[OP
[1]];
1028 /* Compute the condition codes. */
1030 s
= (result
& 0x80000000);
1032 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1033 && (op1
& 0x80000000) != (result
& 0x80000000));
1035 /* Store the result and condition codes. */
1036 State
.regs
[OP
[1]] = result
;
1037 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1038 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1039 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1040 trace_output (OP_REG_REG
);
1043 /* subr reg1, reg2 */
1047 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1049 trace_input ("subr", OP_REG_REG
, 0);
1050 /* Compute the result. */
1051 op0
= State
.regs
[OP
[0]];
1052 op1
= State
.regs
[OP
[1]];
1055 /* Compute the condition codes. */
1057 s
= (result
& 0x80000000);
1059 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1060 && (op0
& 0x80000000) != (result
& 0x80000000));
1062 /* Store the result and condition codes. */
1063 State
.regs
[OP
[1]] = result
;
1064 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1065 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1066 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1067 trace_output (OP_REG_REG
);
1070 /* mulh reg1, reg2 */
1074 trace_input ("mulh", OP_REG_REG
, 0);
1075 State
.regs
[OP
[1]] = ((State
.regs
[OP
[1]] & 0xffff)
1076 * (State
.regs
[OP
[0]] & 0xffff));
1077 trace_output (OP_REG_REG
);
1080 /* mulh sign_extend(imm5), reg2
1086 int value
= SEXT5 (OP
[0]);
1088 trace_input ("mulh", OP_IMM_REG
, 0);
1089 State
.regs
[OP
[1]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1090 trace_output (OP_IMM_REG
);
1093 /* mulhi imm16, reg1, reg2 */
1097 int value
= OP
[0] & 0xffff;
1099 trace_input ("mulhi", OP_IMM_REG_REG
, 0);
1100 State
.regs
[OP
[2]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1101 trace_output (OP_IMM_REG_REG
);
1104 /* divh reg1, reg2 */
1108 unsigned int op0
, op1
, result
, ov
, s
, z
;
1111 trace_input ("divh", OP_REG_REG
, 0);
1113 /* Compute the result. */
1114 temp
= SEXT16 (State
.regs
[OP
[0]]);
1116 op1
= State
.regs
[OP
[1]];
1118 if (op0
== 0xffffffff && op1
== 0x80000000)
1120 result
= 0x80000000;
1134 /* Compute the condition codes. */
1136 s
= (result
& 0x80000000);
1138 /* Store the result and condition codes. */
1139 State
.regs
[OP
[1]] = result
;
1140 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1141 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1142 | (ov
? PSW_OV
: 0));
1143 trace_output (OP_REG_REG
);
1150 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1152 trace_input ("cmp", OP_REG_REG_CMP
, 0);
1153 /* Compute the result. */
1154 op0
= State
.regs
[OP
[0]];
1155 op1
= State
.regs
[OP
[1]];
1158 /* Compute the condition codes. */
1160 s
= (result
& 0x80000000);
1162 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1163 && (op1
& 0x80000000) != (result
& 0x80000000));
1165 /* Set condition codes. */
1166 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1167 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1168 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1169 trace_output (OP_REG_REG_CMP
);
1172 /* cmp sign_extend(imm5), reg */
1176 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1179 /* Compute the result. */
1180 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
1181 temp
= SEXT5 (OP
[0]);
1183 op1
= State
.regs
[OP
[1]];
1186 /* Compute the condition codes. */
1188 s
= (result
& 0x80000000);
1190 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1191 && (op1
& 0x80000000) != (result
& 0x80000000));
1193 /* Set condition codes. */
1194 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1195 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1196 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1197 trace_output (OP_IMM_REG_CMP
);
1200 /* setf cccc,reg2 */
1204 /* Hack alert. We turn off a bit in op0 since we really only
1206 unsigned int op0
, psw
, result
= 0;
1208 trace_input ("setf", OP_EX1
, 0);
1210 psw
= State
.sregs
[5];
1215 result
= ((psw
& PSW_OV
) != 0);
1218 result
= ((psw
& PSW_CY
) != 0);
1221 result
= ((psw
& PSW_Z
) != 0);
1224 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
1227 result
= ((psw
& PSW_S
) != 0);
1233 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
1236 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1237 || ((psw
& PSW_Z
) != 0)) != 0);
1240 result
= ((psw
& PSW_OV
) == 0);
1243 result
= ((psw
& PSW_CY
) == 0);
1246 result
= ((psw
& PSW_Z
) == 0);
1249 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
1252 result
= ((psw
& PSW_S
) == 0);
1255 result
= ((psw
& PSW_SAT
) != 0);
1258 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
1261 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1262 || ((psw
& PSW_Z
) != 0)) == 0);
1266 State
.regs
[OP
[1]] = result
;
1267 trace_output (OP_EX1
);
1270 /* satadd reg,reg */
1274 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1276 trace_input ("satadd", OP_REG_REG
, 0);
1277 /* Compute the result. */
1278 op0
= State
.regs
[OP
[0]];
1279 op1
= State
.regs
[OP
[1]];
1282 /* Compute the condition codes. */
1284 s
= (result
& 0x80000000);
1285 cy
= (result
< op0
|| result
< op1
);
1286 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1287 && (op0
& 0x80000000) != (result
& 0x80000000));
1290 /* Store the result and condition codes. */
1291 State
.regs
[OP
[1]] = result
;
1292 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1293 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1294 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1295 | (sat
? PSW_SAT
: 0));
1297 /* Handle saturated results. */
1299 State
.regs
[OP
[1]] = 0x80000000;
1301 State
.regs
[OP
[1]] = 0x7fffffff;
1302 trace_output (OP_REG_REG
);
1305 /* satadd sign_extend(imm5), reg */
1309 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1313 trace_input ("satadd", OP_IMM_REG
, 0);
1315 /* Compute the result. */
1316 temp
= SEXT5 (OP
[0]);
1318 op1
= State
.regs
[OP
[1]];
1321 /* Compute the condition codes. */
1323 s
= (result
& 0x80000000);
1324 cy
= (result
< op0
|| result
< op1
);
1325 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1326 && (op0
& 0x80000000) != (result
& 0x80000000));
1329 /* Store the result and condition codes. */
1330 State
.regs
[OP
[1]] = result
;
1331 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1332 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1333 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1334 | (sat
? PSW_SAT
: 0));
1336 /* Handle saturated results. */
1338 State
.regs
[OP
[1]] = 0x80000000;
1340 State
.regs
[OP
[1]] = 0x7fffffff;
1341 trace_output (OP_IMM_REG
);
1344 /* satsub reg1, reg2 */
1348 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1350 trace_input ("satsub", OP_REG_REG
, 0);
1352 /* Compute the result. */
1353 op0
= State
.regs
[OP
[0]];
1354 op1
= State
.regs
[OP
[1]];
1357 /* Compute the condition codes. */
1359 s
= (result
& 0x80000000);
1361 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1362 && (op1
& 0x80000000) != (result
& 0x80000000));
1365 /* Store the result and condition codes. */
1366 State
.regs
[OP
[1]] = result
;
1367 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1368 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1369 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1370 | (sat
? PSW_SAT
: 0));
1372 /* Handle saturated results. */
1374 State
.regs
[OP
[1]] = 0x80000000;
1376 State
.regs
[OP
[1]] = 0x7fffffff;
1377 trace_output (OP_REG_REG
);
1380 /* satsubi sign_extend(imm16), reg */
1384 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1387 trace_input ("satsubi", OP_IMM_REG
, 0);
1389 /* Compute the result. */
1390 temp
= SEXT16 (OP
[0]);
1392 op1
= State
.regs
[OP
[1]];
1395 /* Compute the condition codes. */
1397 s
= (result
& 0x80000000);
1399 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1400 && (op1
& 0x80000000) != (result
& 0x80000000));
1403 /* Store the result and condition codes. */
1404 State
.regs
[OP
[1]] = result
;
1405 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1406 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1407 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1408 | (sat
? PSW_SAT
: 0));
1410 /* Handle saturated results. */
1412 State
.regs
[OP
[1]] = 0x80000000;
1414 State
.regs
[OP
[1]] = 0x7fffffff;
1415 trace_output (OP_IMM_REG
);
1418 /* satsubr reg,reg */
1422 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1424 trace_input ("satsubr", OP_REG_REG
, 0);
1426 /* Compute the result. */
1427 op0
= State
.regs
[OP
[0]];
1428 op1
= State
.regs
[OP
[1]];
1431 /* Compute the condition codes. */
1433 s
= (result
& 0x80000000);
1434 cy
= (result
< op0
);
1435 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1436 && (op1
& 0x80000000) != (result
& 0x80000000));
1439 /* Store the result and condition codes. */
1440 State
.regs
[OP
[1]] = result
;
1441 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1442 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1443 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1444 | (sat
? PSW_SAT
: 0));
1446 /* Handle saturated results. */
1448 State
.regs
[OP
[1]] = 0x80000000;
1450 State
.regs
[OP
[1]] = 0x7fffffff;
1451 trace_output (OP_REG_REG
);
1458 unsigned int op0
, op1
, result
, z
, s
;
1460 trace_input ("tst", OP_REG_REG_CMP
, 0);
1462 /* Compute the result. */
1463 op0
= State
.regs
[OP
[0]];
1464 op1
= State
.regs
[OP
[1]];
1467 /* Compute the condition codes. */
1469 s
= (result
& 0x80000000);
1471 /* Store the condition codes. */
1472 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1473 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1474 trace_output (OP_REG_REG_CMP
);
1481 trace_input ("mov", OP_REG_REG_MOVE
, 0);
1482 State
.regs
[OP
[1]] = State
.regs
[OP
[0]];
1483 trace_output (OP_REG_REG_MOVE
);
1486 /* mov sign_extend(imm5), reg */
1490 int value
= SEXT5 (OP
[0]);
1492 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1493 State
.regs
[OP
[1]] = value
;
1494 trace_output (OP_IMM_REG_MOVE
);
1497 /* movea sign_extend(imm16), reg, reg */
1502 int value
= SEXT16 (OP
[0]);
1504 trace_input ("movea", OP_IMM_REG_REG
, 0);
1505 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1506 trace_output (OP_IMM_REG_REG
);
1509 /* movhi imm16, reg, reg */
1513 uint32 value
= (OP
[0] & 0xffff) << 16;
1515 trace_input ("movhi", OP_UIMM_REG_REG
, 16);
1516 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1517 trace_output (OP_UIMM_REG_REG
);
1520 /* sar zero_extend(imm5),reg1 */
1524 unsigned int op0
, op1
, result
, z
, s
, cy
;
1526 trace_input ("sar", OP_IMM_REG
, 0);
1528 op1
= State
.regs
[OP
[1]];
1529 result
= (signed)op1
>> op0
;
1531 /* Compute the condition codes. */
1533 s
= (result
& 0x80000000);
1534 cy
= (op1
& (1 << (op0
- 1)));
1536 /* Store the result and condition codes. */
1537 State
.regs
[OP
[1]] = result
;
1538 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1539 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1540 | (cy
? PSW_CY
: 0));
1541 trace_output (OP_IMM_REG
);
1544 /* sar reg1, reg2 */
1548 unsigned int op0
, op1
, result
, z
, s
, cy
;
1550 trace_input ("sar", OP_REG_REG
, 0);
1551 op0
= State
.regs
[OP
[0]] & 0x1f;
1552 op1
= State
.regs
[OP
[1]];
1553 result
= (signed)op1
>> op0
;
1555 /* Compute the condition codes. */
1557 s
= (result
& 0x80000000);
1558 cy
= (op1
& (1 << (op0
- 1)));
1560 /* Store the result and condition codes. */
1561 State
.regs
[OP
[1]] = result
;
1562 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1563 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1564 | (cy
? PSW_CY
: 0));
1565 trace_output (OP_REG_REG
);
1568 /* shl zero_extend(imm5),reg1 */
1572 unsigned int op0
, op1
, result
, z
, s
, cy
;
1574 trace_input ("shl", OP_IMM_REG
, 0);
1576 op1
= State
.regs
[OP
[1]];
1577 result
= op1
<< op0
;
1579 /* Compute the condition codes. */
1581 s
= (result
& 0x80000000);
1582 cy
= (op1
& (1 << (32 - op0
)));
1584 /* Store the result and condition codes. */
1585 State
.regs
[OP
[1]] = result
;
1586 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1587 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1588 | (cy
? PSW_CY
: 0));
1589 trace_output (OP_IMM_REG
);
1592 /* shl reg1, reg2 */
1596 unsigned int op0
, op1
, result
, z
, s
, cy
;
1598 trace_input ("shl", OP_REG_REG
, 0);
1599 op0
= State
.regs
[OP
[0]] & 0x1f;
1600 op1
= State
.regs
[OP
[1]];
1601 result
= op1
<< op0
;
1603 /* Compute the condition codes. */
1605 s
= (result
& 0x80000000);
1606 cy
= (op1
& (1 << (32 - op0
)));
1608 /* Store the result and condition codes. */
1609 State
.regs
[OP
[1]] = result
;
1610 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1611 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1612 | (cy
? PSW_CY
: 0));
1613 trace_output (OP_REG_REG
);
1616 /* shr zero_extend(imm5),reg1 */
1620 unsigned int op0
, op1
, result
, z
, s
, cy
;
1622 trace_input ("shr", OP_IMM_REG
, 0);
1624 op1
= State
.regs
[OP
[1]];
1625 result
= op1
>> op0
;
1627 /* Compute the condition codes. */
1629 s
= (result
& 0x80000000);
1630 cy
= (op1
& (1 << (op0
- 1)));
1632 /* Store the result and condition codes. */
1633 State
.regs
[OP
[1]] = result
;
1634 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1635 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1636 | (cy
? PSW_CY
: 0));
1637 trace_output (OP_IMM_REG
);
1640 /* shr reg1, reg2 */
1644 unsigned int op0
, op1
, result
, z
, s
, cy
;
1646 trace_input ("shr", OP_REG_REG
, 0);
1647 op0
= State
.regs
[OP
[0]] & 0x1f;
1648 op1
= State
.regs
[OP
[1]];
1649 result
= op1
>> op0
;
1651 /* Compute the condition codes. */
1653 s
= (result
& 0x80000000);
1654 cy
= (op1
& (1 << (op0
- 1)));
1656 /* Store the result and condition codes. */
1657 State
.regs
[OP
[1]] = result
;
1658 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1659 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1660 | (cy
? PSW_CY
: 0));
1661 trace_output (OP_REG_REG
);
1668 unsigned int op0
, op1
, result
, z
, s
;
1670 trace_input ("or", OP_REG_REG
, 0);
1672 /* Compute the result. */
1673 op0
= State
.regs
[OP
[0]];
1674 op1
= State
.regs
[OP
[1]];
1677 /* Compute the condition codes. */
1679 s
= (result
& 0x80000000);
1681 /* Store the result and condition codes. */
1682 State
.regs
[OP
[1]] = result
;
1683 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1684 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1685 trace_output (OP_REG_REG
);
1688 /* ori zero_extend(imm16), reg, reg */
1692 unsigned int op0
, op1
, result
, z
, s
;
1694 trace_input ("ori", OP_UIMM_REG_REG
, 0);
1695 op0
= OP
[0] & 0xffff;
1696 op1
= State
.regs
[OP
[1]];
1699 /* Compute the condition codes. */
1701 s
= (result
& 0x80000000);
1703 /* Store the result and condition codes. */
1704 State
.regs
[OP
[2]] = result
;
1705 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1706 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1707 trace_output (OP_UIMM_REG_REG
);
1714 unsigned int op0
, op1
, result
, z
, s
;
1716 trace_input ("and", OP_REG_REG
, 0);
1718 /* Compute the result. */
1719 op0
= State
.regs
[OP
[0]];
1720 op1
= State
.regs
[OP
[1]];
1723 /* Compute the condition codes. */
1725 s
= (result
& 0x80000000);
1727 /* Store the result and condition codes. */
1728 State
.regs
[OP
[1]] = result
;
1729 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1730 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1731 trace_output (OP_REG_REG
);
1734 /* andi zero_extend(imm16), reg, reg */
1738 unsigned int op0
, op1
, result
, z
;
1740 trace_input ("andi", OP_UIMM_REG_REG
, 0);
1741 op0
= OP
[0] & 0xffff;
1742 op1
= State
.regs
[OP
[1]];
1745 /* Compute the condition codes. */
1748 /* Store the result and condition codes. */
1749 State
.regs
[OP
[2]] = result
;
1750 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1751 State
.sregs
[5] |= (z
? PSW_Z
: 0);
1752 trace_output (OP_UIMM_REG_REG
);
1759 unsigned int op0
, op1
, result
, z
, s
;
1761 trace_input ("xor", OP_REG_REG
, 0);
1763 /* Compute the result. */
1764 op0
= State
.regs
[OP
[0]];
1765 op1
= State
.regs
[OP
[1]];
1768 /* Compute the condition codes. */
1770 s
= (result
& 0x80000000);
1772 /* Store the result and condition codes. */
1773 State
.regs
[OP
[1]] = result
;
1774 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1775 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1776 trace_output (OP_REG_REG
);
1779 /* xori zero_extend(imm16), reg, reg */
1783 unsigned int op0
, op1
, result
, z
, s
;
1785 trace_input ("xori", OP_UIMM_REG_REG
, 0);
1786 op0
= OP
[0] & 0xffff;
1787 op1
= State
.regs
[OP
[1]];
1790 /* Compute the condition codes. */
1792 s
= (result
& 0x80000000);
1794 /* Store the result and condition codes. */
1795 State
.regs
[OP
[2]] = result
;
1796 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1797 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1798 trace_output (OP_UIMM_REG_REG
);
1801 /* not reg1, reg2 */
1805 unsigned int op0
, result
, z
, s
;
1807 trace_input ("not", OP_REG_REG_MOVE
, 0);
1808 /* Compute the result. */
1809 op0
= State
.regs
[OP
[0]];
1812 /* Compute the condition codes. */
1814 s
= (result
& 0x80000000);
1816 /* Store the result and condition codes. */
1817 State
.regs
[OP
[1]] = result
;
1818 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1819 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1820 trace_output (OP_REG_REG_MOVE
);
1827 unsigned int op0
, op1
, op2
;
1830 trace_input ("set1", OP_BIT
, 0);
1831 op0
= State
.regs
[OP
[0]];
1833 temp
= SEXT16 (OP
[2]);
1835 temp
= load_mem (op0
+ op2
, 1);
1836 State
.sregs
[5] &= ~PSW_Z
;
1837 if ((temp
& (1 << op1
)) == 0)
1838 State
.sregs
[5] |= PSW_Z
;
1840 store_mem (op0
+ op2
, 1, temp
);
1841 trace_output (OP_BIT
);
1848 unsigned int op0
, op1
, op2
;
1851 trace_input ("not1", OP_BIT
, 0);
1852 op0
= State
.regs
[OP
[0]];
1854 temp
= SEXT16 (OP
[2]);
1856 temp
= load_mem (op0
+ op2
, 1);
1857 State
.sregs
[5] &= ~PSW_Z
;
1858 if ((temp
& (1 << op1
)) == 0)
1859 State
.sregs
[5] |= PSW_Z
;
1861 store_mem (op0
+ op2
, 1, temp
);
1862 trace_output (OP_BIT
);
1869 unsigned int op0
, op1
, op2
;
1872 trace_input ("clr1", OP_BIT
, 0);
1873 op0
= State
.regs
[OP
[0]];
1875 temp
= SEXT16 (OP
[2]);
1877 temp
= load_mem (op0
+ op2
, 1);
1878 State
.sregs
[5] &= ~PSW_Z
;
1879 if ((temp
& (1 << op1
)) == 0)
1880 State
.sregs
[5] |= PSW_Z
;
1881 temp
&= ~(1 << op1
);
1882 store_mem (op0
+ op2
, 1, temp
);
1883 trace_output (OP_BIT
);
1890 unsigned int op0
, op1
, op2
;
1893 trace_input ("tst1", OP_BIT
, 0);
1894 op0
= State
.regs
[OP
[0]];
1896 temp
= SEXT16 (OP
[2]);
1898 temp
= load_mem (op0
+ op2
, 1);
1899 State
.sregs
[5] &= ~PSW_Z
;
1900 if ((temp
& (1 << op1
)) == 0)
1901 State
.sregs
[5] |= PSW_Z
;
1902 trace_output (OP_BIT
);
1909 State
.exception
= SIGTRAP
;
1917 trace_input ("di", OP_NONE
, 0);
1918 State
.sregs
[5] |= PSW_ID
;
1919 trace_output (OP_NONE
);
1926 trace_input ("ei", OP_NONE
, 0);
1927 State
.sregs
[5] &= ~PSW_ID
;
1928 trace_output (OP_NONE
);
1931 /* halt, not supported */
1935 trace_input ("halt", OP_NONE
, 0);
1936 State
.exception
= SIGQUIT
;
1937 trace_output (OP_NONE
);
1940 /* reti, not supported */
1944 trace_input ("reti", OP_NONE
, 0);
1945 trace_output (OP_NONE
);
1947 if ((State
.sregs
[5] & (PSW_NP
| PSW_EP
)) == PSW_NP
)
1948 { /* Only NP is on */
1949 PC
= State
.sregs
[2] - 4; /* FEPC */
1950 State
.sregs
[5] = State
.sregs
[3]; /* FEPSW */
1954 PC
= State
.sregs
[0] - 4; /* EIPC */
1955 State
.sregs
[5] = State
.sregs
[1]; /* EIPSW */
1959 /* trap, not supportd */
1963 trace_input ("trap", OP_TRAP
, 0);
1964 trace_output (OP_TRAP
);
1966 /* Trap 31 is used for simulating OS I/O functions */
1970 int save_errno
= errno
;
1973 /* Registers passed to trap 0 */
1975 #define FUNC State.regs[6] /* function number, return value */
1976 #define PARM1 State.regs[7] /* optional parm 1 */
1977 #define PARM2 State.regs[8] /* optional parm 2 */
1978 #define PARM3 State.regs[9] /* optional parm 3 */
1980 /* Registers set by trap 0 */
1982 #define RETVAL State.regs[10] /* return value */
1983 #define RETERR State.regs[11] /* return error code */
1985 /* Turn a pointer in a register into a pointer into real memory. */
1987 #define MEMPTR(x) (map (x))
1991 #if !defined(__GO32__) && !defined(_WIN32)
1996 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
1997 (char **)MEMPTR (PARM3
));
2000 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2009 RETVAL
= pipe (host_fd
);
2010 SW (buf
, host_fd
[0]);
2011 buf
+= sizeof(uint16
);
2012 SW (buf
, host_fd
[1]);
2020 RETVAL
= wait (&status
);
2028 RETVAL
= v850_callback
->read (v850_callback
, PARM1
, MEMPTR (PARM2
),
2033 RETVAL
= (int)v850_callback
->write_stdout (v850_callback
,
2034 MEMPTR (PARM2
), PARM3
);
2036 RETVAL
= (int)v850_callback
->write (v850_callback
, PARM1
,
2037 MEMPTR (PARM2
), PARM3
);
2040 RETVAL
= v850_callback
->lseek (v850_callback
, PARM1
, PARM2
, PARM3
);
2043 RETVAL
= v850_callback
->close (v850_callback
, PARM1
);
2046 RETVAL
= v850_callback
->open (v850_callback
, MEMPTR (PARM1
), PARM2
);
2049 /* EXIT - caller can look in PARM1 to work out the
2051 if (PARM1
== 0xdead || PARM1
== 0x1)
2052 State
.exception
= SIGABRT
;
2054 State
.exception
= SIGQUIT
;
2057 case SYS_stat
: /* added at hmsi */
2058 /* stat system call */
2060 struct stat host_stat
;
2063 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2067 /* Just wild-assed guesses. */
2068 store_mem (buf
, 2, host_stat
.st_dev
);
2069 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2070 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2071 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2072 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2073 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2074 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2075 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2076 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2077 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2078 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2083 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2086 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2089 RETVAL
= time (MEMPTR (PARM1
));
2094 RETVAL
= times (&tms
);
2095 store_mem (PARM1
, 4, tms
.tms_utime
);
2096 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
2097 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
2098 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
2101 case SYS_gettimeofday
:
2105 RETVAL
= gettimeofday (&t
, &tz
);
2106 store_mem (PARM1
, 4, t
.tv_sec
);
2107 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
2108 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
2109 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
2113 /* Cast the second argument to void *, to avoid type mismatch
2114 if a prototype is present. */
2115 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2124 { /* Trap 0 -> 30 */
2125 State
.sregs
[0] = PC
+ 4; /* EIPC */
2126 State
.sregs
[1] = State
.sregs
[5]; /* EIPSW */
2127 State
.sregs
[4] &= 0xffff0000; /* Mask out EICC */
2128 State
.sregs
[4] |= 0x40 + OP
[0]; /* EICC */
2129 State
.sregs
[5] |= PSW_EP
| PSW_ID
; /* Now doing exception processing */
2130 PC
= ((OP
[0] < 0x10) ? 0x40 : 0x50) - 4;
2140 trace_input ("ldsr", OP_LDSR
, 0);
2141 op0
= State
.regs
[OP
[0]];
2142 State
.sregs
[OP
[1]] = op0
;
2143 trace_output (OP_LDSR
);
2146 /* stsr, not supported */
2152 trace_input ("stsr", OP_STSR
, 0);
2153 op0
= State
.sregs
[OP
[1]];
2154 State
.regs
[OP
[0]] = op0
;
2155 trace_output (OP_STSR
);