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[binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "v850_sim.h"
3 #include "simops.h"
4 #include "sys/syscall.h"
5 #include "bfd.h"
6 #include <errno.h>
7 #if !defined(__GO32__) && !defined(_WIN32)
8 #include <sys/stat.h>
9 #include <sys/times.h>
10 #include <sys/time.h>
11 #endif
12
13 enum op_types
14 {
15 OP_UNKNOWN,
16 OP_NONE,
17 OP_TRAP,
18 OP_REG,
19 OP_REG_REG,
20 OP_REG_REG_CMP,
21 OP_REG_REG_MOVE,
22 OP_IMM_REG,
23 OP_IMM_REG_CMP,
24 OP_IMM_REG_MOVE,
25 OP_COND_BR,
26 OP_LOAD16,
27 OP_STORE16,
28 OP_LOAD32,
29 OP_STORE32,
30 OP_JUMP,
31 OP_IMM_REG_REG,
32 OP_UIMM_REG_REG,
33 OP_BIT,
34 OP_EX1,
35 OP_EX2,
36 OP_LDSR,
37 OP_STSR,
38 /* start-sanitize-v850e */
39 OP_BIT_CHANGE,
40 OP_REG_REG_REG,
41 OP_REG_REG3,
42 /* end-sanitize-v850e */
43 /* start-sanitize-v850eq */
44 OP_IMM_REG_REG_REG,
45 OP_PUSHPOP1,
46 OP_PUSHPOP2,
47 OP_PUSHPOP3,
48 /* end-sanitize-v850eq */
49 };
50
51 /* start-sanitize-v850e */
52 /* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
53 static int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
54 /* end-sanitize-v850e */
55 /* start-sanitize-v850eq */
56 /* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
57 static int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
58 /* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
59 static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
60 /* end-sanitize-v850eq */
61
62 #ifdef DEBUG
63 static void trace_input PARAMS ((char *name, enum op_types type, int size));
64 static void trace_output PARAMS ((enum op_types result));
65 static int init_text_p = 0;
66 static asection *text;
67 static bfd_vma text_start;
68 static bfd_vma text_end;
69 extern bfd *prog_bfd;
70
71 #ifndef SIZE_INSTRUCTION
72 #define SIZE_INSTRUCTION 6
73 #endif
74
75 #ifndef SIZE_OPERANDS
76 #define SIZE_OPERANDS 16
77 #endif
78
79 #ifndef SIZE_VALUES
80 #define SIZE_VALUES 11
81 #endif
82
83 #ifndef SIZE_LOCATION
84 #define SIZE_LOCATION 40
85 #endif
86
87
88 static void
89 trace_input (name, type, size)
90 char *name;
91 enum op_types type;
92 int size;
93 {
94 char buf[1024];
95 char *p;
96 uint32 values[3];
97 int num_values, i;
98 char *cond;
99 asection *s;
100 const char *filename;
101 const char *functionname;
102 unsigned int linenumber;
103
104 if ((v850_debug & DEBUG_TRACE) == 0)
105 return;
106
107 buf[0] = '\0';
108 if (!init_text_p)
109 {
110 init_text_p = 1;
111 for (s = prog_bfd->sections; s; s = s->next)
112 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
113 {
114 text = s;
115 text_start = bfd_get_section_vma (prog_bfd, s);
116 text_end = text_start + bfd_section_size (prog_bfd, s);
117 break;
118 }
119 }
120
121 if (text && PC >= text_start && PC < text_end)
122 {
123 filename = (const char *)0;
124 functionname = (const char *)0;
125 linenumber = 0;
126 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
127 &filename, &functionname, &linenumber))
128 {
129 p = buf;
130 if (linenumber)
131 {
132 sprintf (p, "Line %5d ", linenumber);
133 p += strlen (p);
134 }
135
136 if (functionname)
137 {
138 sprintf (p, "Func %s ", functionname);
139 p += strlen (p);
140 }
141 else if (filename)
142 {
143 char *q = (char *) strrchr (filename, '/');
144 sprintf (p, "File %s ", (q) ? q+1 : filename);
145 p += strlen (p);
146 }
147
148 if (*p == ' ')
149 *p = '\0';
150 }
151 }
152
153 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
154 (unsigned)PC,
155 SIZE_LOCATION, SIZE_LOCATION, buf,
156 SIZE_INSTRUCTION, name);
157
158 switch (type)
159 {
160 default:
161 case OP_UNKNOWN:
162 case OP_NONE:
163 strcpy (buf, "unknown");
164 break;
165
166 case OP_TRAP:
167 sprintf (buf, "%d", OP[0]);
168 break;
169
170 case OP_REG:
171 sprintf (buf, "r%d", OP[0]);
172 break;
173
174 case OP_REG_REG:
175 case OP_REG_REG_CMP:
176 case OP_REG_REG_MOVE:
177 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
178 break;
179
180 case OP_IMM_REG:
181 case OP_IMM_REG_CMP:
182 case OP_IMM_REG_MOVE:
183 sprintf (buf, "%d,r%d", OP[0], OP[1]);
184 break;
185
186 case OP_COND_BR:
187 sprintf (buf, "%d", SEXT9 (OP[0]));
188 break;
189
190 case OP_LOAD16:
191 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
192 break;
193
194 case OP_STORE16:
195 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
196 break;
197
198 case OP_LOAD32:
199 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
200 break;
201
202 case OP_STORE32:
203 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
204 break;
205
206 case OP_JUMP:
207 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
208 break;
209
210 case OP_IMM_REG_REG:
211 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
212 break;
213
214 case OP_UIMM_REG_REG:
215 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
216 break;
217
218 case OP_BIT:
219 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
220 break;
221
222 case OP_EX1:
223 switch (OP[0] & 0xf)
224 {
225 default: cond = "?"; break;
226 case 0x0: cond = "v"; break;
227 case 0x1: cond = "c"; break;
228 case 0x2: cond = "z"; break;
229 case 0x3: cond = "nh"; break;
230 case 0x4: cond = "s"; break;
231 case 0x5: cond = "t"; break;
232 case 0x6: cond = "lt"; break;
233 case 0x7: cond = "le"; break;
234 case 0x8: cond = "nv"; break;
235 case 0x9: cond = "nc"; break;
236 case 0xa: cond = "nz"; break;
237 case 0xb: cond = "h"; break;
238 case 0xc: cond = "ns"; break;
239 case 0xd: cond = "sa"; break;
240 case 0xe: cond = "ge"; break;
241 case 0xf: cond = "gt"; break;
242 }
243
244 sprintf (buf, "%s,r%d", cond, OP[1]);
245 break;
246
247 case OP_EX2:
248 strcpy (buf, "EX2");
249 break;
250
251 case OP_LDSR:
252 case OP_STSR:
253 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
254 break;
255
256 case OP_PUSHPOP1:
257 for (i = 0; i < 12; i++)
258 if (OP[3] & (1 << type1_regs[i]))
259 strcat (buf, "r%d ", i + 20);
260 break;
261
262 case OP_PUSHPOP2:
263 for (i = 0; i < 16; i++)
264 if (OP[3] & (1 << type2_regs[i]))
265 strcat (buf, "r%d ", i + 16);
266 if (OP[3] & (1 << 19))
267 strcat (buf, "F/EIPC, F/EIPSW " );
268 break;
269
270 case OP_PUSHPOP3:
271 for (i = 0; i < 15; i++)
272 if (OP[3] & (1 << type3_regs[i]))
273 strcat (buf, "r%d ", i + 1);
274 if (OP[3] & (1 << 3))
275 strcat (buf, "PSW " );
276 if (OP[3] & (1 << 19))
277 strcat (buf, "F/EIPC, F/EIPSW " );
278 break;
279
280 case OP_BIT_CHANGE:
281 sprintf (buf, "r%d, [r%d]", OP[1], OP[0] );
282 break;
283 }
284
285 if ((v850_debug & DEBUG_VALUES) == 0)
286 {
287 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
288 }
289 else
290 {
291 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
292 switch (type)
293 {
294 default:
295 case OP_UNKNOWN:
296 case OP_NONE:
297 case OP_TRAP:
298 num_values = 0;
299 break;
300
301 case OP_REG:
302 case OP_REG_REG_MOVE:
303 values[0] = State.regs[OP[0]];
304 num_values = 1;
305 break;
306
307 case OP_BIT_CHANGE:
308 case OP_REG_REG:
309 case OP_REG_REG_CMP:
310 values[0] = State.regs[OP[1]];
311 values[1] = State.regs[OP[0]];
312 num_values = 2;
313 break;
314
315 case OP_IMM_REG:
316 case OP_IMM_REG_CMP:
317 values[0] = SEXT5 (OP[0]);
318 values[1] = OP[1];
319 num_values = 2;
320 break;
321
322 case OP_IMM_REG_MOVE:
323 values[0] = SEXT5 (OP[0]);
324 num_values = 1;
325 break;
326
327 case OP_COND_BR:
328 values[0] = State.pc;
329 values[1] = SEXT9 (OP[0]);
330 values[2] = PSW;
331 num_values = 3;
332 break;
333
334 case OP_LOAD16:
335 values[0] = OP[1] * size;
336 values[1] = State.regs[30];
337 num_values = 2;
338 break;
339
340 case OP_STORE16:
341 values[0] = State.regs[OP[0]];
342 values[1] = OP[1] * size;
343 values[2] = State.regs[30];
344 num_values = 3;
345 break;
346
347 case OP_LOAD32:
348 values[0] = SEXT16 (OP[2]);
349 values[1] = State.regs[OP[0]];
350 num_values = 2;
351 break;
352
353 case OP_STORE32:
354 values[0] = State.regs[OP[1]];
355 values[1] = SEXT16 (OP[2]);
356 values[2] = State.regs[OP[0]];
357 num_values = 3;
358 break;
359
360 case OP_JUMP:
361 values[0] = SEXT22 (OP[0]);
362 values[1] = State.pc;
363 num_values = 2;
364 break;
365
366 case OP_IMM_REG_REG:
367 values[0] = SEXT16 (OP[0]) << size;
368 values[1] = State.regs[OP[1]];
369 num_values = 2;
370 break;
371
372 case OP_UIMM_REG_REG:
373 values[0] = (OP[0] & 0xffff) << size;
374 values[1] = State.regs[OP[1]];
375 num_values = 2;
376 break;
377
378 case OP_BIT:
379 num_values = 0;
380 break;
381
382 case OP_EX1:
383 values[0] = PSW;
384 num_values = 1;
385 break;
386
387 case OP_EX2:
388 num_values = 0;
389 break;
390
391 case OP_LDSR:
392 values[0] = State.regs[OP[0]];
393 num_values = 1;
394 break;
395
396 case OP_STSR:
397 values[0] = State.sregs[OP[1]];
398 num_values = 1;
399 }
400
401 for (i = 0; i < num_values; i++)
402 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
403
404 while (i++ < 3)
405 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
406 }
407 }
408
409 static void
410 trace_output (result)
411 enum op_types result;
412 {
413 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
414 {
415 switch (result)
416 {
417 default:
418 case OP_UNKNOWN:
419 case OP_NONE:
420 case OP_TRAP:
421 case OP_REG:
422 case OP_REG_REG_CMP:
423 case OP_IMM_REG_CMP:
424 case OP_COND_BR:
425 case OP_STORE16:
426 case OP_STORE32:
427 case OP_BIT:
428 case OP_EX2:
429 break;
430
431 case OP_LOAD16:
432 case OP_STSR:
433 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
434 (unsigned long)State.regs[OP[0]]);
435 break;
436
437 case OP_REG_REG:
438 case OP_REG_REG_MOVE:
439 case OP_IMM_REG:
440 case OP_IMM_REG_MOVE:
441 case OP_LOAD32:
442 case OP_EX1:
443 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
444 (unsigned long)State.regs[OP[1]]);
445 break;
446
447 case OP_IMM_REG_REG:
448 case OP_UIMM_REG_REG:
449 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
450 (unsigned long)State.regs[OP[2]]);
451 break;
452
453 case OP_JUMP:
454 if (OP[1] != 0)
455 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
456 (unsigned long)State.regs[OP[1]]);
457 break;
458
459 case OP_LDSR:
460 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
461 (unsigned long)State.sregs[OP[1]]);
462 break;
463 }
464
465 (*v850_callback->printf_filtered) (v850_callback, "\n");
466 }
467 }
468
469 #else
470 #define trace_input(NAME, IN1, IN2)
471 #define trace_output(RESULT)
472
473 //#define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" );
474
475 #endif
476
477 \f
478 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
479 static unsigned int
480 condition_met (unsigned code)
481 {
482 unsigned int psw = PSW;
483
484 switch (code & 0xf)
485 {
486 case 0x0: return ((psw & PSW_OV) != 0);
487 case 0x1: return ((psw & PSW_CY) != 0);
488 case 0x2: return ((psw & PSW_Z) != 0);
489 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
490 case 0x4: return ((psw & PSW_S) != 0);
491 /*case 0x5: return 1;*/
492 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
493 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
494 case 0x8: return ((psw & PSW_OV) == 0);
495 case 0x9: return ((psw & PSW_CY) == 0);
496 case 0xa: return ((psw & PSW_Z) == 0);
497 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
498 case 0xc: return ((psw & PSW_S) == 0);
499 case 0xd: return ((psw & PSW_SAT) != 0);
500 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
501 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
502 }
503
504 return 1;
505 }
506
507 /* start-sanitize-v850e */
508 static unsigned long
509 Add32 (unsigned long a1, unsigned long a2, int * carry)
510 {
511 unsigned long result = (a1 + a2);
512
513 * carry = (result < a1);
514
515 return result;
516 }
517
518 static void
519 Multiply64 (boolean sign, unsigned long op0)
520 {
521 unsigned long op1;
522 unsigned long lo;
523 unsigned long mid1;
524 unsigned long mid2;
525 unsigned long hi;
526 unsigned long RdLo;
527 unsigned long RdHi;
528 int carry;
529
530 op1 = State.regs[ OP[1] ];
531
532 if (sign)
533 {
534 /* Compute sign of result and adjust operands if necessary. */
535
536 sign = (op0 ^ op1) & 0x80000000;
537
538 if (((signed long) op0) < 0)
539 op0 = - op0;
540
541 if (((signed long) op1) < 0)
542 op1 = - op1;
543 }
544
545 /* We can split the 32x32 into four 16x16 operations. This ensures
546 that we do not lose precision on 32bit only hosts: */
547 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
548 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
549 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
550 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
551
552 /* We now need to add all of these results together, taking care
553 to propogate the carries from the additions: */
554 RdLo = Add32 (lo, (mid1 << 16), & carry);
555 RdHi = carry;
556 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
557 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
558
559 if (sign)
560 {
561 /* Negate result if necessary. */
562
563 RdLo = ~ RdLo;
564 RdHi = ~ RdHi;
565 if (RdLo == 0xFFFFFFFF)
566 {
567 RdLo = 0;
568 RdHi += 1;
569 }
570 else
571 RdLo += 1;
572 }
573
574 State.regs[ OP[1] ] = RdLo;
575 State.regs[ OP[2] >> 11 ] = RdHi;
576
577 return;
578 }
579 /* end-sanitize-v850e */
580
581 \f
582 /* sld.b */
583 int
584 OP_300 ()
585 {
586 unsigned long result;
587
588 result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
589
590 /* start-sanitize-v850eq */
591 #ifdef ARCH_v850eq
592 trace_input ("sld.bu", OP_LOAD16, 1);
593
594 State.regs[ OP[1] ] = result;
595 #else
596 /* end-sanitize-v850eq */
597 trace_input ("sld.b", OP_LOAD16, 1);
598
599 State.regs[ OP[1] ] = SEXT8 (result);
600 /* start-sanitize-v850eq */
601 #endif
602 /* end-sanitize-v850eq */
603
604 trace_output (OP_LOAD16);
605
606 return 2;
607 }
608
609 /* sld.h */
610 int
611 OP_400 ()
612 {
613 unsigned long result;
614
615 result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
616
617 /* start-sanitize-v850eq */
618 #ifdef ARCH_v850eq
619 trace_input ("sld.hu", OP_LOAD16, 2);
620
621 State.regs[ OP[1] ] = result;
622 #else
623 /* end-sanitize-v850eq */
624 trace_input ("sld.h", OP_LOAD16, 2);
625
626 State.regs[ OP[1] ] = SEXT16 (result);
627 /* start-sanitize-v850eq */
628 #endif
629 /* end-sanitize-v850eq */
630
631 trace_output (OP_LOAD16);
632
633 return 2;
634 }
635
636 /* sld.w */
637 int
638 OP_500 ()
639 {
640 trace_input ("sld.w", OP_LOAD16, 4);
641
642 State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
643
644 trace_output (OP_LOAD16);
645
646 return 2;
647 }
648
649 /* sst.b */
650 int
651 OP_380 ()
652 {
653 trace_input ("sst.b", OP_STORE16, 1);
654
655 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
656
657 trace_output (OP_STORE16);
658
659 return 2;
660 }
661
662 /* sst.h */
663 int
664 OP_480 ()
665 {
666 trace_input ("sst.h", OP_STORE16, 2);
667
668 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
669
670 trace_output (OP_STORE16);
671
672 return 2;
673 }
674
675 /* sst.w */
676 int
677 OP_501 ()
678 {
679 trace_input ("sst.w", OP_STORE16, 4);
680
681 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
682
683 trace_output (OP_STORE16);
684
685 return 2;
686 }
687
688 /* ld.b */
689 int
690 OP_700 ()
691 {
692 int adr;
693
694 trace_input ("ld.b", OP_LOAD32, 1);
695
696 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
697
698 State.regs[ OP[1] ] = SEXT8 (load_mem (adr, 1));
699
700 trace_output (OP_LOAD32);
701
702 return 4;
703 }
704
705 /* ld.h */
706 int
707 OP_720 ()
708 {
709 int adr;
710
711 trace_input ("ld.h", OP_LOAD32, 2);
712
713 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
714 adr &= ~0x1;
715
716 State.regs[ OP[1] ] = SEXT16 (load_mem (adr, 2));
717
718 trace_output (OP_LOAD32);
719
720 return 4;
721 }
722
723 /* ld.w */
724 int
725 OP_10720 ()
726 {
727 int adr;
728
729 trace_input ("ld.w", OP_LOAD32, 4);
730
731 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
732 adr &= ~0x3;
733
734 State.regs[ OP[1] ] = load_mem (adr, 4);
735
736 trace_output (OP_LOAD32);
737
738 return 4;
739 }
740
741 /* st.b */
742 int
743 OP_740 ()
744 {
745 trace_input ("st.b", OP_STORE32, 1);
746
747 store_mem (State.regs[ OP[0] ] + SEXT16 (OP[2]), 1, State.regs[ OP[1] ]);
748
749 trace_output (OP_STORE32);
750
751 return 4;
752 }
753
754 /* st.h */
755 int
756 OP_760 ()
757 {
758 int adr;
759
760 trace_input ("st.h", OP_STORE32, 2);
761
762 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
763 adr &= ~1;
764
765 store_mem (adr, 2, State.regs[ OP[1] ]);
766
767 trace_output (OP_STORE32);
768
769 return 4;
770 }
771
772 /* st.w */
773 int
774 OP_10760 ()
775 {
776 int adr;
777
778 trace_input ("st.w", OP_STORE32, 4);
779
780 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
781 adr &= ~3;
782
783 store_mem (adr, 4, State.regs[ OP[1] ]);
784
785 trace_output (OP_STORE32);
786
787 return 4;
788 }
789
790 static int
791 branch (int code)
792 {
793 unsigned int psw;
794 int op0;
795
796 trace_input ("Bcond", OP_COND_BR, 0);
797 trace_output (OP_COND_BR);
798
799 if (condition_met (code))
800 return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
801 else
802 return 2;
803 }
804
805 /* bv disp9 */
806 int
807 OP_580 ()
808 {
809 return branch (0);
810 }
811
812 /* bl disp9 */
813 int
814 OP_581 ()
815 {
816 return branch (1);
817 }
818
819 /* be disp9 */
820 int
821 OP_582 ()
822 {
823 return branch (2);
824 }
825
826 /* bnh disp 9*/
827 int
828 OP_583 ()
829 {
830 return branch (3);
831 }
832
833 /* bn disp9 */
834 int
835 OP_584 ()
836 {
837 return branch (4);
838 }
839
840 /* br disp9 */
841 int
842 OP_585 ()
843 {
844 return branch (5);
845 }
846
847 /* blt disp9 */
848 int
849 OP_586 ()
850 {
851 return branch (6);
852 }
853
854 /* ble disp9 */
855 int
856 OP_587 ()
857 {
858 return branch (7);
859 }
860
861 /* bnv disp9 */
862 int
863 OP_588 ()
864 {
865 return branch (8);
866 }
867
868 /* bnl disp9 */
869 int
870 OP_589 ()
871 {
872 return branch (9);
873 }
874
875 /* bne disp9 */
876 int
877 OP_58A ()
878 {
879 return branch (10);
880 }
881
882 /* bh disp9 */
883 int
884 OP_58B ()
885 {
886 return branch (11);
887 }
888
889 /* bp disp9 */
890 int
891 OP_58C ()
892 {
893 return branch (12);
894 }
895
896 /* bsa disp9 */
897 int
898 OP_58D ()
899 {
900 return branch (13);
901 }
902
903 /* bge disp9 */
904 int
905 OP_58E ()
906 {
907 return branch (14);
908 }
909
910 /* bgt disp9 */
911 int
912 OP_58F ()
913 {
914 return branch (15);
915 }
916
917 /* jmp [reg1] */
918 /* sld.bu disp4[ep], reg2 */
919 int
920 OP_60 ()
921 {
922 if (OP[1] == 0)
923 {
924 trace_input ("jmp", OP_REG, 0);
925
926 PC = State.regs[ OP[0] ];
927
928 trace_output (OP_REG);
929
930 return 0; /* Add nothing to the PC, we have already done it. */
931 }
932 /* start-sanitize-v850e */
933 else
934 {
935 unsigned long result;
936
937 result = load_mem (State.regs[30] + (OP[3] & 0xf), 1);
938
939 /* start-sanitize-v850eq */
940 #ifdef ARCH_v850eq
941 trace_input ("sld.b", OP_LOAD16, 1);
942
943 State.regs[ OP[1] ] = SEXT8 (result);
944 #else
945 /* end-sanitize-v850eq */
946 trace_input ("sld.bu", OP_LOAD16, 1);
947
948 State.regs[ OP[1] ] = result;
949 /* start-sanitize-v850eq */
950 #endif
951 /* end-sanitize-v850eq */
952
953 trace_output (OP_LOAD16);
954
955 return 2;
956 }
957 /* end-sanitize-v850e */
958 }
959
960 /* jarl/jr disp22, reg */
961 int
962 OP_780 ()
963 {
964 trace_input ("jarl/jr", OP_JUMP, 0);
965
966 if (OP[ 1 ] != 0)
967 State.regs[ OP[1] ] = PC + 4;
968
969 trace_output (OP_JUMP);
970
971 return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
972 }
973
974 /* add reg, reg */
975 int
976 OP_1C0 ()
977 {
978 unsigned int op0, op1, result, z, s, cy, ov;
979
980 trace_input ("add", OP_REG_REG, 0);
981
982 /* Compute the result. */
983
984 op0 = State.regs[ OP[0] ];
985 op1 = State.regs[ OP[1] ];
986
987 result = op0 + op1;
988
989 /* Compute the condition codes. */
990 z = (result == 0);
991 s = (result & 0x80000000);
992 cy = (result < op0 || result < op1);
993 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
994 && (op0 & 0x80000000) != (result & 0x80000000));
995
996 /* Store the result and condition codes. */
997 State.regs[OP[1]] = result;
998 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
999 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1000 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1001 trace_output (OP_REG_REG);
1002
1003 return 2;
1004 }
1005
1006 /* add sign_extend(imm5), reg */
1007 int
1008 OP_240 ()
1009 {
1010 unsigned int op0, op1, result, z, s, cy, ov;
1011 int temp;
1012
1013 trace_input ("add", OP_IMM_REG, 0);
1014
1015 /* Compute the result. */
1016 temp = SEXT5 (OP[0]);
1017 op0 = temp;
1018 op1 = State.regs[OP[1]];
1019 result = op0 + op1;
1020
1021 /* Compute the condition codes. */
1022 z = (result == 0);
1023 s = (result & 0x80000000);
1024 cy = (result < op0 || result < op1);
1025 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1026 && (op0 & 0x80000000) != (result & 0x80000000));
1027
1028 /* Store the result and condition codes. */
1029 State.regs[OP[1]] = result;
1030 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1031 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1032 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1033 trace_output (OP_IMM_REG);
1034
1035 return 2;
1036 }
1037
1038 /* addi sign_extend(imm16), reg, reg */
1039 int
1040 OP_600 ()
1041 {
1042 unsigned int op0, op1, result, z, s, cy, ov;
1043
1044 trace_input ("addi", OP_IMM_REG_REG, 0);
1045
1046 /* Compute the result. */
1047
1048 op0 = SEXT16 (OP[2]);
1049 op1 = State.regs[ OP[0] ];
1050 result = op0 + op1;
1051
1052 /* Compute the condition codes. */
1053 z = (result == 0);
1054 s = (result & 0x80000000);
1055 cy = (result < op0 || result < op1);
1056 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1057 && (op0 & 0x80000000) != (result & 0x80000000));
1058
1059 /* Store the result and condition codes. */
1060 State.regs[OP[1]] = result;
1061 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1062 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1063 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1064 trace_output (OP_IMM_REG_REG);
1065
1066 return 4;
1067 }
1068
1069 /* sub reg1, reg2 */
1070 int
1071 OP_1A0 ()
1072 {
1073 unsigned int op0, op1, result, z, s, cy, ov;
1074
1075 trace_input ("sub", OP_REG_REG, 0);
1076 /* Compute the result. */
1077 op0 = State.regs[ OP[0] ];
1078 op1 = State.regs[ OP[1] ];
1079 result = op1 - op0;
1080
1081 /* Compute the condition codes. */
1082 z = (result == 0);
1083 s = (result & 0x80000000);
1084 cy = (op1 < op0);
1085 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1086 && (op1 & 0x80000000) != (result & 0x80000000));
1087
1088 /* Store the result and condition codes. */
1089 State.regs[OP[1]] = result;
1090 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1091 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1092 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1093 trace_output (OP_REG_REG);
1094
1095 return 2;
1096 }
1097
1098 /* subr reg1, reg2 */
1099 int
1100 OP_180 ()
1101 {
1102 unsigned int op0, op1, result, z, s, cy, ov;
1103
1104 trace_input ("subr", OP_REG_REG, 0);
1105 /* Compute the result. */
1106 op0 = State.regs[ OP[0] ];
1107 op1 = State.regs[ OP[1] ];
1108 result = op0 - op1;
1109
1110 /* Compute the condition codes. */
1111 z = (result == 0);
1112 s = (result & 0x80000000);
1113 cy = (op0 < op1);
1114 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1115 && (op0 & 0x80000000) != (result & 0x80000000));
1116
1117 /* Store the result and condition codes. */
1118 State.regs[OP[1]] = result;
1119 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1120 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1121 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1122 trace_output (OP_REG_REG);
1123
1124 return 2;
1125 }
1126
1127 /* sxh reg1 */
1128 /* mulh reg1, reg2 */
1129 int
1130 OP_E0 ()
1131 {
1132 /* start-sanitize-v850e */
1133 if (OP[1] == 0)
1134 {
1135 trace_input ("sxh", OP_REG, 0);
1136
1137 State.regs[ OP[0] ] = SEXT16 (State.regs[ OP[0] ]);
1138
1139 trace_output (OP_REG);
1140 }
1141 else
1142 /* end-sanitize-v850e */
1143 {
1144 trace_input ("mulh", OP_REG_REG, 0);
1145
1146 State.regs[ OP[1] ] = (SEXT16 (State.regs[ OP[1] ]) * SEXT16 (State.regs[ OP[0] ]));
1147
1148 trace_output (OP_REG_REG);
1149 }
1150
1151 return 2;
1152 }
1153
1154 /* mulh sign_extend(imm5), reg2 */
1155 int
1156 OP_2E0 ()
1157 {
1158 trace_input ("mulh", OP_IMM_REG, 0);
1159
1160 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
1161
1162 trace_output (OP_IMM_REG);
1163
1164 return 2;
1165 }
1166
1167 /* mulhi imm16, reg1, reg2 */
1168 int
1169 OP_6E0 ()
1170 {
1171 if (OP[1] == 0)
1172 {
1173 }
1174 else
1175 {
1176 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1177
1178 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[0] ]) * SEXT16 (OP[2]);
1179
1180 trace_output (OP_IMM_REG_REG);
1181 }
1182
1183 return 4;
1184 }
1185
1186 /* divh reg1, reg2 */
1187 /* switch reg1 */
1188 int
1189 OP_40 ()
1190 {
1191 /* start-sanitize-v850e */
1192 if (OP[1] == 0)
1193 {
1194 unsigned long adr;
1195
1196 trace_input ("switch", OP_REG, 0);
1197
1198 adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
1199 State.pc = State.pc + 2 + (SEXT16 (load_mem (adr, 2)) << 1);
1200
1201 trace_output (OP_REG);
1202 }
1203 else
1204 /* end-sanitize-v850e */
1205 {
1206 unsigned int op0, op1, result, ov, s, z;
1207 int temp;
1208
1209 trace_input ("divh", OP_REG_REG, 0);
1210
1211 /* Compute the result. */
1212 temp = SEXT16 (State.regs[ OP[0] ]);
1213 op0 = temp;
1214 op1 = State.regs[OP[1]];
1215
1216 if (op0 == 0xffffffff && op1 == 0x80000000)
1217 {
1218 result = 0x80000000;
1219 ov = 1;
1220 }
1221 else if (op0 != 0)
1222 {
1223 result = op1 / op0;
1224 ov = 0;
1225 }
1226 else
1227 {
1228 result = 0x0;
1229 ov = 1;
1230 }
1231
1232 /* Compute the condition codes. */
1233 z = (result == 0);
1234 s = (result & 0x80000000);
1235
1236 /* Store the result and condition codes. */
1237 State.regs[OP[1]] = result;
1238 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1239 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1240 | (ov ? PSW_OV : 0));
1241 trace_output (OP_REG_REG);
1242 }
1243
1244 return 2;
1245 }
1246
1247 /* cmp reg, reg */
1248 int
1249 OP_1E0 ()
1250 {
1251 unsigned int op0, op1, result, z, s, cy, ov;
1252
1253 trace_input ("cmp", OP_REG_REG_CMP, 0);
1254 /* Compute the result. */
1255 op0 = State.regs[ OP[0] ];
1256 op1 = State.regs[ OP[1] ];
1257 result = op1 - op0;
1258
1259 /* Compute the condition codes. */
1260 z = (result == 0);
1261 s = (result & 0x80000000);
1262 cy = (op1 < op0);
1263 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1264 && (op1 & 0x80000000) != (result & 0x80000000));
1265
1266 /* Set condition codes. */
1267 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1268 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1269 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1270 trace_output (OP_REG_REG_CMP);
1271
1272 return 2;
1273 }
1274
1275 /* cmp sign_extend(imm5), reg */
1276 int
1277 OP_260 ()
1278 {
1279 unsigned int op0, op1, result, z, s, cy, ov;
1280 int temp;
1281
1282 /* Compute the result. */
1283 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1284 temp = SEXT5 (OP[0]);
1285 op0 = temp;
1286 op1 = State.regs[OP[1]];
1287 result = op1 - op0;
1288
1289 /* Compute the condition codes. */
1290 z = (result == 0);
1291 s = (result & 0x80000000);
1292 cy = (op1 < op0);
1293 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1294 && (op1 & 0x80000000) != (result & 0x80000000));
1295
1296 /* Set condition codes. */
1297 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1298 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1299 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1300 trace_output (OP_IMM_REG_CMP);
1301
1302 return 2;
1303 }
1304
1305 /* setf cccc,reg2 */
1306 int
1307 OP_7E0 ()
1308 {
1309 trace_input ("setf", OP_EX1, 0);
1310
1311 State.regs[ OP[1] ] = condition_met (OP[0]);
1312
1313 trace_output (OP_EX1);
1314
1315 return 4;
1316 }
1317
1318 /* zxh reg1 */
1319 /* satadd reg,reg */
1320 int
1321 OP_C0 ()
1322 {
1323 /* start-sanitize-v850e */
1324 if (OP[1] == 0)
1325 {
1326 trace_input ("zxh", OP_REG, 0);
1327
1328 State.regs[ OP[0] ] &= 0xffff;
1329
1330 trace_output (OP_REG);
1331 }
1332 else
1333 /* end-sanitize-v850e */
1334 {
1335 unsigned int op0, op1, result, z, s, cy, ov, sat;
1336
1337 trace_input ("satadd", OP_REG_REG, 0);
1338 /* Compute the result. */
1339 op0 = State.regs[ OP[0] ];
1340 op1 = State.regs[ OP[1] ];
1341 result = op0 + op1;
1342
1343 /* Compute the condition codes. */
1344 z = (result == 0);
1345 s = (result & 0x80000000);
1346 cy = (result < op0 || result < op1);
1347 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1348 && (op0 & 0x80000000) != (result & 0x80000000));
1349 sat = ov;
1350
1351 /* Store the result and condition codes. */
1352 State.regs[OP[1]] = result;
1353 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1354 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1355 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1356 | (sat ? PSW_SAT : 0));
1357
1358 /* Handle saturated results. */
1359 if (sat && s)
1360 State.regs[OP[1]] = 0x80000000;
1361 else if (sat)
1362 State.regs[OP[1]] = 0x7fffffff;
1363 trace_output (OP_REG_REG);
1364 }
1365
1366 return 2;
1367 }
1368
1369 /* satadd sign_extend(imm5), reg */
1370 int
1371 OP_220 ()
1372 {
1373 unsigned int op0, op1, result, z, s, cy, ov, sat;
1374
1375 int temp;
1376
1377 trace_input ("satadd", OP_IMM_REG, 0);
1378
1379 /* Compute the result. */
1380 temp = SEXT5 (OP[0]);
1381 op0 = temp;
1382 op1 = State.regs[OP[1]];
1383 result = op0 + op1;
1384
1385 /* Compute the condition codes. */
1386 z = (result == 0);
1387 s = (result & 0x80000000);
1388 cy = (result < op0 || result < op1);
1389 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1390 && (op0 & 0x80000000) != (result & 0x80000000));
1391 sat = ov;
1392
1393 /* Store the result and condition codes. */
1394 State.regs[OP[1]] = result;
1395 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1396 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1397 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1398 | (sat ? PSW_SAT : 0));
1399
1400 /* Handle saturated results. */
1401 if (sat && s)
1402 State.regs[OP[1]] = 0x80000000;
1403 else if (sat)
1404 State.regs[OP[1]] = 0x7fffffff;
1405 trace_output (OP_IMM_REG);
1406
1407 return 2;
1408 }
1409
1410 /* satsub reg1, reg2 */
1411 /* sxb reg1 */
1412 int
1413 OP_A0 ()
1414 {
1415 /* start-sanitize-v850e */
1416 if (OP[1] == 0)
1417 {
1418 trace_input ("sxb", OP_REG, 0);
1419
1420 State.regs[ OP[0] ] = SEXT8 (State.regs[ OP[0] ]);
1421
1422 trace_output (OP_REG);
1423 }
1424 else
1425 /* end-sanitize-v850e */
1426 {
1427 unsigned int op0, op1, result, z, s, cy, ov, sat;
1428
1429 trace_input ("satsub", OP_REG_REG, 0);
1430
1431 /* Compute the result. */
1432 op0 = State.regs[ OP[0] ];
1433 op1 = State.regs[ OP[1] ];
1434 result = op1 - op0;
1435
1436 /* Compute the condition codes. */
1437 z = (result == 0);
1438 s = (result & 0x80000000);
1439 cy = (op1 < op0);
1440 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1441 && (op1 & 0x80000000) != (result & 0x80000000));
1442 sat = ov;
1443
1444 /* Store the result and condition codes. */
1445 State.regs[OP[1]] = result;
1446 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1447 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1448 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1449 | (sat ? PSW_SAT : 0));
1450
1451 /* Handle saturated results. */
1452 if (sat && s)
1453 State.regs[OP[1]] = 0x80000000;
1454 else if (sat)
1455 State.regs[OP[1]] = 0x7fffffff;
1456 trace_output (OP_REG_REG);
1457 }
1458
1459 return 2;
1460 }
1461
1462 /* satsubi sign_extend(imm16), reg */
1463 int
1464 OP_660 ()
1465 {
1466 unsigned int op0, op1, result, z, s, cy, ov, sat;
1467 int temp;
1468
1469 trace_input ("satsubi", OP_IMM_REG, 0);
1470
1471 /* Compute the result. */
1472 temp = SEXT16 (OP[2]);
1473 op0 = temp;
1474 op1 = State.regs[ OP[0] ];
1475 result = op1 - op0;
1476
1477 /* Compute the condition codes. */
1478 z = (result == 0);
1479 s = (result & 0x80000000);
1480 cy = (op1 < op0);
1481 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1482 && (op1 & 0x80000000) != (result & 0x80000000));
1483 sat = ov;
1484
1485 /* Store the result and condition codes. */
1486 State.regs[OP[1]] = result;
1487 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1488 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1489 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1490 | (sat ? PSW_SAT : 0));
1491
1492 /* Handle saturated results. */
1493 if (sat && s)
1494 State.regs[OP[1]] = 0x80000000;
1495 else if (sat)
1496 State.regs[OP[1]] = 0x7fffffff;
1497 trace_output (OP_IMM_REG);
1498
1499 return 4;
1500 }
1501
1502 /* satsubr reg,reg */
1503 /* zxb reg1 */
1504 int
1505 OP_80 ()
1506 {
1507 /* start-sanitize-v850e */
1508 if (OP[1] == 0)
1509 {
1510 trace_input ("zxb", OP_REG, 0);
1511
1512 State.regs[ OP[0] ] &= 0xff;
1513
1514 trace_output (OP_REG);
1515 }
1516 else
1517 /* end-sanitize-v850e */
1518 {
1519 unsigned int op0, op1, result, z, s, cy, ov, sat;
1520
1521 trace_input ("satsubr", OP_REG_REG, 0);
1522
1523 /* Compute the result. */
1524 op0 = State.regs[ OP[0] ];
1525 op1 = State.regs[ OP[1] ];
1526 result = op0 - op1;
1527
1528 /* Compute the condition codes. */
1529 z = (result == 0);
1530 s = (result & 0x80000000);
1531 cy = (result < op0);
1532 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1533 && (op1 & 0x80000000) != (result & 0x80000000));
1534 sat = ov;
1535
1536 /* Store the result and condition codes. */
1537 State.regs[OP[1]] = result;
1538 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1539 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1540 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1541 | (sat ? PSW_SAT : 0));
1542
1543 /* Handle saturated results. */
1544 if (sat && s)
1545 State.regs[OP[1]] = 0x80000000;
1546 else if (sat)
1547 State.regs[OP[1]] = 0x7fffffff;
1548 trace_output (OP_REG_REG);
1549 }
1550
1551 return 2;
1552 }
1553
1554 /* tst reg,reg */
1555 int
1556 OP_160 ()
1557 {
1558 unsigned int op0, op1, result, z, s;
1559
1560 trace_input ("tst", OP_REG_REG_CMP, 0);
1561
1562 /* Compute the result. */
1563 op0 = State.regs[ OP[0] ];
1564 op1 = State.regs[ OP[1] ];
1565 result = op0 & op1;
1566
1567 /* Compute the condition codes. */
1568 z = (result == 0);
1569 s = (result & 0x80000000);
1570
1571 /* Store the condition codes. */
1572 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1573 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1574 trace_output (OP_REG_REG_CMP);
1575
1576 return 2;
1577 }
1578
1579 /* mov reg, reg */
1580 int
1581 OP_0 ()
1582 {
1583 trace_input ("mov", OP_REG_REG_MOVE, 0);
1584
1585 State.regs[ OP[1] ] = State.regs[ OP[0] ];
1586
1587 trace_output (OP_REG_REG_MOVE);
1588
1589 return 2;
1590 }
1591
1592 /* mov sign_extend(imm5), reg */
1593 /* callt imm6 */
1594 int
1595 OP_200 ()
1596 {
1597 /* start-sanitize-v850e */
1598 if (OP[1] == 0)
1599 {
1600 unsigned long adr;
1601
1602 trace_input ("callt", OP_LOAD16, 1);
1603
1604 CTPC = PC + 2;
1605 CTPSW = PSW;
1606
1607 adr = CTBP + ((OP[3] & 0x3f) << 1);
1608
1609 PC = CTBP + load_mem (adr, 1);
1610
1611 trace_output (OP_LOAD16);
1612
1613 return 0;
1614 }
1615 else
1616 /* end-sanitize-v850e */
1617 {
1618 int value = SEXT5 (OP[0]);
1619
1620 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1621
1622 State.regs[ OP[1] ] = value;
1623
1624 trace_output (OP_IMM_REG_MOVE);
1625
1626 return 2;
1627 }
1628 }
1629
1630 /* mov imm32, reg1 */
1631 /* movea sign_extend(imm16), reg, reg */
1632 int
1633 OP_620 ()
1634 {
1635 /* start-sanitize-v850e */
1636 if (OP[1] == 0)
1637 {
1638 trace_input ("mov", OP_IMM32_REG, 4);
1639
1640 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1641
1642 trace_output (OP_IMM32_REG);
1643
1644 return 6;
1645 }
1646 else
1647 /* end-sanitize-v850e */
1648 {
1649 trace_input ("movea", OP_IMM_REG_REG, 0);
1650
1651 State.regs[ OP[1] ] = State.regs[ OP[0] ] + SEXT16 (OP[2]);
1652
1653 trace_output (OP_IMM_REG_REG);
1654
1655 return 4;
1656 }
1657 }
1658
1659 /* dispose imm5, list12 [, reg1] */
1660 /* movhi imm16, reg, reg */
1661 int
1662 OP_640 ()
1663 {
1664 /* start-sanitize-v850e */
1665
1666 if (OP[1] == 0)
1667 {
1668 int i;
1669
1670 trace_input ("dispose", OP_PUSHPOP1, 0);
1671
1672 SP += (OP[3] & 0x3e) << 1;
1673
1674 /* Load the registers with lower number registers being retrieved from lower addresses. */
1675 for (i = 0; i < 12; i++)
1676 if ((OP[3] & (1 << type1_regs[ i ])))
1677 {
1678 State.regs[ 20 + i ] = load_mem (SP, 4);
1679 SP += 4;
1680 }
1681
1682 if ((OP[3] & 0x1f0000) != 0)
1683 {
1684 PC = State.regs[ (OP[3] >> 16) & 0x1f];
1685 return 0;
1686 }
1687
1688 trace_output (OP_PUSHPOP1);
1689 }
1690 else
1691 /* end-sanitize-v850e */
1692 {
1693 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1694
1695 State.regs[ OP[1] ] = State.regs[ OP[0] ] + OP[2] << 16;
1696
1697 trace_output (OP_UIMM_REG_REG);
1698 }
1699
1700 return 4;
1701 }
1702
1703 /* sar zero_extend(imm5),reg1 */
1704 int
1705 OP_2A0 ()
1706 {
1707 unsigned int op0, op1, result, z, s, cy;
1708
1709 trace_input ("sar", OP_IMM_REG, 0);
1710 op0 = OP[0];
1711 op1 = State.regs[ OP[1] ];
1712 result = (signed)op1 >> op0;
1713
1714 /* Compute the condition codes. */
1715 z = (result == 0);
1716 s = (result & 0x80000000);
1717 cy = (op1 & (1 << (op0 - 1)));
1718
1719 /* Store the result and condition codes. */
1720 State.regs[ OP[1] ] = result;
1721 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1722 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1723 | (cy ? PSW_CY : 0));
1724 trace_output (OP_IMM_REG);
1725
1726 return 2;
1727 }
1728
1729 /* sar reg1, reg2 */
1730 int
1731 OP_A007E0 ()
1732 {
1733 unsigned int op0, op1, result, z, s, cy;
1734
1735 trace_input ("sar", OP_REG_REG, 0);
1736
1737 op0 = State.regs[ OP[0] ] & 0x1f;
1738 op1 = State.regs[ OP[1] ];
1739 result = (signed)op1 >> op0;
1740
1741 /* Compute the condition codes. */
1742 z = (result == 0);
1743 s = (result & 0x80000000);
1744 cy = (op1 & (1 << (op0 - 1)));
1745
1746 /* Store the result and condition codes. */
1747 State.regs[OP[1]] = result;
1748 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1749 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1750 | (cy ? PSW_CY : 0));
1751 trace_output (OP_REG_REG);
1752
1753 return 4;
1754 }
1755
1756 /* shl zero_extend(imm5),reg1 */
1757 int
1758 OP_2C0 ()
1759 {
1760 unsigned int op0, op1, result, z, s, cy;
1761
1762 trace_input ("shl", OP_IMM_REG, 0);
1763 op0 = OP[0];
1764 op1 = State.regs[ OP[1] ];
1765 result = op1 << op0;
1766
1767 /* Compute the condition codes. */
1768 z = (result == 0);
1769 s = (result & 0x80000000);
1770 cy = (op1 & (1 << (32 - op0)));
1771
1772 /* Store the result and condition codes. */
1773 State.regs[OP[1]] = result;
1774 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1775 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1776 | (cy ? PSW_CY : 0));
1777 trace_output (OP_IMM_REG);
1778
1779 return 2;
1780 }
1781
1782 /* shl reg1, reg2 */
1783 int
1784 OP_C007E0 ()
1785 {
1786 unsigned int op0, op1, result, z, s, cy;
1787
1788 trace_input ("shl", OP_REG_REG, 0);
1789 op0 = State.regs[ OP[0] ] & 0x1f;
1790 op1 = State.regs[ OP[1] ];
1791 result = op1 << op0;
1792
1793 /* Compute the condition codes. */
1794 z = (result == 0);
1795 s = (result & 0x80000000);
1796 cy = (op1 & (1 << (32 - op0)));
1797
1798 /* Store the result and condition codes. */
1799 State.regs[OP[1]] = result;
1800 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1801 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1802 | (cy ? PSW_CY : 0));
1803 trace_output (OP_REG_REG);
1804
1805 return 4;
1806 }
1807
1808 /* shr zero_extend(imm5),reg1 */
1809 int
1810 OP_280 ()
1811 {
1812 unsigned int op0, op1, result, z, s, cy;
1813
1814 trace_input ("shr", OP_IMM_REG, 0);
1815 op0 = OP[0];
1816 op1 = State.regs[ OP[1] ];
1817 result = op1 >> op0;
1818
1819 /* Compute the condition codes. */
1820 z = (result == 0);
1821 s = (result & 0x80000000);
1822 cy = (op1 & (1 << (op0 - 1)));
1823
1824 /* Store the result and condition codes. */
1825 State.regs[OP[1]] = result;
1826 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1827 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1828 | (cy ? PSW_CY : 0));
1829 trace_output (OP_IMM_REG);
1830
1831 return 2;
1832 }
1833
1834 /* shr reg1, reg2 */
1835 int
1836 OP_8007E0 ()
1837 {
1838 unsigned int op0, op1, result, z, s, cy;
1839
1840 trace_input ("shr", OP_REG_REG, 0);
1841 op0 = State.regs[ OP[0] ] & 0x1f;
1842 op1 = State.regs[ OP[1] ];
1843 result = op1 >> op0;
1844
1845 /* Compute the condition codes. */
1846 z = (result == 0);
1847 s = (result & 0x80000000);
1848 cy = (op1 & (1 << (op0 - 1)));
1849
1850 /* Store the result and condition codes. */
1851 State.regs[OP[1]] = result;
1852 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1853 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1854 | (cy ? PSW_CY : 0));
1855 trace_output (OP_REG_REG);
1856
1857 return 4;
1858 }
1859
1860 /* or reg, reg */
1861 int
1862 OP_100 ()
1863 {
1864 unsigned int op0, op1, result, z, s;
1865
1866 trace_input ("or", OP_REG_REG, 0);
1867
1868 /* Compute the result. */
1869 op0 = State.regs[ OP[0] ];
1870 op1 = State.regs[ OP[1] ];
1871 result = op0 | op1;
1872
1873 /* Compute the condition codes. */
1874 z = (result == 0);
1875 s = (result & 0x80000000);
1876
1877 /* Store the result and condition codes. */
1878 State.regs[OP[1]] = result;
1879 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1880 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1881 trace_output (OP_REG_REG);
1882
1883 return 2;
1884 }
1885
1886 /* ori zero_extend(imm16), reg, reg */
1887 int
1888 OP_680 ()
1889 {
1890 unsigned int op0, op1, result, z, s;
1891
1892 trace_input ("ori", OP_UIMM_REG_REG, 0);
1893 op0 = OP[2];
1894 op1 = State.regs[ OP[0] ];
1895 result = op0 | op1;
1896
1897 /* Compute the condition codes. */
1898 z = (result == 0);
1899 s = (result & 0x80000000);
1900
1901 /* Store the result and condition codes. */
1902 State.regs[OP[1]] = result;
1903 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1904 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1905 trace_output (OP_UIMM_REG_REG);
1906
1907 return 4;
1908 }
1909
1910 /* and reg, reg */
1911 int
1912 OP_140 ()
1913 {
1914 unsigned int op0, op1, result, z, s;
1915
1916 trace_input ("and", OP_REG_REG, 0);
1917
1918 /* Compute the result. */
1919 op0 = State.regs[ OP[0] ];
1920 op1 = State.regs[ OP[1] ];
1921 result = op0 & op1;
1922
1923 /* Compute the condition codes. */
1924 z = (result == 0);
1925 s = (result & 0x80000000);
1926
1927 /* Store the result and condition codes. */
1928 State.regs[OP[1]] = result;
1929 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1930 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1931 trace_output (OP_REG_REG);
1932
1933 return 2;
1934 }
1935
1936 /* andi zero_extend(imm16), reg, reg */
1937 int
1938 OP_6C0 ()
1939 {
1940 unsigned int result, z;
1941
1942 trace_input ("andi", OP_UIMM_REG_REG, 0);
1943
1944 result = OP[2] & State.regs[ OP[0] ];
1945
1946 /* Compute the condition codes. */
1947 z = (result == 0);
1948
1949 /* Store the result and condition codes. */
1950 State.regs[ OP[1] ] = result;
1951
1952 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1953 PSW |= (z ? PSW_Z : 0);
1954
1955 trace_output (OP_UIMM_REG_REG);
1956
1957 return 4;
1958 }
1959
1960 /* xor reg, reg */
1961 int
1962 OP_120 ()
1963 {
1964 unsigned int op0, op1, result, z, s;
1965
1966 trace_input ("xor", OP_REG_REG, 0);
1967
1968 /* Compute the result. */
1969 op0 = State.regs[ OP[0] ];
1970 op1 = State.regs[ OP[1] ];
1971 result = op0 ^ op1;
1972
1973 /* Compute the condition codes. */
1974 z = (result == 0);
1975 s = (result & 0x80000000);
1976
1977 /* Store the result and condition codes. */
1978 State.regs[OP[1]] = result;
1979 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1980 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1981 trace_output (OP_REG_REG);
1982
1983 return 2;
1984 }
1985
1986 /* xori zero_extend(imm16), reg, reg */
1987 int
1988 OP_6A0 ()
1989 {
1990 unsigned int op0, op1, result, z, s;
1991
1992 trace_input ("xori", OP_UIMM_REG_REG, 0);
1993 op0 = OP[2];
1994 op1 = State.regs[ OP[0] ];
1995 result = op0 ^ op1;
1996
1997 /* Compute the condition codes. */
1998 z = (result == 0);
1999 s = (result & 0x80000000);
2000
2001 /* Store the result and condition codes. */
2002 State.regs[OP[1]] = result;
2003 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2004 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2005 trace_output (OP_UIMM_REG_REG);
2006
2007 return 4;
2008 }
2009
2010 /* not reg1, reg2 */
2011 int
2012 OP_20 ()
2013 {
2014 unsigned int op0, result, z, s;
2015
2016 trace_input ("not", OP_REG_REG_MOVE, 0);
2017 /* Compute the result. */
2018 op0 = State.regs[ OP[0] ];
2019 result = ~op0;
2020
2021 /* Compute the condition codes. */
2022 z = (result == 0);
2023 s = (result & 0x80000000);
2024
2025 /* Store the result and condition codes. */
2026 State.regs[OP[1]] = result;
2027 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2028 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2029 trace_output (OP_REG_REG_MOVE);
2030
2031 return 2;
2032 }
2033
2034 /* set1 */
2035 int
2036 OP_7C0 ()
2037 {
2038 unsigned int op0, op1, op2;
2039 int temp;
2040
2041 trace_input ("set1", OP_BIT, 0);
2042 op0 = State.regs[ OP[0] ];
2043 op1 = OP[1] & 0x7;
2044 temp = SEXT16 (OP[2]);
2045 op2 = temp;
2046 temp = load_mem (op0 + op2, 1);
2047 PSW &= ~PSW_Z;
2048 if ((temp & (1 << op1)) == 0)
2049 PSW |= PSW_Z;
2050 temp |= (1 << op1);
2051 store_mem (op0 + op2, 1, temp);
2052 trace_output (OP_BIT);
2053
2054 return 4;
2055 }
2056
2057 /* not1 */
2058 int
2059 OP_47C0 ()
2060 {
2061 unsigned int op0, op1, op2;
2062 int temp;
2063
2064 trace_input ("not1", OP_BIT, 0);
2065 op0 = State.regs[ OP[0] ];
2066 op1 = OP[1] & 0x7;
2067 temp = SEXT16 (OP[2]);
2068 op2 = temp;
2069 temp = load_mem (op0 + op2, 1);
2070 PSW &= ~PSW_Z;
2071 if ((temp & (1 << op1)) == 0)
2072 PSW |= PSW_Z;
2073 temp ^= (1 << op1);
2074 store_mem (op0 + op2, 1, temp);
2075 trace_output (OP_BIT);
2076
2077 return 4;
2078 }
2079
2080 /* clr1 */
2081 int
2082 OP_87C0 ()
2083 {
2084 unsigned int op0, op1, op2;
2085 int temp;
2086
2087 trace_input ("clr1", OP_BIT, 0);
2088 op0 = State.regs[ OP[0] ];
2089 op1 = OP[1] & 0x7;
2090 temp = SEXT16 (OP[2]);
2091 op2 = temp;
2092 temp = load_mem (op0 + op2, 1);
2093 PSW &= ~PSW_Z;
2094 if ((temp & (1 << op1)) == 0)
2095 PSW |= PSW_Z;
2096 temp &= ~(1 << op1);
2097 store_mem (op0 + op2, 1, temp);
2098 trace_output (OP_BIT);
2099
2100 return 4;
2101 }
2102
2103 /* tst1 */
2104 int
2105 OP_C7C0 ()
2106 {
2107 unsigned int op0, op1, op2;
2108 int temp;
2109
2110 trace_input ("tst1", OP_BIT, 0);
2111 op0 = State.regs[ OP[0] ];
2112 op1 = OP[1] & 0x7;
2113 temp = SEXT16 (OP[2]);
2114 op2 = temp;
2115 temp = load_mem (op0 + op2, 1);
2116 PSW &= ~PSW_Z;
2117 if ((temp & (1 << op1)) == 0)
2118 PSW |= PSW_Z;
2119 trace_output (OP_BIT);
2120
2121 return 4;
2122 }
2123
2124 /* breakpoint */
2125 int
2126 OP_FFFF ()
2127 {
2128 State.exception = SIGTRAP;
2129 return -4;
2130 }
2131
2132 /* di */
2133 int
2134 OP_16007E0 ()
2135 {
2136 trace_input ("di", OP_NONE, 0);
2137 PSW |= PSW_ID;
2138 trace_output (OP_NONE);
2139
2140 return 4;
2141 }
2142
2143 /* ei */
2144 int
2145 OP_16087E0 ()
2146 {
2147 trace_input ("ei", OP_NONE, 0);
2148 PSW &= ~PSW_ID;
2149 trace_output (OP_NONE);
2150
2151 return 4;
2152 }
2153
2154 /* halt */
2155 int
2156 OP_12007E0 ()
2157 {
2158 trace_input ("halt", OP_NONE, 0);
2159 /* FIXME this should put processor into a mode where NMI still handled */
2160 State.exception = SIGQUIT;
2161 trace_output (OP_NONE);
2162
2163 return 4;
2164 }
2165
2166 /* reti */
2167 int
2168 OP_14007E0 ()
2169 {
2170 trace_input ("reti", OP_NONE, 0);
2171 trace_output (OP_NONE);
2172
2173 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
2174 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
2175 {
2176 PC = FEPC - 4;
2177 PSW = FEPSW;
2178 }
2179 else
2180 {
2181 PC = EIPC - 4;
2182 PSW = EIPSW;
2183 }
2184
2185 return 0;
2186 }
2187
2188 /* trap */
2189 int
2190 OP_10007E0 ()
2191 {
2192 trace_input ("trap", OP_TRAP, 0);
2193 trace_output (OP_TRAP);
2194
2195 /* Trap 31 is used for simulating OS I/O functions */
2196
2197 if (OP[0] == 31)
2198 {
2199 int save_errno = errno;
2200 errno = 0;
2201
2202 /* Registers passed to trap 0 */
2203
2204 #define FUNC State.regs[6] /* function number, return value */
2205 #define PARM1 State.regs[7] /* optional parm 1 */
2206 #define PARM2 State.regs[8] /* optional parm 2 */
2207 #define PARM3 State.regs[9] /* optional parm 3 */
2208
2209 /* Registers set by trap 0 */
2210
2211 #define RETVAL State.regs[10] /* return value */
2212 #define RETERR State.regs[11] /* return error code */
2213
2214 /* Turn a pointer in a register into a pointer into real memory. */
2215
2216 #define MEMPTR(x) (map (x))
2217
2218 switch (FUNC)
2219 {
2220 #if !defined(__GO32__) && !defined(_WIN32)
2221 case SYS_fork:
2222 RETVAL = fork ();
2223 break;
2224 case SYS_execve:
2225 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2226 (char **)MEMPTR (PARM3));
2227 break;
2228 #ifdef SYS_execv
2229 case SYS_execv:
2230 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2231 break;
2232 #endif
2233 #if 0
2234 case SYS_pipe:
2235 {
2236 reg_t buf;
2237 int host_fd[2];
2238
2239 buf = PARM1;
2240 RETVAL = pipe (host_fd);
2241 SW (buf, host_fd[0]);
2242 buf += sizeof(uint16);
2243 SW (buf, host_fd[1]);
2244 }
2245 break;
2246
2247 case SYS_wait:
2248 {
2249 int status;
2250
2251 RETVAL = wait (&status);
2252 SW (PARM1, status);
2253 }
2254 break;
2255 #endif
2256 #endif
2257
2258 case SYS_read:
2259 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
2260 PARM3);
2261 break;
2262 case SYS_write:
2263 if (PARM1 == 1)
2264 RETVAL = (int)v850_callback->write_stdout (v850_callback,
2265 MEMPTR (PARM2), PARM3);
2266 else
2267 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
2268 MEMPTR (PARM2), PARM3);
2269 break;
2270 case SYS_lseek:
2271 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
2272 break;
2273 case SYS_close:
2274 RETVAL = v850_callback->close (v850_callback, PARM1);
2275 break;
2276 case SYS_open:
2277 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
2278 break;
2279 case SYS_exit:
2280 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2281 State.exception = PARM1 & 0xffff; /* get signal encoded by kill */
2282 else if (PARM1 == 0xdead)
2283 State.exception = SIGABRT; /* old libraries */
2284 else
2285 State.exception = SIG_V850_EXIT; /* PARM1 has exit status encoded */
2286 break;
2287
2288 #if !defined(__GO32__) && !defined(_WIN32)
2289 case SYS_stat: /* added at hmsi */
2290 /* stat system call */
2291 {
2292 struct stat host_stat;
2293 reg_t buf;
2294
2295 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2296
2297 buf = PARM2;
2298
2299 /* Just wild-assed guesses. */
2300 store_mem (buf, 2, host_stat.st_dev);
2301 store_mem (buf + 2, 2, host_stat.st_ino);
2302 store_mem (buf + 4, 4, host_stat.st_mode);
2303 store_mem (buf + 8, 2, host_stat.st_nlink);
2304 store_mem (buf + 10, 2, host_stat.st_uid);
2305 store_mem (buf + 12, 2, host_stat.st_gid);
2306 store_mem (buf + 14, 2, host_stat.st_rdev);
2307 store_mem (buf + 16, 4, host_stat.st_size);
2308 store_mem (buf + 20, 4, host_stat.st_atime);
2309 store_mem (buf + 28, 4, host_stat.st_mtime);
2310 store_mem (buf + 36, 4, host_stat.st_ctime);
2311 }
2312 break;
2313
2314 case SYS_chown:
2315 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2316 break;
2317 case SYS_chmod:
2318 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2319 break;
2320 #ifdef SYS_time
2321 case SYS_time:
2322 {
2323 time_t now;
2324 RETVAL = time (&now);
2325 store_mem (PARM1, 4, now);
2326 }
2327 break;
2328 #endif
2329 #ifdef SYS_times
2330 case SYS_times:
2331 {
2332 struct tms tms;
2333 RETVAL = times (&tms);
2334 store_mem (PARM1, 4, tms.tms_utime);
2335 store_mem (PARM1 + 4, 4, tms.tms_stime);
2336 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2337 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2338 break;
2339 }
2340 #endif
2341 case SYS_gettimeofday:
2342 {
2343 struct timeval t;
2344 struct timezone tz;
2345 RETVAL = gettimeofday (&t, &tz);
2346 store_mem (PARM1, 4, t.tv_sec);
2347 store_mem (PARM1 + 4, 4, t.tv_usec);
2348 store_mem (PARM2, 4, tz.tz_minuteswest);
2349 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2350 break;
2351 }
2352 #ifdef SYS_utime
2353 case SYS_utime:
2354 /* Cast the second argument to void *, to avoid type mismatch
2355 if a prototype is present. */
2356 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2357 break;
2358 #endif
2359 #endif
2360 default:
2361 abort ();
2362 }
2363 RETERR = errno;
2364 errno = save_errno;
2365
2366 return 4;
2367 }
2368 else
2369 { /* Trap 0 -> 30 */
2370 EIPC = PC + 4;
2371 EIPSW = PSW;
2372 /* Mask out EICC */
2373 ECR &= 0xffff0000;
2374 ECR |= 0x40 + OP[0];
2375 /* Flag that we are now doing exception processing. */
2376 PSW |= PSW_EP | PSW_ID;
2377 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2378
2379 return 0;
2380 }
2381 }
2382
2383 /* ldsr, reg,reg */
2384 int
2385 OP_2007E0 ()
2386 {
2387 trace_input ("ldsr", OP_LDSR, 0);
2388
2389 State.sregs[ OP[1] ] = State.regs[ OP[0] ];
2390
2391 trace_output (OP_LDSR);
2392
2393 return 4;
2394 }
2395
2396 /* stsr */
2397 int
2398 OP_4007E0 ()
2399 {
2400 unsigned int op0;
2401
2402 trace_input ("stsr", OP_STSR, 0);
2403
2404 State.regs[ OP[1] ] = State.sregs[ OP[0] ];
2405
2406 trace_output (OP_STSR);
2407
2408 return 4;
2409 }
2410
2411 /* tst1 reg2, [reg1] */
2412 int
2413 OP_E607E0 (void)
2414 {
2415 int temp;
2416
2417 trace_input ("tst1", OP_BIT_LOAD, 1);
2418
2419 temp = load_mem (State.regs[ OP[0] ], 1);
2420
2421 PSW &= ~PSW_Z;
2422 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
2423 PSW |= PSW_Z;
2424
2425 trace_output (OP_BIT_LOAD);
2426
2427 return 4;
2428 }
2429
2430 /* start-sanitize-v850e */
2431
2432 #define BIT_CHANGE_OP( name, binop ) \
2433 unsigned int bit; \
2434 unsigned int temp; \
2435 \
2436 trace_input (name, OP_BIT_CHANGE, 0); \
2437 \
2438 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2439 temp = load_mem (State.regs[ OP[0] ], 1); \
2440 \
2441 PSW &= ~PSW_Z; \
2442 if ((temp & bit) == 0) \
2443 PSW |= PSW_Z; \
2444 temp binop bit; \
2445 \
2446 store_mem (State.regs[ OP[0] ], 1, temp); \
2447 \
2448 trace_output (OP_BIT_CHANGE); \
2449 \
2450 return 4;
2451
2452 /* clr1 reg2, [reg1] */
2453 int
2454 OP_E407E0 (void)
2455 {
2456 BIT_CHANGE_OP ("clr1", &= ~ );
2457 }
2458
2459 /* not1 reg2, [reg1] */
2460 int
2461 OP_E207E0 (void)
2462 {
2463 BIT_CHANGE_OP ("not1", ^= );
2464 }
2465
2466 /* set1 */
2467 int
2468 OP_E007E0 (void)
2469 {
2470 BIT_CHANGE_OP ("set1", |= );
2471 }
2472
2473 /* sasf */
2474 int
2475 OP_20007E0 (void)
2476 {
2477 trace_input ("sasf", OP_EX1, 0);
2478
2479 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2480
2481 trace_output (OP_EX1);
2482
2483 return 4;
2484 }
2485 /* end-sanitize-v850e */
2486
2487 /* start-sanitize-v850eq */
2488 /* sdivun imm5, reg1, reg2, reg3 */
2489 int
2490 OP_1C207E0 (void)
2491 {
2492 unsigned long long int quotient;
2493 unsigned long long int remainder;
2494 unsigned long long int divisor;
2495 unsigned long long int dividend;
2496 boolean overflow = false;
2497 unsigned int imm5;
2498
2499 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2500
2501 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2502
2503 divisor = State.regs[ OP[0] ] << imm5;
2504 dividend = State.regs[ OP[1] ];
2505
2506 State.regs[ OP[1] ] = quotient = dividend / divisor;
2507 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2508
2509 if (divisor == 0)
2510 {
2511 overflow = true;
2512 quotient = dividend;
2513 }
2514
2515 /* Set condition codes. */
2516 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2517
2518 if (overflow) PSW |= PSW_OV;
2519 if (quotient == 0) PSW |= PSW_Z;
2520
2521 trace_output (OP_IMM_REG_REG_REG);
2522
2523 return 4;
2524 }
2525
2526 /* sdivn imm5, reg1, reg2, reg3 */
2527 int
2528 OP_1C007E0 (void)
2529 {
2530 signed long long int quotient;
2531 signed long long int remainder;
2532 signed long long int divisor;
2533 signed long long int dividend;
2534 boolean overflow = false;
2535 unsigned int imm5;
2536
2537 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2538
2539 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2540
2541 divisor = State.regs[ OP[0] ] << imm5;
2542 dividend = State.regs[ OP[1] ];
2543
2544 State.regs[ OP[1] ] = quotient = dividend / divisor;
2545 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2546
2547 if (divisor == 0)
2548 {
2549 overflow = true;
2550 quotient = dividend;
2551 }
2552
2553 /* Set condition codes. */
2554 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2555
2556 if (overflow) PSW |= PSW_OV;
2557 if (quotient == 0) PSW |= PSW_Z;
2558 if (quotient < 0) PSW |= PSW_S;
2559
2560 trace_output (OP_IMM_REG_REG_REG);
2561
2562 return 4;
2563 }
2564
2565 /* sdivhun imm5, reg1, reg2, reg3 */
2566 int
2567 OP_18207E0 (void)
2568 {
2569 unsigned long long int quotient;
2570 unsigned long long int remainder;
2571 unsigned long long int divisor;
2572 unsigned long long int dividend;
2573 boolean overflow = false;
2574 unsigned int imm5;
2575
2576 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2577
2578 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2579
2580 divisor = State.regs[ OP[0] ] << imm5;
2581 dividend = State.regs[ OP[1] ] & 0xffff;
2582
2583 State.regs[ OP[1] ] = quotient = dividend / divisor;
2584 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2585
2586 if (divisor == 0)
2587 {
2588 overflow = true;
2589 quotient = dividend;
2590 }
2591
2592 /* Set condition codes. */
2593 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2594
2595 if (overflow) PSW |= PSW_OV;
2596 if (quotient == 0) PSW |= PSW_Z;
2597
2598 trace_output (OP_IMM_REG_REG_REG);
2599
2600 return 4;
2601 }
2602
2603 /* sdivhn imm5, reg1, reg2, reg3 */
2604 int
2605 OP_18007E0 (void)
2606 {
2607 signed long long int quotient;
2608 signed long long int remainder;
2609 signed long long int divisor;
2610 signed long long int dividend;
2611 boolean overflow = false;
2612 unsigned int imm5;
2613
2614 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2615
2616 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2617
2618 divisor = State.regs[ OP[0] ] << imm5;
2619 dividend = SEXT16 (State.regs[ OP[1] ]);
2620
2621 State.regs[ OP[1] ] = quotient = dividend / divisor;
2622 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2623
2624 if (divisor == 0)
2625 {
2626 overflow = true;
2627 quotient = dividend;
2628 }
2629
2630 /* Set condition codes. */
2631 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2632
2633 if (overflow) PSW |= PSW_OV;
2634 if (quotient == 0) PSW |= PSW_Z;
2635 if (quotient < 0) PSW |= PSW_S;
2636
2637 trace_output (OP_IMM_REG_REG_REG);
2638
2639 return 4;
2640 }
2641 /* end-sanitize-v850eq */
2642
2643 /* start-sanitize-v850e */
2644 /* divu reg1, reg2, reg3 */
2645 /* divun imm5, reg1, reg2, reg3 */
2646 int
2647 OP_2C207E0 (void)
2648 {
2649 unsigned long int quotient;
2650 unsigned long int remainder;
2651 unsigned long int divisor;
2652 unsigned long int dividend;
2653 boolean overflow = false;
2654
2655 if ((OP[3] & 0x3c0000) == 0)
2656 {
2657 trace_input ("divu", OP_REG_REG_REG, 0);
2658
2659 /* Compute the result. */
2660
2661 divisor = State.regs[ OP[0] ];
2662 dividend = State.regs[ OP[1] ];
2663
2664 if (divisor == 0)
2665 {
2666 overflow = true;
2667 divisor = 1;
2668 }
2669
2670 State.regs[ OP[1] ] = quotient = dividend / divisor;
2671 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2672
2673 /* Set condition codes. */
2674 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2675
2676 if (overflow) PSW |= PSW_OV;
2677 if (quotient == 0) PSW |= PSW_Z;
2678
2679 trace_output (OP_REG_REG_REG);
2680 }
2681 /* start-sanitize-v850eq */
2682 else
2683 {
2684 unsigned int imm5;
2685
2686 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
2687
2688 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2689
2690 divisor = State.regs[ OP[0] ];
2691 dividend = State.regs[ OP[1] ];
2692
2693 State.regs[ OP[1] ] = quotient = dividend / divisor;
2694 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2695
2696 if ((divisor == 0)
2697 || (quotient > (1 << imm5))
2698 || (quotient < (((imm5 & 1) ? 1 : -1) << imm5)))
2699 {
2700 overflow = true;
2701 quotient = dividend;
2702 }
2703
2704 /* Set condition codes. */
2705 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2706
2707 if (overflow) PSW |= PSW_OV;
2708 if (quotient == 0) PSW |= PSW_Z;
2709
2710 trace_output (OP_IMM_REG_REG_REG);
2711 }
2712 /* end-sanitize-v850eq */
2713
2714 return 4;
2715 }
2716
2717 /* div reg1, reg2, reg3 */
2718 /* divn imm5, reg1, reg2, reg3 */
2719 int
2720 OP_2C007E0 (void)
2721 {
2722 signed long int quotient;
2723 signed long int remainder;
2724 signed long int divisor;
2725 signed long int dividend;
2726 boolean overflow = false;
2727
2728 if ((OP[3] & 0x3c0000) == 0)
2729 {
2730 trace_input ("div", OP_REG_REG_REG, 0);
2731
2732 /* Compute the result. */
2733
2734 divisor = State.regs[ OP[0] ];
2735 dividend = State.regs[ OP[1] ];
2736
2737 if (divisor == 0 || (divisor == -1 && dividend == (1 << 31)))
2738 {
2739 overflow = true;
2740 divisor = 1;
2741 }
2742
2743 State.regs[ OP[1] ] = quotient = dividend / divisor;
2744 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2745
2746 /* Set condition codes. */
2747 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2748
2749 if (overflow) PSW |= PSW_OV;
2750 if (quotient == 0) PSW |= PSW_Z;
2751 if (quotient < 0) PSW |= PSW_S;
2752
2753 trace_output (OP_REG_REG_REG);
2754 }
2755 /* start-sanitize-v850eq */
2756 else
2757 {
2758 unsigned int imm5;
2759
2760 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
2761
2762 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2763
2764 divisor = State.regs[ OP[0] ];
2765 dividend = State.regs[ OP[1] ];
2766
2767 State.regs[ OP[1] ] = quotient = dividend / divisor;
2768 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2769
2770 if ((divisor == 0)
2771 || (quotient > (1 << imm5))
2772 || (divisor == -1 && dividend == (1 << 31))
2773 || (quotient < (((imm5 & 1) ? 1 : -1) << imm5)))
2774 {
2775 overflow = true;
2776 quotient = dividend;
2777 }
2778
2779 /* Set condition codes. */
2780 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2781
2782 if (overflow) PSW |= PSW_OV;
2783 if (quotient == 0) PSW |= PSW_Z;
2784 if (quotient < 0) PSW |= PSW_S;
2785
2786 trace_output (OP_IMM_REG_REG_REG);
2787 }
2788 /* end-sanitize-v850eq */
2789
2790 return 4;
2791 }
2792
2793 /* divhu reg1, reg2, reg3 */
2794 /* divhun imm5, reg1, reg2, reg3 */
2795 int
2796 OP_28207E0 (void)
2797 {
2798 unsigned long int quotient;
2799 unsigned long int remainder;
2800 unsigned long int divisor;
2801 unsigned long int dividend;
2802 boolean overflow = false;
2803
2804 if ((OP[3] & 0x3c0000) == 0)
2805 {
2806 trace_input ("divhu", OP_REG_REG_REG, 0);
2807
2808 /* Compute the result. */
2809
2810 divisor = State.regs[ OP[0] ];
2811 dividend = State.regs[ OP[1] ] & 0xffff;
2812
2813 if (divisor == 0)
2814 {
2815 overflow = true;
2816 divisor = 1;
2817 }
2818
2819 State.regs[ OP[1] ] = quotient = dividend / divisor;
2820 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2821
2822 /* Set condition codes. */
2823 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2824
2825 if (overflow) PSW |= PSW_OV;
2826 if (quotient == 0) PSW |= PSW_Z;
2827
2828 trace_output (OP_REG_REG_REG);
2829 }
2830 /* start-sanitize-v850eq */
2831 else
2832 {
2833 unsigned int imm5;
2834
2835 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
2836
2837 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2838
2839 divisor = State.regs[ OP[0] ];
2840 dividend = State.regs[ OP[1] ] & 0xffff;
2841
2842 State.regs[ OP[1] ] = quotient = dividend / divisor;
2843 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2844
2845 if ((divisor == 0)
2846 || (quotient > (1 << imm5))
2847 || (quotient < (((imm5 & 1) ? 1 : -1) << imm5)))
2848 {
2849 overflow = true;
2850 quotient = dividend;
2851 }
2852
2853 /* Set condition codes. */
2854 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2855
2856 if (overflow) PSW |= PSW_OV;
2857 if (quotient == 0) PSW |= PSW_Z;
2858
2859 trace_output (OP_IMM_REG_REG_REG);
2860 }
2861 /* end-sanitize-v850eq */
2862
2863 return 4;
2864 }
2865
2866 /* divh reg1, reg2, reg3 */
2867 /* divhn imm5, reg1, reg2, reg3 */
2868 int
2869 OP_28007E0 (void)
2870 {
2871 signed long int quotient;
2872 signed long int remainder;
2873 signed long int divisor;
2874 signed long int dividend;
2875 boolean overflow = false;
2876
2877 if ((OP[3] & 0x3c0000) == 0)
2878 {
2879 trace_input ("divh", OP_REG_REG_REG, 0);
2880
2881 /* Compute the result. */
2882
2883 divisor = State.regs[ OP[0] ];
2884 dividend = SEXT16 (State.regs[ OP[1] ]);
2885
2886 if (divisor == 0 || (divisor == -1 && dividend == (1 << 31)))
2887 {
2888 overflow = true;
2889 divisor = 1;
2890 }
2891
2892 State.regs[ OP[1] ] = quotient = dividend / divisor;
2893 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2894
2895 /* Set condition codes. */
2896 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2897
2898 if (overflow) PSW |= PSW_OV;
2899 if (quotient == 0) PSW |= PSW_Z;
2900 if (quotient < 0) PSW |= PSW_S;
2901
2902 trace_output (OP_REG_REG_REG);
2903 }
2904 /* start-sanitize-v850eq */
2905 else
2906 {
2907 unsigned int imm5;
2908
2909 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
2910
2911 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2912
2913 divisor = State.regs[ OP[0] ];
2914 dividend = SEXT16 (State.regs[ OP[1] ]);
2915
2916 State.regs[ OP[1] ] = quotient = dividend / divisor;
2917 State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
2918
2919 if ((divisor == 0)
2920 || (quotient > (1 << imm5))
2921 || (divisor == -1 && dividend == (1 << 31))
2922 || (quotient < (((imm5 & 1) ? 1 : -1) << imm5)))
2923 {
2924 overflow = true;
2925 quotient = dividend;
2926 }
2927
2928 /* Set condition codes. */
2929 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2930
2931 if (overflow) PSW |= PSW_OV;
2932 if (quotient == 0) PSW |= PSW_Z;
2933 if (quotient < 0) PSW |= PSW_S;
2934
2935 trace_output (OP_IMM_REG_REG_REG);
2936 }
2937 /* end-sanitize-v850eq */
2938
2939 return 4;
2940 }
2941
2942 /* mulu imm9, reg2, reg3 */
2943 int
2944 OP_24207E0 (void)
2945 {
2946 trace_input ("mulu", OP_IMM_REG_REG, 0);
2947
2948 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2949
2950 trace_output (OP_IMM_REG_REG);
2951
2952 return 4;
2953 }
2954
2955 /* end-sanitize-v850e */
2956
2957 /* mulu reg1, reg2, reg3 */
2958 int
2959 OP_22207E0 (void)
2960 {
2961 trace_input ("mulu", OP_REG_REG_REG, 0);
2962
2963 Multiply64 (false, State.regs[ OP[0] ]);
2964
2965 trace_output (OP_REG_REG_REG);
2966
2967 return 4;
2968 }
2969
2970 /* start-sanitize-v850e */
2971
2972 /* mul imm9, reg2, reg3 */
2973 int
2974 OP_24007E0 (void)
2975 {
2976 trace_input ("mul", OP_IMM_REG_REG, 0);
2977
2978 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2979
2980 trace_output (OP_IMM_REG_REG);
2981
2982 return 4;
2983 }
2984
2985 /* cmov imm5, reg2, reg3 */
2986 int
2987 OP_30007E0 (void)
2988 {
2989 trace_input ("cmov", OP_IMM_REG_REG, 0);
2990
2991 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
2992
2993 trace_output (OP_IMM_REG_REG);
2994
2995 return 4;
2996
2997 }
2998
2999 /* ctret */
3000 int
3001 OP_14407E0 (void)
3002 {
3003 trace_input ("ctret", OP_NONE, 0);
3004
3005 PC = CTPC;
3006 PSW = CTPSW;
3007
3008 trace_output (OP_NONE);
3009
3010 return 0;
3011 }
3012
3013 /* hsw */
3014 int
3015 OP_34407E0 (void)
3016 {
3017 unsigned long value;
3018
3019 trace_input ("hsw", OP_REG_REG3, 0);
3020
3021 value = State.regs[ OP[ 1 ] ];
3022 value >>= 16;
3023 value |= (State.regs[ OP[ 1 ] ] << 16);
3024
3025 State.regs[ OP[2] >> 11 ] = value;
3026
3027 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3028
3029 if (value == 0) PSW |= PSW_Z;
3030 if (value & 0x80000000) PSW |= PSW_S;
3031 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3032
3033 trace_output (OP_REG_REG3);
3034
3035 return 4;
3036 }
3037
3038 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
3039
3040 /* bsw */
3041 int
3042 OP_34007E0 (void)
3043 {
3044 unsigned long value;
3045
3046 trace_input ("bsw", OP_REG_REG3, 0);
3047
3048 value = State.regs[ OP[ 1 ] ];
3049 value >>= 24;
3050 value |= (State.regs[ OP[ 1 ] ] << 24);
3051 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
3052 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
3053
3054 State.regs[ OP[2] >> 11 ] = value;
3055
3056 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3057
3058 if (value == 0) PSW |= PSW_Z;
3059 if (value & 0x80000000) PSW |= PSW_S;
3060 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
3061
3062 trace_output (OP_REG_REG3);
3063
3064 return 4;
3065 }
3066
3067 /* bsh */
3068 int
3069 OP_34207E0 (void)
3070 {
3071 unsigned long value;
3072
3073 trace_input ("bsh", OP_REG_REG3, 0);
3074
3075 value = State.regs[ OP[ 1 ] ];
3076 value >>= 8;
3077 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
3078 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
3079
3080 State.regs[ OP[2] >> 11 ] = value;
3081
3082 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3083
3084 if (value == 0) PSW |= PSW_Z;
3085 if (value & 0x80000000) PSW |= PSW_S;
3086 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3087
3088 trace_output (OP_REG_REG3);
3089
3090 return 4;
3091 }
3092
3093 /* pushml list18 */
3094 /* ld.hu */
3095 int
3096 OP_107E0 (void)
3097 {
3098 if (OP[ 1 ] == 0)
3099 {
3100 int i;
3101
3102 trace_input ("pushml", OP_PUSHPOP3, 0);
3103
3104 if (OP[3] & (1 << 19))
3105 {
3106 SP -= 8;
3107
3108 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3109 {
3110 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3111 store_mem ( SP & ~ 3, 4, FEPSW);
3112 }
3113 else
3114 {
3115 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3116 store_mem ( SP & ~ 3, 4, EIPSW);
3117 }
3118 }
3119
3120 if (OP[3] & (1 << 3))
3121 {
3122 SP -= 4;
3123
3124 store_mem (SP & ~ 3, 4, PSW);
3125 }
3126
3127 /* Store the registers with lower number registers being placed at lower addresses. */
3128 for (i = 15; i--;)
3129 if ((OP[3] & (1 << type3_regs[ i ])))
3130 {
3131 SP -= 4;
3132 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
3133 }
3134
3135 trace_output (OP_PUSHPOP2);
3136 }
3137 else
3138 {
3139 int adr;
3140
3141 trace_input ("ld.hu", OP_LOAD32, 2);
3142
3143 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
3144 adr &= ~0x1;
3145
3146 State.regs[ OP[1] ] = load_mem (adr, 2);
3147
3148 trace_output (OP_LOAD32);
3149 }
3150
3151 return 4;
3152 }
3153
3154 /* prepare list12, imm5 */
3155 /* ld.bu */
3156 int
3157 OP_10780 (void)
3158 {
3159 if (OP[ 1 ] == 0)
3160 {
3161 int i;
3162
3163 trace_input ("prepare", OP_PUSHPOP1, 0);
3164
3165 /* Store the registers with lower number registers being placed at lower addresses. */
3166 for (i = 12; i--;)
3167 if ((OP[3] & (1 << type1_regs[ i ])))
3168 {
3169 SP -= 4;
3170 store_mem (SP, 4, State.regs[ 20 + i ]);
3171 }
3172
3173 SP -= (OP[3] & 0x3e) << 1;
3174
3175 trace_output (OP_PUSHPOP1);
3176 }
3177 else
3178 {
3179 int adr;
3180
3181 trace_input ("ld.bu", OP_LOAD32, 1);
3182
3183 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1) | ((OP[3] >> 5) & 1);
3184
3185 State.regs[ OP[1] ] = load_mem (adr, 1);
3186
3187 trace_output (OP_LOAD32);
3188 }
3189
3190 return 4;
3191 }
3192
3193 /* prepare list12, imm5, imm32 */
3194 int
3195 OP_1B0780 (void)
3196 {
3197 int i;
3198
3199 trace_input ("prepare", OP_PUSHPOP1, 0);
3200
3201 /* Store the registers with lower number registers being placed at lower addresses. */
3202 for (i = 12; i--;)
3203 if ((OP[3] & (1 << type1_regs[ i ])))
3204 {
3205 SP -= 4;
3206 store_mem (SP, 4, State.regs[ 20 + i ]);
3207 }
3208
3209 SP -= (OP[3] & 0x3e) << 1;
3210
3211 EP = load_mem (PC + 4, 4);
3212
3213 trace_output (OP_PUSHPOP1);
3214
3215 return 8;
3216 }
3217
3218 /* prepare list12, imm5, imm16-32 */
3219 int
3220 OP_130780 (void)
3221 {
3222 int i;
3223
3224 trace_input ("prepare", OP_PUSHPOP1, 0);
3225
3226 /* Store the registers with lower number registers being placed at lower addresses. */
3227 for (i = 12; i--;)
3228 if ((OP[3] & (1 << type1_regs[ i ])))
3229 {
3230 SP -= 4;
3231 store_mem (SP, 4, State.regs[ 20 + i ]);
3232 }
3233
3234 SP -= (OP[3] & 0x3e) << 1;
3235
3236 EP = load_mem (PC + 4, 2) << 16;
3237
3238 trace_output (OP_PUSHPOP1);
3239
3240 return 6;
3241 }
3242
3243 /* prepare list12, imm5, imm16 */
3244 int
3245 OP_B0780 (void)
3246 {
3247 int i;
3248
3249 trace_input ("prepare", OP_PUSHPOP1, 0);
3250
3251 /* Store the registers with lower number registers being placed at lower addresses. */
3252 for (i = 12; i--;)
3253 if ((OP[3] & (1 << type1_regs[ i ])))
3254 {
3255 SP -= 4;
3256 store_mem (SP, 4, State.regs[ 20 + i ]);
3257 }
3258
3259 SP -= (OP[3] & 0x3e) << 1;
3260
3261 EP = SEXT16 (load_mem (PC + 4, 2));
3262
3263 trace_output (OP_PUSHPOP1);
3264
3265 return 6;
3266 }
3267
3268 /* prepare list12, imm5, sp */
3269 int
3270 OP_30780 (void)
3271 {
3272 int i;
3273
3274 trace_input ("prepare", OP_PUSHPOP1, 0);
3275
3276 /* Store the registers with lower number registers being placed at lower addresses. */
3277 for (i = 12; i--;)
3278 if ((OP[3] & (1 << type1_regs[ i ])))
3279 {
3280 SP -= 4;
3281 store_mem (SP, 4, State.regs[ 20 + i ]);
3282 }
3283
3284 SP -= (OP[3] & 0x3e) << 1;
3285
3286 EP = SP;
3287
3288 trace_output (OP_PUSHPOP1);
3289
3290 return 4;
3291 }
3292
3293 /* end-sanitize-v850e */
3294 /* start-sanitize-v850eq */
3295
3296 /* popmh list18 */
3297 int
3298 OP_307F0 (void)
3299 {
3300 int i;
3301
3302 trace_input ("popmh", OP_PUSHPOP2, 0);
3303
3304 /* Load the registers with lower number registers being retrieved from lower addresses. */
3305 for (i = 0; i++; i < 16)
3306 if ((OP[3] & (1 << type2_regs[ i ])))
3307 {
3308 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
3309 SP += 4;
3310 }
3311
3312 if (OP[3] & (1 << 19))
3313 {
3314 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3315 {
3316 FEPSW = load_mem ( SP & ~ 3, 4);
3317 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3318 }
3319 else
3320 {
3321 EIPSW = load_mem ( SP & ~ 3, 4);
3322 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3323 }
3324
3325 SP += 8;
3326 }
3327
3328 trace_output (OP_PUSHPOP2);
3329
3330 return 4;
3331 }
3332
3333 /* popml lsit18 */
3334 int
3335 OP_107F0 (void)
3336 {
3337 int i;
3338
3339 trace_input ("popml", OP_PUSHPOP3, 0);
3340
3341 /* Load the registers with lower number registers being retrieved from lower addresses. */
3342 for (i = 0; i++; i < 15)
3343 if ((OP[3] & (1 << type3_regs[ i ])))
3344 {
3345 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
3346 SP += 4;
3347 }
3348
3349 if (OP[3] & (1 << 3))
3350 {
3351 PSW = load_mem (SP & ~ 3, 4);
3352 SP += 4;
3353 }
3354
3355 if (OP[3] & (1 << 19))
3356 {
3357 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3358 {
3359 FEPSW = load_mem ( SP & ~ 3, 4);
3360 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3361 }
3362 else
3363 {
3364 EIPSW = load_mem ( SP & ~ 3, 4);
3365 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3366 }
3367
3368 SP += 8;
3369 }
3370
3371 trace_output (OP_PUSHPOP2);
3372 }
3373
3374 /* pushmh list18 */
3375 int
3376 OP_307E0 (void)
3377 {
3378 int i;
3379
3380 trace_input ("pushmh", OP_PUSHPOP2, 0);
3381
3382 if (OP[3] & (1 << 19))
3383 {
3384 SP -= 8;
3385
3386 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3387 {
3388 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3389 store_mem ( SP & ~ 3, 4, FEPSW);
3390 }
3391 else
3392 {
3393 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3394 store_mem ( SP & ~ 3, 4, EIPSW);
3395 }
3396 }
3397
3398 /* Store the registers with lower number registers being placed at lower addresses. */
3399 for (i = 16; i--;)
3400 if ((OP[3] & (1 << type2_regs[ i ])))
3401 {
3402 SP -= 4;
3403 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
3404 }
3405
3406 trace_output (OP_PUSHPOP2);
3407
3408 return 4;
3409 }
3410
3411 /* end-sanitize-v850eq */
3412 /* start-sanitize-v850e */
3413
3414 /* sld.hu */
3415 int
3416 OP_70 (void)
3417 {
3418 unsigned long result;
3419
3420 result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
3421
3422 /* start-sanitize-v850eq */
3423 #ifdef ARCH_v850eq
3424 trace_input ("sld.h", OP_LOAD16, 2);
3425
3426 State.regs[ OP[1] ] = SEXT16 (result);
3427 #else
3428 /* end-sanitize-v850eq */
3429 trace_input ("sld.hu", OP_LOAD16, 2);
3430
3431 State.regs[ OP[1] ] = result;
3432 /* start-sanitize-v850eq */
3433 #endif
3434 /* end-sanitize-v850eq */
3435
3436 trace_output (OP_LOAD16);
3437
3438 return 2;
3439 }
3440
3441 /* cmov reg1, reg2, reg3 */
3442 int
3443 OP_32007E0 (void)
3444 {
3445 trace_input ("cmov", OP_REG_REG_REG, 0);
3446
3447 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
3448
3449 trace_output (OP_REG_REG_REG);
3450
3451 return 4;
3452 }
3453
3454 /* mul reg1, reg2, reg3 */
3455 int
3456 OP_22007E0 (void)
3457 {
3458 trace_input ("mul", OP_REG_REG_REG, 0);
3459
3460 Multiply64 (true, State.regs[ OP[0] ]);
3461
3462 trace_output (OP_REG_REG_REG);
3463
3464 return 4;
3465 }
3466
3467 /* end-sanitize-v850e */